[top] Expand ibex breakpoints to 4 - fixes #3850 Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson b/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson index 0f05f52..9070d43 100644 --- a/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson +++ b/hw/ip/rv_core_ibex/data/rv_core_ibex.hjson
@@ -317,6 +317,13 @@ expose: "true" }, + { name: "DbgHwBreakNum" + type: "int" + default: "1" + local: "false" + expose: "true" + }, + { name: "SecureIbex" type: "bit" default: "0"
diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv index 4cf7331..201293e 100644 --- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv +++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
@@ -29,6 +29,7 @@ parameter bit ICacheScramble = 1'b1, parameter bit BranchPredictor = 1'b1, parameter bit DbgTriggerEn = 1'b1, + parameter int unsigned DbgHwBreakNum = 1, parameter bit SecureIbex = 1'b1, parameter ibex_pkg::lfsr_seed_t RndCnstLfsrSeed = ibex_pkg::RndCnstLfsrSeedDefault, parameter ibex_pkg::lfsr_perm_t RndCnstLfsrPerm = ibex_pkg::RndCnstLfsrPermDefault, @@ -359,6 +360,7 @@ .ICacheScramble ( ICacheScramble ), .BranchPredictor ( BranchPredictor ), .DbgTriggerEn ( DbgTriggerEn ), + .DbgHwBreakNum ( DbgHwBreakNum ), // SEC_CM: LOGIC.SHADOW // SEC_CM: PC.CTRL_FLOW.CONSISTENCY, CTRL_FLOW.UNPREDICTABLE, CORE.DATA_REG_SW.SCA // SEC_CM: EXCEPTION.CTRL_FLOW.GLOBAL_ESC, EXCEPTION.CTRL_FLOW.LOCAL_ESC
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 318d80c..1583800 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -6999,6 +6999,7 @@ ICacheScramble: "1" BranchPredictor: "0" DbgTriggerEn: "1" + DbgHwBreakNum: "4" SecureIbex: "1" DmHaltAddr: tl_main_pkg::ADDR_SPACE_RV_DM__ROM + dm::HaltAddress[31:0] DmExceptionAddr: tl_main_pkg::ADDR_SPACE_RV_DM__ROM + dm::ExceptionAddress[31:0] @@ -7211,6 +7212,13 @@ name_top: RvCoreIbexDbgTriggerEn } { + name: DbgHwBreakNum + type: int + default: "4" + expose: "true" + name_top: RvCoreIbexDbgHwBreakNum + } + { name: SecureIbex type: bit default: "1"
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index 3bb9d8e..995a6d7 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -720,6 +720,7 @@ ICacheScramble: "1", BranchPredictor: "0", DbgTriggerEn: "1", + DbgHwBreakNum: "4", SecureIbex: "1", DmHaltAddr: "tl_main_pkg::ADDR_SPACE_RV_DM__ROM + dm::HaltAddress[31:0]", DmExceptionAddr: "tl_main_pkg::ADDR_SPACE_RV_DM__ROM + dm::ExceptionAddress[31:0]",
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 900be6a..d460813 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -101,6 +101,7 @@ parameter bit RvCoreIbexICacheScramble = 1, parameter bit RvCoreIbexBranchPredictor = 0, parameter bit RvCoreIbexDbgTriggerEn = 1, + parameter int RvCoreIbexDbgHwBreakNum = 4, parameter bit RvCoreIbexSecureIbex = 1, parameter int unsigned RvCoreIbexDmHaltAddr = tl_main_pkg::ADDR_SPACE_RV_DM__ROM + dm::HaltAddress[31:0], @@ -2531,6 +2532,7 @@ .ICacheScramble(RvCoreIbexICacheScramble), .BranchPredictor(RvCoreIbexBranchPredictor), .DbgTriggerEn(RvCoreIbexDbgTriggerEn), + .DbgHwBreakNum(RvCoreIbexDbgHwBreakNum), .SecureIbex(RvCoreIbexSecureIbex), .DmHaltAddr(RvCoreIbexDmHaltAddr), .DmExceptionAddr(RvCoreIbexDmExceptionAddr),