[dif] Clean up dif_spi_device.h to use new-style names
Signed-off-by: Miguel Young de la Sota <mcyoung@google.com>
diff --git a/sw/device/boot_rom/bootstrap.c b/sw/device/boot_rom/bootstrap.c
index 41e507c..8d98d8e 100644
--- a/sw/device/boot_rom/bootstrap.c
+++ b/sw/device/boot_rom/bootstrap.c
@@ -88,15 +88,13 @@
uint32_t expected_frame_num = 0;
while (true) {
size_t bytes_available;
- CHECK(dif_spi_device_rx_pending(spi, &bytes_available) ==
- kDifSpiDeviceResultOk,
+ CHECK(dif_spi_device_rx_pending(spi, &bytes_available) == kDifSpiDeviceOk,
"Failed to check pending bytes.");
if (bytes_available >= sizeof(spiflash_frame_t)) {
spiflash_frame_t frame;
- CHECK(
- dif_spi_device_recv(spi, &frame, sizeof(spiflash_frame_t),
- /*bytes_received=*/NULL) == kDifSpiDeviceResultOk,
- "Failed to recieve bytes from SPI.");
+ CHECK(dif_spi_device_recv(spi, &frame, sizeof(spiflash_frame_t),
+ /*bytes_received=*/NULL) == kDifSpiDeviceOk,
+ "Failed to recieve bytes from SPI.");
uint32_t frame_num = SPIFLASH_FRAME_NUM(frame.header.frame_num);
LOG_INFO("Processing frame #%d, expecting #%d", frame_num,
@@ -106,16 +104,14 @@
if (!check_frame_hash(&frame)) {
LOG_ERROR("Detected hash mismatch on frame #%d", frame_num);
CHECK(dif_spi_device_send(spi, ack, sizeof(ack),
- /*bytes_received=*/NULL) ==
- kDifSpiDeviceResultOk,
+ /*bytes_received=*/NULL) == kDifSpiDeviceOk,
"Failed to send bytes to SPI.");
continue;
}
hw_SHA256_hash(&frame, sizeof(spiflash_frame_t), ack);
CHECK(dif_spi_device_send(spi, ack, sizeof(ack),
- /*bytes_received=*/NULL) ==
- kDifSpiDeviceResultOk,
+ /*bytes_received=*/NULL) == kDifSpiDeviceOk,
"Failed to send bytes to SPI.");
if (expected_frame_num == 0) {
@@ -141,8 +137,7 @@
} else {
// Send previous ack if unable to verify current frame.
CHECK(dif_spi_device_send(spi, ack, sizeof(ack),
- /*bytes_received=*/NULL) ==
- kDifSpiDeviceResultOk,
+ /*bytes_received=*/NULL) == kDifSpiDeviceOk,
"Failed to send bytes to SPI.");
}
}
@@ -158,19 +153,25 @@
LOG_INFO("Bootstrap requested, initialising HW...");
flash_init_block();
- mmio_region_t spi_reg = mmio_region_from_addr(0x40020000);
- dif_spi_device_config_t config = {
- .clock_polarity = kDifSpiDeviceEdgePositive,
- .data_phase = kDifSpiDeviceEdgeNegative,
- .tx_order = kDifSpiDeviceBitOrderMsbToLsb,
- .rx_order = kDifSpiDeviceBitOrderMsbToLsb,
- .rx_fifo_timeout = 63,
- .rx_fifo_len = kDifSpiDeviceBufferLen / 2,
- .tx_fifo_len = kDifSpiDeviceBufferLen / 2,
- };
dif_spi_device_t spi;
- CHECK(dif_spi_device_init(spi_reg, &config, &spi) == kDifSpiDeviceResultOk,
+ CHECK(dif_spi_device_init(
+ (dif_spi_device_params_t){
+ .base_addr = mmio_region_from_addr(0x40020000),
+ },
+ &spi),
"Failed to initialize SPI.");
+ CHECK(
+ dif_spi_device_configure(&spi,
+ (dif_spi_device_config_t){
+ .clock_polarity = kDifSpiDeviceEdgePositive,
+ .data_phase = kDifSpiDeviceEdgeNegative,
+ .tx_order = kDifSpiDeviceBitOrderMsbToLsb,
+ .rx_order = kDifSpiDeviceBitOrderMsbToLsb,
+ .rx_fifo_timeout = 63,
+ .rx_fifo_len = kDifSpiDeviceBufferLen / 2,
+ .tx_fifo_len = kDifSpiDeviceBufferLen / 2,
+ }) == kDifSpiDeviceOk,
+ "Failed to configure SPI.");
LOG_INFO("HW initialisation completed, waiting for SPI input...");
int error = bootstrap_flash(&spi);
diff --git a/sw/device/examples/demos.c b/sw/device/examples/demos.c
index 61679dc..1506bfe 100644
--- a/sw/device/examples/demos.c
+++ b/sw/device/examples/demos.c
@@ -66,11 +66,11 @@
uint32_t spi_buf[8];
size_t spi_len;
CHECK(dif_spi_device_recv(spi, spi_buf, sizeof(spi_buf), &spi_len) ==
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
if (spi_len > 0) {
uint32_t echo_word = spi_buf[0] ^ 0x01010101;
CHECK(dif_spi_device_send(spi, &echo_word, sizeof(uint32_t),
- /*bytes_sent=*/NULL) == kDifSpiDeviceResultOk);
+ /*bytes_sent=*/NULL) == kDifSpiDeviceOk);
LOG_INFO("SPI: %z", spi_len, spi_buf);
}
}
diff --git a/sw/device/examples/hello_usbdev/hello_usbdev.c b/sw/device/examples/hello_usbdev/hello_usbdev.c
index 49c8e7a..37b3580 100644
--- a/sw/device/examples/hello_usbdev/hello_usbdev.c
+++ b/sw/device/examples/hello_usbdev/hello_usbdev.c
@@ -104,18 +104,21 @@
pinmux_init();
- mmio_region_t spi_reg = mmio_region_from_addr(0x40020000);
- dif_spi_device_config_t spi_config = {
- .clock_polarity = kDifSpiDeviceEdgePositive,
- .data_phase = kDifSpiDeviceEdgeNegative,
- .tx_order = kDifSpiDeviceBitOrderMsbToLsb,
- .rx_order = kDifSpiDeviceBitOrderMsbToLsb,
- .rx_fifo_timeout = 63,
- .rx_fifo_len = kDifSpiDeviceBufferLen / 2,
- .tx_fifo_len = kDifSpiDeviceBufferLen / 2,
- };
- CHECK(dif_spi_device_init(spi_reg, &spi_config, &spi) ==
- kDifSpiDeviceResultOk);
+ CHECK(dif_spi_device_init(
+ (dif_spi_device_params_t){
+ .base_addr = mmio_region_from_addr(0x40020000),
+ },
+ &spi));
+ CHECK(dif_spi_device_configure(
+ &spi, (dif_spi_device_config_t){
+ .clock_polarity = kDifSpiDeviceEdgePositive,
+ .data_phase = kDifSpiDeviceEdgeNegative,
+ .tx_order = kDifSpiDeviceBitOrderMsbToLsb,
+ .rx_order = kDifSpiDeviceBitOrderMsbToLsb,
+ .rx_fifo_timeout = 63,
+ .rx_fifo_len = kDifSpiDeviceBufferLen / 2,
+ .tx_fifo_len = kDifSpiDeviceBufferLen / 2,
+ }) == kDifSpiDeviceOk);
dif_gpio_params_t gpio_params = {
.base_addr = mmio_region_from_addr(0x40010000),
@@ -145,7 +148,7 @@
usb_simpleserial_init(&simple_serial1, &usbdev, 2, usb_receipt_callback_1);
CHECK(dif_spi_device_send(&spi, "SPI!", 4, /*bytes_sent=*/NULL) ==
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
bool say_hello = true;
bool pass_signaled = false;
diff --git a/sw/device/examples/hello_world/hello_world.c b/sw/device/examples/hello_world/hello_world.c
index 9a37ae0..903fbfb 100644
--- a/sw/device/examples/hello_world/hello_world.c
+++ b/sw/device/examples/hello_world/hello_world.c
@@ -22,18 +22,21 @@
pinmux_init();
- mmio_region_t spi_reg = mmio_region_from_addr(0x40020000);
- dif_spi_device_config_t spi_config = {
- .clock_polarity = kDifSpiDeviceEdgePositive,
- .data_phase = kDifSpiDeviceEdgeNegative,
- .tx_order = kDifSpiDeviceBitOrderMsbToLsb,
- .rx_order = kDifSpiDeviceBitOrderMsbToLsb,
- .rx_fifo_timeout = 63,
- .rx_fifo_len = kDifSpiDeviceBufferLen / 2,
- .tx_fifo_len = kDifSpiDeviceBufferLen / 2,
- };
- CHECK(dif_spi_device_init(spi_reg, &spi_config, &spi) ==
- kDifSpiDeviceResultOk);
+ CHECK(dif_spi_device_init(
+ (dif_spi_device_params_t){
+ .base_addr = mmio_region_from_addr(0x40020000),
+ },
+ &spi));
+ CHECK(dif_spi_device_configure(
+ &spi, (dif_spi_device_config_t){
+ .clock_polarity = kDifSpiDeviceEdgePositive,
+ .data_phase = kDifSpiDeviceEdgeNegative,
+ .tx_order = kDifSpiDeviceBitOrderMsbToLsb,
+ .rx_order = kDifSpiDeviceBitOrderMsbToLsb,
+ .rx_fifo_timeout = 63,
+ .rx_fifo_len = kDifSpiDeviceBufferLen / 2,
+ .tx_fifo_len = kDifSpiDeviceBufferLen / 2,
+ }) == kDifSpiDeviceOk);
dif_gpio_params_t gpio_params = {
.base_addr = mmio_region_from_addr(0x40010000),
@@ -56,7 +59,7 @@
LOG_INFO("The LEDs show the ASCII code of the last character.");
CHECK(dif_spi_device_send(&spi, "SPI!", 4, /*bytes_sent=*/NULL) ==
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
uint32_t gpio_state = 0;
while (true) {
diff --git a/sw/device/lib/dif/dif_spi_device.c b/sw/device/lib/dif/dif_spi_device.c
index c97ba8a..c29e412 100644
--- a/sw/device/lib/dif/dif_spi_device.c
+++ b/sw/device/lib/dif/dif_spi_device.c
@@ -10,32 +10,44 @@
const uint16_t kDifSpiDeviceBufferLen = SPI_DEVICE_BUFFER_SIZE_BYTES;
+dif_spi_device_result_t dif_spi_device_init(dif_spi_device_params_t params,
+ dif_spi_device_t *spi) {
+ if (spi == NULL) {
+ return kDifSpiDeviceBadArg;
+ }
+
+ // This ensures all other fields are zeroed.
+ *spi = (dif_spi_device_t){.params = params};
+
+ return kDifSpiDeviceOk;
+}
+
/**
* Computes the required value of the control register from a given
* configuration.
*/
DIF_WARN_UNUSED_RESULT
static dif_spi_device_result_t build_control_word(
- const dif_spi_device_config_t *config, uint32_t *control_word) {
+ dif_spi_device_config_t config, uint32_t *control_word) {
*control_word = 0;
// Default polarity is positive.
- if (config->clock_polarity == kDifSpiDeviceEdgeNegative) {
+ if (config.clock_polarity == kDifSpiDeviceEdgeNegative) {
*control_word |= 0x1 << SPI_DEVICE_CFG_CPOL;
}
// Default phase is negative.
- if (config->data_phase == kDifSpiDeviceEdgePositive) {
+ if (config.data_phase == kDifSpiDeviceEdgePositive) {
*control_word |= 0x1 << SPI_DEVICE_CFG_CPHA;
}
// Default order is msb to lsb.
- if (config->tx_order == kDifSpiDeviceBitOrderLsbToMsb) {
+ if (config.tx_order == kDifSpiDeviceBitOrderLsbToMsb) {
*control_word |= 0x1 << SPI_DEVICE_CFG_TX_ORDER;
}
// Default order is msb to lsb.
- if (config->rx_order == kDifSpiDeviceBitOrderLsbToMsb) {
+ if (config.rx_order == kDifSpiDeviceBitOrderLsbToMsb) {
*control_word |= 0x1 << SPI_DEVICE_CFG_RX_ORDER;
}
@@ -45,18 +57,16 @@
.mask = SPI_DEVICE_CFG_TIMER_V_MASK,
.index = SPI_DEVICE_CFG_TIMER_V_OFFSET,
},
- config->rx_fifo_timeout);
+ config.rx_fifo_timeout);
- return kDifSpiDeviceResultOk;
+ return kDifSpiDeviceOk;
}
-dif_spi_device_result_t dif_spi_device_init(
- mmio_region_t base_addr, const dif_spi_device_config_t *config,
- dif_spi_device_t *spi) {
- if (config == NULL || spi == NULL) {
- return kDifSpiDeviceResultBadArg;
+dif_spi_device_result_t dif_spi_device_configure(
+ dif_spi_device_t *spi, dif_spi_device_config_t config) {
+ if (spi == NULL) {
+ return kDifSpiDeviceBadArg;
}
- spi->base_addr = base_addr;
// NOTE: we do not write to any registers until performing all
// function argument checks, to avoid a halfway-configured SPI.
@@ -64,17 +74,17 @@
uint32_t device_config;
dif_spi_device_result_t control_error =
build_control_word(config, &device_config);
- if (control_error != kDifSpiDeviceResultOk) {
+ if (control_error != kDifSpiDeviceOk) {
return control_error;
}
uint16_t rx_fifo_start = 0x0;
- uint16_t rx_fifo_end = config->rx_fifo_len - 1;
+ uint16_t rx_fifo_end = config.rx_fifo_len - 1;
uint16_t tx_fifo_start = rx_fifo_end + 1;
- uint16_t tx_fifo_end = tx_fifo_start + config->tx_fifo_len - 1;
+ uint16_t tx_fifo_end = tx_fifo_start + config.tx_fifo_len - 1;
if (tx_fifo_end >= kDifSpiDeviceBufferLen) {
// We've overflown the SRAM region...
- return kDifSpiDeviceResultBadArg;
+ return kDifSpiDeviceBadArg;
}
uint32_t rx_fifo_bounds = 0;
@@ -109,198 +119,251 @@
},
tx_fifo_end);
- spi->rx_fifo_base = rx_fifo_start;
- spi->rx_fifo_len = config->rx_fifo_len;
- spi->tx_fifo_base = tx_fifo_start;
- spi->tx_fifo_len = config->tx_fifo_len;
+ spi->rx_fifo_len = config.rx_fifo_len;
+ spi->tx_fifo_len = config.tx_fifo_len;
- // Now that we know that all function arguments are valid, we can abort
- // all current transactions and begin reconfiguring the device.
- dif_spi_device_result_t err;
- err = dif_spi_device_abort(spi);
- if (err != kDifSpiDeviceResultOk) {
- return err;
- }
- err = dif_spi_device_irq_reset(spi);
- if (err != kDifSpiDeviceResultOk) {
- return err;
- }
-
- mmio_region_write32(spi->base_addr, SPI_DEVICE_CFG_REG_OFFSET, device_config);
- mmio_region_write32(spi->base_addr, SPI_DEVICE_RXF_ADDR_REG_OFFSET,
+ mmio_region_write32(spi->params.base_addr, SPI_DEVICE_CFG_REG_OFFSET,
+ device_config);
+ mmio_region_write32(spi->params.base_addr, SPI_DEVICE_RXF_ADDR_REG_OFFSET,
rx_fifo_bounds);
- mmio_region_write32(spi->base_addr, SPI_DEVICE_TXF_ADDR_REG_OFFSET,
+ mmio_region_write32(spi->params.base_addr, SPI_DEVICE_TXF_ADDR_REG_OFFSET,
tx_fifo_bounds);
- return kDifSpiDeviceResultOk;
+ return kDifSpiDeviceOk;
}
dif_spi_device_result_t dif_spi_device_abort(const dif_spi_device_t *spi) {
if (spi == NULL) {
- return kDifSpiDeviceResultBadArg;
+ return kDifSpiDeviceBadArg;
}
// Set the `abort` bit, and then spin until `abort_done` is asserted.
- mmio_region_nonatomic_set_bit32(spi->base_addr, SPI_DEVICE_CONTROL_REG_OFFSET,
+ mmio_region_nonatomic_set_bit32(spi->params.base_addr,
+ SPI_DEVICE_CONTROL_REG_OFFSET,
SPI_DEVICE_CONTROL_ABORT);
- while (!mmio_region_get_bit32(spi->base_addr, SPI_DEVICE_STATUS_REG_OFFSET,
+ while (!mmio_region_get_bit32(spi->params.base_addr,
+ SPI_DEVICE_STATUS_REG_OFFSET,
SPI_DEVICE_STATUS_ABORT_DONE)) {
}
- return kDifSpiDeviceResultOk;
+ return kDifSpiDeviceOk;
}
-dif_spi_device_result_t dif_spi_device_irq_reset(const dif_spi_device_t *spi) {
- if (spi == NULL) {
- return kDifSpiDeviceResultBadArg;
- }
-
- dif_spi_device_result_t err;
-
- err = dif_spi_device_irq_clear_all(spi);
- if (err != kDifSpiDeviceResultOk) {
- return err;
- }
- err = dif_spi_device_set_irq_levels(spi, 0x80, 0x00);
- if (err != kDifSpiDeviceResultOk) {
- return err;
- }
-
- // Disable interrupts manually, since the relevant DIF only allows for single
- // bit flips.
- mmio_region_write32(spi->base_addr, SPI_DEVICE_INTR_ENABLE_REG_OFFSET, 0);
-
- return kDifSpiDeviceResultOk;
-}
-
-dif_spi_device_result_t dif_spi_device_irq_get(const dif_spi_device_t *spi,
- dif_spi_device_irq_type_t type,
- bool *flag_out) {
- if (spi == NULL || flag_out == NULL) {
- return kDifSpiDeviceResultBadArg;
+dif_spi_device_result_t dif_spi_device_irq_is_pending(
+ const dif_spi_device_t *spi, dif_spi_device_irq_t irq, bool *is_pending) {
+ if (spi == NULL || is_pending == NULL) {
+ return kDifSpiDeviceBadArg;
}
uint32_t bit_index = 0;
- switch (type) {
- case kDifSpiDeviceIrqTypeRxFull:
+ switch (irq) {
+ case kDifSpiDeviceIrqRxFull:
bit_index = SPI_DEVICE_INTR_STATE_RXF;
break;
- case kDifSpiDeviceIrqTypeRxAboveLevel:
+ case kDifSpiDeviceIrqRxAboveLevel:
bit_index = SPI_DEVICE_INTR_STATE_RXLVL;
break;
- case kDifSpiDeviceIrqTypeTxBelowLevel:
+ case kDifSpiDeviceIrqTxBelowLevel:
bit_index = SPI_DEVICE_INTR_STATE_TXLVL;
break;
- case kDifSpiDeviceIrqTypeRxError:
+ case kDifSpiDeviceIrqRxError:
bit_index = SPI_DEVICE_INTR_STATE_RXERR;
break;
- case kDifSpiDeviceIrqTypeRxOverflow:
+ case kDifSpiDeviceIrqRxOverflow:
bit_index = SPI_DEVICE_INTR_STATE_RXOVERFLOW;
break;
- case kDifSpiDeviceIrqTypeTxUnderflow:
+ case kDifSpiDeviceIrqTxUnderflow:
bit_index = SPI_DEVICE_INTR_STATE_TXUNDERFLOW;
break;
}
- *flag_out = mmio_region_get_bit32(
- spi->base_addr, SPI_DEVICE_INTR_STATE_REG_OFFSET, bit_index);
- return kDifSpiDeviceResultOk;
+ *is_pending = mmio_region_get_bit32(
+ spi->params.base_addr, SPI_DEVICE_INTR_STATE_REG_OFFSET, bit_index);
+ return kDifSpiDeviceOk;
}
-dif_spi_device_result_t dif_spi_device_irq_clear_all(
- const dif_spi_device_t *spi) {
+dif_spi_device_result_t dif_spi_device_irq_acknowledge(
+ const dif_spi_device_t *spi, dif_spi_device_irq_t irq) {
if (spi == NULL) {
- return kDifSpiDeviceResultBadArg;
- }
-
- // The state register is a write-one-clear register.
- mmio_region_write32(spi->base_addr, SPI_DEVICE_INTR_STATE_REG_OFFSET,
- UINT32_MAX);
-
- return kDifSpiDeviceResultOk;
-}
-
-dif_spi_device_result_t dif_spi_device_irq_enable(
- const dif_spi_device_t *spi, dif_spi_device_irq_type_t type,
- dif_spi_device_irq_state_t state) {
- if (spi == NULL) {
- return kDifSpiDeviceResultBadArg;
+ return kDifSpiDeviceBadArg;
}
uint32_t bit_index = 0;
- switch (type) {
- case kDifSpiDeviceIrqTypeRxFull:
+ switch (irq) {
+ case kDifSpiDeviceIrqRxFull:
+ bit_index = SPI_DEVICE_INTR_STATE_RXF;
+ break;
+ case kDifSpiDeviceIrqRxAboveLevel:
+ bit_index = SPI_DEVICE_INTR_STATE_RXLVL;
+ break;
+ case kDifSpiDeviceIrqTxBelowLevel:
+ bit_index = SPI_DEVICE_INTR_STATE_TXLVL;
+ break;
+ case kDifSpiDeviceIrqRxError:
+ bit_index = SPI_DEVICE_INTR_STATE_RXERR;
+ break;
+ case kDifSpiDeviceIrqRxOverflow:
+ bit_index = SPI_DEVICE_INTR_STATE_RXOVERFLOW;
+ break;
+ case kDifSpiDeviceIrqTxUnderflow:
+ bit_index = SPI_DEVICE_INTR_STATE_TXUNDERFLOW;
+ break;
+ }
+
+ mmio_region_write32(spi->params.base_addr, SPI_DEVICE_INTR_STATE_REG_OFFSET,
+ 1 << bit_index);
+ return kDifSpiDeviceOk;
+}
+
+dif_spi_device_result_t dif_spi_device_irq_get_enabled(
+ const dif_spi_device_t *spi, dif_spi_device_irq_t irq,
+ dif_spi_device_toggle_t *state) {
+ if (spi == NULL || state == NULL) {
+ return kDifSpiDeviceBadArg;
+ }
+
+ uint32_t bit_index = 0;
+ switch (irq) {
+ case kDifSpiDeviceIrqRxFull:
bit_index = SPI_DEVICE_INTR_ENABLE_RXF;
break;
- case kDifSpiDeviceIrqTypeRxAboveLevel:
+ case kDifSpiDeviceIrqRxAboveLevel:
bit_index = SPI_DEVICE_INTR_ENABLE_RXLVL;
break;
- case kDifSpiDeviceIrqTypeTxBelowLevel:
+ case kDifSpiDeviceIrqTxBelowLevel:
bit_index = SPI_DEVICE_INTR_ENABLE_TXLVL;
break;
- case kDifSpiDeviceIrqTypeRxError:
+ case kDifSpiDeviceIrqRxError:
bit_index = SPI_DEVICE_INTR_ENABLE_RXERR;
break;
- case kDifSpiDeviceIrqTypeRxOverflow:
+ case kDifSpiDeviceIrqRxOverflow:
bit_index = SPI_DEVICE_INTR_ENABLE_RXOVERFLOW;
break;
- case kDifSpiDeviceIrqTypeTxUnderflow:
+ case kDifSpiDeviceIrqTxUnderflow:
+ bit_index = SPI_DEVICE_INTR_ENABLE_TXUNDERFLOW;
+ break;
+ }
+
+ bool is_enabled = mmio_region_get_bit32(
+ spi->params.base_addr, SPI_DEVICE_INTR_ENABLE_REG_OFFSET, bit_index);
+ *state =
+ is_enabled ? kDifSpiDeviceToggleEnabled : kDifSpiDeviceToggleDisabled;
+
+ return kDifSpiDeviceOk;
+}
+
+dif_spi_device_result_t dif_spi_device_irq_set_enabled(
+ const dif_spi_device_t *spi, dif_spi_device_irq_t irq,
+ dif_spi_device_toggle_t state) {
+ if (spi == NULL) {
+ return kDifSpiDeviceBadArg;
+ }
+
+ uint32_t bit_index = 0;
+ switch (irq) {
+ case kDifSpiDeviceIrqRxFull:
+ bit_index = SPI_DEVICE_INTR_ENABLE_RXF;
+ break;
+ case kDifSpiDeviceIrqRxAboveLevel:
+ bit_index = SPI_DEVICE_INTR_ENABLE_RXLVL;
+ break;
+ case kDifSpiDeviceIrqTxBelowLevel:
+ bit_index = SPI_DEVICE_INTR_ENABLE_TXLVL;
+ break;
+ case kDifSpiDeviceIrqRxError:
+ bit_index = SPI_DEVICE_INTR_ENABLE_RXERR;
+ break;
+ case kDifSpiDeviceIrqRxOverflow:
+ bit_index = SPI_DEVICE_INTR_ENABLE_RXOVERFLOW;
+ break;
+ case kDifSpiDeviceIrqTxUnderflow:
bit_index = SPI_DEVICE_INTR_ENABLE_TXUNDERFLOW;
break;
}
switch (state) {
- case kDifSpiDeviceIrqStateEnabled:
+ case kDifSpiDeviceToggleEnabled:
mmio_region_nonatomic_set_bit32(
- spi->base_addr, SPI_DEVICE_INTR_ENABLE_REG_OFFSET, bit_index);
+ spi->params.base_addr, SPI_DEVICE_INTR_ENABLE_REG_OFFSET, bit_index);
break;
- case kDifSpiDeviceIrqStateDisabled:
+ case kDifSpiDeviceToggleDisabled:
mmio_region_nonatomic_clear_bit32(
- spi->base_addr, SPI_DEVICE_INTR_ENABLE_REG_OFFSET, bit_index);
+ spi->params.base_addr, SPI_DEVICE_INTR_ENABLE_REG_OFFSET, bit_index);
break;
}
- return kDifSpiDeviceResultOk;
+ return kDifSpiDeviceOk;
}
-dif_spi_device_result_t dif_spi_device_irq_force(
- const dif_spi_device_t *spi, dif_spi_device_irq_type_t type) {
+dif_spi_device_result_t dif_spi_device_irq_force(const dif_spi_device_t *spi,
+ dif_spi_device_irq_t irq) {
if (spi == NULL) {
- return kDifSpiDeviceResultBadArg;
+ return kDifSpiDeviceBadArg;
}
uint32_t bit_index = 0;
- switch (type) {
- case kDifSpiDeviceIrqTypeRxFull:
+ switch (irq) {
+ case kDifSpiDeviceIrqRxFull:
bit_index = SPI_DEVICE_INTR_TEST_RXF;
break;
- case kDifSpiDeviceIrqTypeRxAboveLevel:
+ case kDifSpiDeviceIrqRxAboveLevel:
bit_index = SPI_DEVICE_INTR_TEST_RXLVL;
break;
- case kDifSpiDeviceIrqTypeTxBelowLevel:
+ case kDifSpiDeviceIrqTxBelowLevel:
bit_index = SPI_DEVICE_INTR_TEST_TXLVL;
break;
- case kDifSpiDeviceIrqTypeRxError:
+ case kDifSpiDeviceIrqRxError:
bit_index = SPI_DEVICE_INTR_TEST_RXERR;
break;
- case kDifSpiDeviceIrqTypeRxOverflow:
+ case kDifSpiDeviceIrqRxOverflow:
bit_index = SPI_DEVICE_INTR_TEST_RXOVERFLOW;
break;
- case kDifSpiDeviceIrqTypeTxUnderflow:
+ case kDifSpiDeviceIrqTxUnderflow:
bit_index = SPI_DEVICE_INTR_TEST_TXUNDERFLOW;
break;
}
uint32_t mask = 1 << bit_index;
- mmio_region_write32(spi->base_addr, SPI_DEVICE_INTR_TEST_REG_OFFSET, mask);
+ mmio_region_write32(spi->params.base_addr, SPI_DEVICE_INTR_TEST_REG_OFFSET,
+ mask);
- return kDifSpiDeviceResultOk;
+ return kDifSpiDeviceOk;
+}
+
+dif_spi_device_result_t dif_spi_device_irq_disable_all(
+ const dif_spi_device_t *spi, dif_spi_device_irq_snapshot_t *snapshot) {
+ if (spi == NULL) {
+ return kDifSpiDeviceBadArg;
+ }
+
+ if (snapshot != NULL) {
+ *snapshot = mmio_region_read32(spi->params.base_addr,
+ SPI_DEVICE_INTR_ENABLE_REG_OFFSET);
+ }
+
+ mmio_region_write32(spi->params.base_addr, SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
+ 0);
+
+ return kDifSpiDeviceOk;
+}
+
+dif_spi_device_result_t dif_spi_device_irq_restore_all(
+ const dif_spi_device_t *spi,
+ const dif_spi_device_irq_snapshot_t *snapshot) {
+ if (spi == NULL || snapshot == NULL) {
+ return kDifSpiDeviceBadArg;
+ }
+
+ mmio_region_write32(spi->params.base_addr, SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
+ *snapshot);
+
+ return kDifSpiDeviceOk;
}
dif_spi_device_result_t dif_spi_device_set_irq_levels(
const dif_spi_device_t *spi, uint16_t rx_level, uint16_t tx_level) {
if (spi == NULL) {
- return kDifSpiDeviceResultBadArg;
+ return kDifSpiDeviceBadArg;
}
uint32_t compressed_limit = 0;
@@ -318,10 +381,10 @@
.index = SPI_DEVICE_FIFO_LEVEL_TXLVL_OFFSET,
},
tx_level);
- mmio_region_write32(spi->base_addr, SPI_DEVICE_FIFO_LEVEL_REG_OFFSET,
+ mmio_region_write32(spi->params.base_addr, SPI_DEVICE_FIFO_LEVEL_REG_OFFSET,
compressed_limit);
- return kDifSpiDeviceResultOk;
+ return kDifSpiDeviceOk;
}
/**
@@ -418,7 +481,7 @@
*/
static fifo_ptrs_t decompress_ptrs(const dif_spi_device_t *spi,
fifo_ptr_params_t params) {
- uint32_t ptr = mmio_region_read32(spi->base_addr, params.reg_offset);
+ uint32_t ptr = mmio_region_read32(spi->params.base_addr, params.reg_offset);
uint16_t write_val =
(uint16_t)((ptr >> params.write_offset) & params.write_mask);
uint16_t read_val =
@@ -469,7 +532,7 @@
.mask = params.read_mask, .index = params.read_offset,
},
read_val);
- mmio_region_write32(spi->base_addr, params.reg_offset, ptr);
+ mmio_region_write32(spi->params.base_addr, params.reg_offset, ptr);
}
/**
@@ -505,25 +568,25 @@
dif_spi_device_result_t dif_spi_device_rx_pending(const dif_spi_device_t *spi,
size_t *bytes_pending) {
if (spi == NULL || bytes_pending == NULL) {
- return kDifSpiDeviceResultBadArg;
+ return kDifSpiDeviceBadArg;
}
fifo_ptrs_t ptrs = decompress_ptrs(spi, kRxFifoParams);
*bytes_pending = fifo_bytes_in_use(ptrs, spi->rx_fifo_len);
- return kDifSpiDeviceResultOk;
+ return kDifSpiDeviceOk;
}
dif_spi_device_result_t dif_spi_device_tx_pending(const dif_spi_device_t *spi,
size_t *bytes_pending) {
if (spi == NULL || bytes_pending == NULL) {
- return kDifSpiDeviceResultBadArg;
+ return kDifSpiDeviceBadArg;
}
fifo_ptrs_t ptrs = decompress_ptrs(spi, kTxFifoParams);
*bytes_pending = fifo_bytes_in_use(ptrs, spi->tx_fifo_len);
- return kDifSpiDeviceResultOk;
+ return kDifSpiDeviceOk;
}
/**
@@ -582,11 +645,11 @@
}
if (is_recv) {
// SPI device buffer -> `byte_buf`
- mmio_region_memcpy_from_mmio32(spi->base_addr, mmio_offset, byte_buf,
- bytes_to_copy);
+ mmio_region_memcpy_from_mmio32(spi->params.base_addr, mmio_offset,
+ byte_buf, bytes_to_copy);
} else {
// `byte_buf` -> SPI device buffer
- mmio_region_memcpy_to_mmio32(spi->base_addr, mmio_offset, byte_buf,
+ mmio_region_memcpy_to_mmio32(spi->params.base_addr, mmio_offset, byte_buf,
bytes_to_copy);
}
fifo_ptr_increment(ptr, bytes_to_copy, fifo_len);
@@ -601,10 +664,10 @@
void *buf, size_t buf_len,
size_t *bytes_received) {
if (spi == NULL || buf == NULL) {
- return kDifSpiDeviceResultBadArg;
+ return kDifSpiDeviceBadArg;
}
- uint16_t fifo_base = spi->rx_fifo_base;
+ uint16_t fifo_base = 0;
uint16_t fifo_len = spi->rx_fifo_len;
fifo_ptrs_t fifo = decompress_ptrs(spi, kRxFifoParams);
@@ -617,17 +680,18 @@
// Commit the new RX FIFO pointers.
compress_ptrs(spi, kRxFifoParams, fifo);
}
- return kDifSpiDeviceResultOk;
+ return kDifSpiDeviceOk;
}
dif_spi_device_result_t dif_spi_device_send(const dif_spi_device_t *spi,
const void *buf, size_t buf_len,
size_t *bytes_sent) {
if (spi == NULL || buf == NULL) {
- return kDifSpiDeviceResultBadArg;
+ return kDifSpiDeviceBadArg;
}
- uint16_t fifo_base = spi->tx_fifo_base;
+ // Start of the TX FIFO is the end of the RX FIFO.
+ uint16_t fifo_base = spi->rx_fifo_len;
uint16_t fifo_len = spi->tx_fifo_len;
fifo_ptrs_t fifo = decompress_ptrs(spi, kTxFifoParams);
@@ -640,5 +704,5 @@
// Commit the new TX FIFO pointers.
compress_ptrs(spi, kTxFifoParams, fifo);
}
- return kDifSpiDeviceResultOk;
+ return kDifSpiDeviceOk;
}
diff --git a/sw/device/lib/dif/dif_spi_device.h b/sw/device/lib/dif/dif_spi_device.h
index 8c7b176..d2e7490 100644
--- a/sw/device/lib/dif/dif_spi_device.h
+++ b/sw/device/lib/dif/dif_spi_device.h
@@ -23,54 +23,108 @@
#endif // __cplusplus
/**
- * Represents a signal edge type.
+ * A signal edge type: positive or negative.
*/
typedef enum dif_spi_device_edge {
+ /**
+ * Represents a positive edge (i.e., from low to high).
+ */
kDifSpiDeviceEdgePositive,
+ /**
+ * Represents a negative edge (i.e., from high to low).
+ */
kDifSpiDeviceEdgeNegative,
} dif_spi_device_edge_t;
/**
- * Represents a bit ordering.
+ * A bit ordering within a byte.
*/
typedef enum dif_spi_device_bit_order {
+ /**
+ * Represents the most-significant-bit to least-significant-bit order.
+ */
kDifSpiDeviceBitOrderMsbToLsb,
+ /**
+ * Represents the least-significant-bit to most-significant-bit order.
+ */
kDifSpiDeviceBitOrderLsbToMsb,
} dif_spi_device_bit_order_t;
/**
- * Represents the enablement state of a particular SPI IRQ.
+ * A toggle state: enabled, or disabled.
+ *
+ * This enum may be used instead of a `bool` when describing an enabled/disabled
+ * state.
*/
-typedef enum dif_spi_device_irq_state {
- kDifSpiDeviceIrqStateEnabled = true,
- kDifSpiDeviceIrqStateDisabled = false,
-} dif_spi_device_irq_state_t;
+typedef enum dif_spi_device_toggle {
+ /*
+ * The "enabled" state.
+ */
+ kDifSpiDeviceToggleEnabled,
+ /**
+ * The "disabled" state.
+ */
+ kDifSpiDeviceToggleDisabled,
+} dif_spi_device_toggle_t;
/**
- * Represents the types of interrupts that the SPI device will
- * fire to signal state.
+ * A SPI interrupt request type.
*/
-typedef enum dif_spi_device_irq_type {
- kDifSpiDeviceIrqTypeRxFull,
- kDifSpiDeviceIrqTypeRxAboveLevel,
- kDifSpiDeviceIrqTypeTxBelowLevel,
- kDifSpiDeviceIrqTypeRxError,
- kDifSpiDeviceIrqTypeRxOverflow,
- kDifSpiDeviceIrqTypeTxUnderflow,
-} dif_spi_device_irq_type_t;
+typedef enum dif_spi_device_irq {
+ /**
+ * Indicates that the RX FIFO is full.
+ */
+ kDifSpiDeviceIrqRxFull,
+ /**
+ * Indicates that the RX FIFO is above the configured level.
+ */
+ kDifSpiDeviceIrqRxAboveLevel,
+ /**
+ * Indicates that the TX FIFO is below the configured level.
+ */
+ kDifSpiDeviceIrqTxBelowLevel,
+ /**
+ * Indicates an error in the RX FIFO.
+ */
+ kDifSpiDeviceIrqRxError,
+ /**
+ * Indicates that overflow has occured in the RX FIFO.
+ */
+ kDifSpiDeviceIrqRxOverflow,
+ /**
+ * Indicates that underflow has occured in the RX FIFO.
+ */
+ kDifSpiDeviceIrqTxUnderflow,
+} dif_spi_device_irq_t;
/**
- * Errors returned by SPI DIF functions.
+ * A snapshot of the enablement state of the interrupts for SPI.
+ *
+ * This is an opaque type, to be used with the
+ * `dif_spi_device_irq_disable_all()` and
+ * `dif_spi_device_irq_restore_all()` functions.
+ */
+typedef uint32_t dif_spi_device_irq_snapshot_t;
+
+/**
+ * The result of a SPI operation.
*/
typedef enum dif_spi_device_result {
/**
- * Indicates a successful operation.
+ * Indicates that the operation succeeded.
*/
- kDifSpiDeviceResultOk = 0,
+ kDifSpiDeviceOk = 0,
/**
- * Indicates a failed precondition on the function arguments.
+ * Indicates some unspecified failure.
*/
- kDifSpiDeviceResultBadArg,
+ kDifSpiDeviceError = 1,
+ /**
+ * Indicates that some parameter passed into a function failed a
+ * precondition.
+ *
+ * When this value is returned, no hardware operations occured.
+ */
+ kDifSpiDeviceBadArg = 2,
} dif_spi_device_result_t;
/**
@@ -82,7 +136,24 @@
extern const uint16_t kDifSpiDeviceBufferLen;
/**
- * Configuration for initializing a SPI device.
+ * Hardware instantiation parameters for SPI.
+ *
+ * This struct describes information about the underlying hardware that is
+ * not determined until the hardware design is used as part of a top-level
+ * design.
+ */
+typedef struct dif_spi_device_params {
+ /**
+ * The base address for the SPI hardware registers.
+ */
+ mmio_region_t base_addr;
+} dif_spi_device_params_t;
+
+/**
+ * Runtime configuration for SPI.
+ *
+ * This struct describes runtime information for one-time configuration of the
+ * hardware.
*/
typedef struct dif_spi_device_config {
dif_spi_device_edge_t clock_polarity;
@@ -90,103 +161,155 @@
dif_spi_device_bit_order_t tx_order;
dif_spi_device_bit_order_t rx_order;
uint8_t rx_fifo_timeout;
+ /**
+ * The length, in bytes, that should be reserved for the RX FIFO.
+ *
+ * `kDifSpiDeviceBufferLen / 2` is a good default for this value.
+ */
uint16_t rx_fifo_len;
+ /**
+ * The length, in bytes, that should be reserved for the TX FIFO.
+ *
+ * `kDifSpiDeviceBufferLen / 2` is a good default for this value.
+ */
uint16_t tx_fifo_len;
} dif_spi_device_config_t;
/**
- * State for a particular SPI device.
+ * A handle to a SPI device.
*
- * Its member variables should be considered private, and are only provided so
- * that callers can allocate it.
+ * This type should be treated as opaque by users.
*/
typedef struct dif_spi_device {
- mmio_region_t base_addr;
- uint16_t rx_fifo_base;
+ dif_spi_device_params_t params;
uint16_t rx_fifo_len;
- uint16_t tx_fifo_base;
uint16_t tx_fifo_len;
} dif_spi_device_t;
/**
- * Initializes a SPI device with the given configuration.
+ * Creates a new handle for SPI.
*
- * @param base_addr The start of the SPI device register.
- * @param config The configuration to initialize with.
- * @param[out] spi The initialized device.
+ * This function does not actuate the hardware.
+ *
+ * @param params Hardware instantiation parameters.
+ * @param[out] spi Out param for the initialized handle.
* @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_spi_device_result_t dif_spi_device_init(
- mmio_region_t base_addr, const dif_spi_device_config_t *config,
- dif_spi_device_t *spi);
+dif_spi_device_result_t dif_spi_device_init(dif_spi_device_params_t params,
+ dif_spi_device_t *spi);
+
+/**
+ * Configures SPI with runtime information.
+ *
+ * This function should need to be called once for the lifetime of `handle`.
+ *
+ * @param spi A SPI handle.
+ * @param config Runtime configuration parameters.
+ * @return The result of the operation.
+ */
+DIF_WARN_UNUSED_RESULT
+dif_spi_device_result_t dif_spi_device_configure(
+ dif_spi_device_t *spi, dif_spi_device_config_t config);
/**
* Issues an "abort" to the given SPI device, causing all in-progress IO to
* halt.
*
- * @param spi An SPI device.
+ * @param spi A SPI handle.
* @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
dif_spi_device_result_t dif_spi_device_abort(const dif_spi_device_t *spi);
/**
- * Resets all interrupt-related state on the given SPI device, such as enabled
- * interrupts and set RX/TX levels.
+ * Returns whether a particular interrupt is currently pending.
*
- * @param spi An SPI device.
+ * @param spi A SPI handle.
+ * @param irq An interrupt type.
+ * @param[out] is_pending Out-param for whether the interrupt is pending.
* @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_spi_device_result_t dif_spi_device_irq_reset(const dif_spi_device_t *spi);
+dif_spi_device_result_t dif_spi_device_irq_is_pending(
+ const dif_spi_device_t *spi, dif_spi_device_irq_t irq, bool *is_pending);
/**
- * Returns whether the given IRQ is currently being serviced.
+ * Acknowledges a particular interrupt, indicating to the hardware that it has
+ * been successfully serviced.
*
- * @param spi An SPI device.
- * @param type Which IRQ type to check.
- * @param[out] flag Whether the IRQ is active.
+ * @param spi A SPI handle.
+ * @param irq An interrupt type.
* @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_spi_device_result_t dif_spi_device_irq_get(const dif_spi_device_t *spi,
- dif_spi_device_irq_type_t type,
- bool *flag_out);
+dif_spi_device_result_t dif_spi_device_irq_acknowledge(
+ const dif_spi_device_t *spi, dif_spi_device_irq_t irq);
/**
- * Clears all active interrupt bits.
+ * Checks whether a particular interrupt is currently enabled or disabled.
*
- * @param spi An SPI device.
+ * @param spi A SPI handle.
+ * @param irq An interrupt type.
+ * @param[out] state Out-param toggle state of the interrupt.
* @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_spi_device_result_t dif_spi_device_irq_clear_all(
- const dif_spi_device_t *spi);
+dif_spi_device_result_t dif_spi_device_irq_get_enabled(
+ const dif_spi_device_t *spi, dif_spi_device_irq_t irq,
+ dif_spi_device_toggle_t *state);
/**
- * Enable or disable a particular interrupt.
+ * Sets whether a particular interrupt is currently enabled or disabled.
*
- * @param spi An SPI device.
- * @param type Which IRQ type to toggle.
- * @param state The state to update the bit to.
+ * @param spi A SPI handle.
+ * @param irq An interrupt type.
+ * @param state The new toggle state for the interrupt.
* @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_spi_device_result_t dif_spi_device_irq_enable(
- const dif_spi_device_t *spi, dif_spi_device_irq_type_t type,
- dif_spi_device_irq_state_t state);
+dif_spi_device_result_t dif_spi_device_irq_set_enabled(
+ const dif_spi_device_t *spi, dif_spi_device_irq_t irq,
+ dif_spi_device_toggle_t state);
/**
- * Forces a particular IRQ type to fire.
+ * Forces a particular interrupt, causing it to be serviced as if hardware had
+ * asserted it.
*
- * @param spi An SPI device.
- * @param type Which IRQ type to fire.
+ * @param spi A SPI handle.
+ * @param irq An interrupt type.
* @return The result of the operation.
*/
DIF_WARN_UNUSED_RESULT
-dif_spi_device_result_t dif_spi_device_irq_force(
- const dif_spi_device_t *spi, dif_spi_device_irq_type_t type);
+dif_spi_device_result_t dif_spi_device_irq_force(const dif_spi_device_t *spi,
+ dif_spi_device_irq_t irq);
+
+/**
+ * Disables all interrupts, optionally snapshotting all toggle state for later
+ * restoration.
+ *
+ * @param spi A SPI handle.
+ * @param[out] snapshot Out-param for the snapshot; may be `NULL`.
+ * @return The result of the operation.
+ */
+DIF_WARN_UNUSED_RESULT
+dif_spi_device_result_t dif_spi_device_irq_disable_all(
+ const dif_spi_device_t *spi, dif_spi_device_irq_snapshot_t *snapshot);
+
+/**
+ * Restores interrupts from the given snapshot.
+ *
+ * This function can be used with `dif_spi_device_irq_disable_all()` to
+ * temporary
+ * interrupt save-and-restore.
+ *
+ * @param spi A SPI handle.
+ * @param snapshot A snapshot to restore from.
+ * @return The result of the operation.
+ */
+DIF_WARN_UNUSED_RESULT
+dif_spi_device_result_t dif_spi_device_irq_restore_all(
+ const dif_spi_device_t *spi, const dif_spi_device_irq_snapshot_t *snapshot);
/**
* Sets up the "FIFO level" (that is, number of bytes present in a particular
@@ -202,7 +325,7 @@
* to detect that there is free space to write more data to the TX FIFO.
* This is the `Main Memory -> Spi Buffer` case.
*
- * @param spi An SPI device.
+ * @param spi A SPI handle.
* @param rx_level The new RX level, as described above.
* @param tx_level The new TX level, as described above.
* @return The result of the operation.
@@ -214,7 +337,7 @@
/**
* Returns the number of bytes still pending receipt by software in the RX FIFO.
*
- * @param spi An SPI device.
+ * @param spi A SPI handle.
* @param[out] bytes_pending The number of bytes pending
* @return The result of the operation.
*/
@@ -226,7 +349,7 @@
* Returns the number of bytes still pending transmission by hardware in the TX
* FIFO.
*
- * @param spi An SPI device.
+ * @param spi A SPI handle.
* @param[out] bytes_pending The number of bytes pending
* @return The result of the operation.
*/
diff --git a/sw/device/tests/dif/dif_spi_device_unittest.cc b/sw/device/tests/dif/dif_spi_device_unittest.cc
index f86207e..dea6ab2 100644
--- a/sw/device/tests/dif/dif_spi_device_unittest.cc
+++ b/sw/device/tests/dif/dif_spi_device_unittest.cc
@@ -40,11 +40,9 @@
static const uint16_t kFifoLen = 0x400;
dif_spi_device_t spi_ = {
- /*base_addr=*/dev().region(),
- /*rx_fifo_base=*/0x0000,
- /*rx_fifo_len=*/kFifoLen,
- /*tx_fifo_base=*/kFifoLen,
- /*tx_fifo_len=*/kFifoLen,
+ .params = {.base_addr = dev().region()},
+ .rx_fifo_len = kFifoLen,
+ .tx_fifo_len = kFifoLen,
};
dif_spi_device_config_t config_ = {
@@ -66,7 +64,7 @@
EXPECT_READ32(SPI_DEVICE_STATUS_REG_OFFSET,
{{SPI_DEVICE_STATUS_ABORT_DONE, 0x1}});
- EXPECT_EQ(dif_spi_device_abort(&spi_), kDifSpiDeviceResultOk);
+ EXPECT_EQ(dif_spi_device_abort(&spi_), kDifSpiDeviceOk);
}
TEST_F(AbortTest, Delayed) {
@@ -81,30 +79,16 @@
EXPECT_READ32(SPI_DEVICE_STATUS_REG_OFFSET,
{{SPI_DEVICE_STATUS_ABORT_DONE, 0x1}});
- EXPECT_EQ(dif_spi_device_abort(&spi_), kDifSpiDeviceResultOk);
+ EXPECT_EQ(dif_spi_device_abort(&spi_), kDifSpiDeviceOk);
}
TEST_F(AbortTest, NullArgs) {
- EXPECT_EQ(dif_spi_device_abort(nullptr), kDifSpiDeviceResultBadArg);
+ EXPECT_EQ(dif_spi_device_abort(nullptr), kDifSpiDeviceBadArg);
}
-class InitTest : public SpiTest {};
+class ConfigTest : public SpiTest {};
-TEST_F(InitTest, BasicInit) {
- EXPECT_MASK32(SPI_DEVICE_CONTROL_REG_OFFSET,
- {{SPI_DEVICE_CONTROL_ABORT, 0x1, 0x1}});
- EXPECT_READ32(SPI_DEVICE_STATUS_REG_OFFSET,
- {{SPI_DEVICE_STATUS_ABORT_DONE, 0x1}});
-
- EXPECT_WRITE32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
- std::numeric_limits<uint32_t>::max());
-
- EXPECT_WRITE32(SPI_DEVICE_FIFO_LEVEL_REG_OFFSET,
- {{SPI_DEVICE_FIFO_LEVEL_RXLVL_OFFSET, 0x80},
- {SPI_DEVICE_FIFO_LEVEL_TXLVL_OFFSET, 0x00}});
-
- EXPECT_WRITE32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET, 0x0);
-
+TEST_F(ConfigTest, BasicInit) {
EXPECT_WRITE32(SPI_DEVICE_CFG_REG_OFFSET,
{
{SPI_DEVICE_CFG_CPOL, 0},
@@ -124,31 +108,16 @@
{SPI_DEVICE_TXF_ADDR_LIMIT_OFFSET, 0x800 - 1},
});
- EXPECT_EQ(dif_spi_device_init(dev().region(), &config_, &spi_),
- kDifSpiDeviceResultOk);
+ EXPECT_EQ(dif_spi_device_configure(&spi_, config_), kDifSpiDeviceOk);
}
-TEST_F(InitTest, ComplexInit) {
+TEST_F(ConfigTest, ComplexInit) {
config_.clock_polarity = kDifSpiDeviceEdgeNegative;
config_.data_phase = kDifSpiDeviceEdgePositive;
config_.tx_order = kDifSpiDeviceBitOrderLsbToMsb;
config_.rx_fifo_timeout = 42;
config_.rx_fifo_len = 0x24;
- EXPECT_MASK32(SPI_DEVICE_CONTROL_REG_OFFSET,
- {{SPI_DEVICE_CONTROL_ABORT, 0x1, 0x1}});
- EXPECT_READ32(SPI_DEVICE_STATUS_REG_OFFSET,
- {{SPI_DEVICE_STATUS_ABORT_DONE, 0x1}});
-
- EXPECT_WRITE32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
- std::numeric_limits<uint32_t>::max());
-
- EXPECT_WRITE32(SPI_DEVICE_FIFO_LEVEL_REG_OFFSET,
- {{SPI_DEVICE_FIFO_LEVEL_RXLVL_OFFSET, 0x80},
- {SPI_DEVICE_FIFO_LEVEL_TXLVL_OFFSET, 0x00}});
-
- EXPECT_WRITE32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET, 0x0);
-
EXPECT_WRITE32(SPI_DEVICE_CFG_REG_OFFSET,
{
{SPI_DEVICE_CFG_CPOL, 1},
@@ -168,21 +137,16 @@
{SPI_DEVICE_TXF_ADDR_LIMIT_OFFSET, 0x423},
});
- EXPECT_EQ(dif_spi_device_init(dev().region(), &config_, &spi_),
- kDifSpiDeviceResultOk);
+ EXPECT_EQ(dif_spi_device_configure(&spi_, config_), kDifSpiDeviceOk);
}
-TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_spi_device_init(dev().region(), &config_, nullptr),
- kDifSpiDeviceResultBadArg);
- EXPECT_EQ(dif_spi_device_init(dev().region(), nullptr, &spi_),
- kDifSpiDeviceResultBadArg);
+TEST_F(ConfigTest, NullArgs) {
+ EXPECT_EQ(dif_spi_device_configure(nullptr, config_), kDifSpiDeviceBadArg);
}
-TEST_F(InitTest, InitSramOverflow) {
+TEST_F(ConfigTest, InitSramOverflow) {
config_.rx_fifo_len = 0x1000;
- EXPECT_EQ(dif_spi_device_init(dev().region(), &config_, &spi_),
- kDifSpiDeviceResultBadArg);
+ EXPECT_EQ(dif_spi_device_configure(&spi_, config_), kDifSpiDeviceBadArg);
}
class IrqTest : public SpiTest {};
@@ -192,110 +156,111 @@
EXPECT_READ32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
{{SPI_DEVICE_INTR_STATE_RXF, 1}});
- EXPECT_EQ(dif_spi_device_irq_get(&spi_, kDifSpiDeviceIrqTypeRxFull, &out),
- kDifSpiDeviceResultOk);
+ EXPECT_EQ(dif_spi_device_irq_is_pending(&spi_, kDifSpiDeviceIrqRxFull, &out),
+ kDifSpiDeviceOk);
EXPECT_TRUE(out);
EXPECT_READ32(
SPI_DEVICE_INTR_STATE_REG_OFFSET,
{{SPI_DEVICE_INTR_STATE_RXERR, 0}, {SPI_DEVICE_INTR_STATE_RXF, 1}});
- EXPECT_EQ(dif_spi_device_irq_get(&spi_, kDifSpiDeviceIrqTypeRxError, &out),
- kDifSpiDeviceResultOk);
+ EXPECT_EQ(dif_spi_device_irq_is_pending(&spi_, kDifSpiDeviceIrqRxError, &out),
+ kDifSpiDeviceOk);
EXPECT_FALSE(out);
EXPECT_READ32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
{{SPI_DEVICE_INTR_STATE_TXUNDERFLOW, 1}});
EXPECT_EQ(
- dif_spi_device_irq_get(&spi_, kDifSpiDeviceIrqTypeTxUnderflow, &out),
- kDifSpiDeviceResultOk);
+ dif_spi_device_irq_is_pending(&spi_, kDifSpiDeviceIrqTxUnderflow, &out),
+ kDifSpiDeviceOk);
EXPECT_TRUE(out);
EXPECT_READ32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
{{SPI_DEVICE_INTR_STATE_TXLVL, 0}});
EXPECT_EQ(
- dif_spi_device_irq_get(&spi_, kDifSpiDeviceIrqTypeTxBelowLevel, &out),
- kDifSpiDeviceResultOk);
+ dif_spi_device_irq_is_pending(&spi_, kDifSpiDeviceIrqTxBelowLevel, &out),
+ kDifSpiDeviceOk);
EXPECT_FALSE(out);
}
TEST_F(IrqTest, GetNull) {
bool out;
- EXPECT_EQ(dif_spi_device_irq_get(nullptr, kDifSpiDeviceIrqTypeRxFull, &out),
- kDifSpiDeviceResultBadArg);
- EXPECT_EQ(dif_spi_device_irq_get(&spi_, kDifSpiDeviceIrqTypeRxFull, nullptr),
- kDifSpiDeviceResultBadArg);
+ EXPECT_EQ(
+ dif_spi_device_irq_is_pending(nullptr, kDifSpiDeviceIrqRxFull, &out),
+ kDifSpiDeviceBadArg);
+ EXPECT_EQ(
+ dif_spi_device_irq_is_pending(&spi_, kDifSpiDeviceIrqRxFull, nullptr),
+ kDifSpiDeviceBadArg);
}
TEST_F(IrqTest, Enable) {
EXPECT_MASK32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
{{SPI_DEVICE_INTR_ENABLE_RXF, 0x1, 1}});
- EXPECT_EQ(dif_spi_device_irq_enable(&spi_, kDifSpiDeviceIrqTypeRxFull,
- kDifSpiDeviceIrqStateEnabled),
- kDifSpiDeviceResultOk);
+ EXPECT_EQ(dif_spi_device_irq_set_enabled(&spi_, kDifSpiDeviceIrqRxFull,
+ kDifSpiDeviceToggleEnabled),
+ kDifSpiDeviceOk);
EXPECT_MASK32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
{{SPI_DEVICE_INTR_ENABLE_RXERR, 0x1, 0}});
- EXPECT_EQ(dif_spi_device_irq_enable(&spi_, kDifSpiDeviceIrqTypeRxError,
- kDifSpiDeviceIrqStateDisabled),
- kDifSpiDeviceResultOk);
+ EXPECT_EQ(dif_spi_device_irq_set_enabled(&spi_, kDifSpiDeviceIrqRxError,
+ kDifSpiDeviceToggleDisabled),
+ kDifSpiDeviceOk);
EXPECT_MASK32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
{{SPI_DEVICE_INTR_ENABLE_TXUNDERFLOW, 0x1, 1}});
- EXPECT_EQ(dif_spi_device_irq_enable(&spi_, kDifSpiDeviceIrqTypeTxUnderflow,
- kDifSpiDeviceIrqStateEnabled),
- kDifSpiDeviceResultOk);
+ EXPECT_EQ(dif_spi_device_irq_set_enabled(&spi_, kDifSpiDeviceIrqTxUnderflow,
+ kDifSpiDeviceToggleEnabled),
+ kDifSpiDeviceOk);
EXPECT_MASK32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
{{SPI_DEVICE_INTR_ENABLE_TXLVL, 0x1, 0}});
- EXPECT_EQ(dif_spi_device_irq_enable(&spi_, kDifSpiDeviceIrqTypeTxBelowLevel,
- kDifSpiDeviceIrqStateDisabled),
- kDifSpiDeviceResultOk);
+ EXPECT_EQ(dif_spi_device_irq_set_enabled(&spi_, kDifSpiDeviceIrqTxBelowLevel,
+ kDifSpiDeviceToggleDisabled),
+ kDifSpiDeviceOk);
}
TEST_F(IrqTest, EnableNull) {
- EXPECT_EQ(dif_spi_device_irq_enable(nullptr, kDifSpiDeviceIrqTypeRxFull,
- kDifSpiDeviceIrqStateEnabled),
- kDifSpiDeviceResultBadArg);
+ EXPECT_EQ(dif_spi_device_irq_set_enabled(nullptr, kDifSpiDeviceIrqRxFull,
+ kDifSpiDeviceToggleEnabled),
+ kDifSpiDeviceBadArg);
}
TEST_F(IrqTest, Force) {
EXPECT_WRITE32(SPI_DEVICE_INTR_TEST_REG_OFFSET,
{{SPI_DEVICE_INTR_TEST_RXF, 1}});
- EXPECT_EQ(dif_spi_device_irq_force(&spi_, kDifSpiDeviceIrqTypeRxFull),
- kDifSpiDeviceResultOk);
+ EXPECT_EQ(dif_spi_device_irq_force(&spi_, kDifSpiDeviceIrqRxFull),
+ kDifSpiDeviceOk);
EXPECT_WRITE32(SPI_DEVICE_INTR_TEST_REG_OFFSET,
{{SPI_DEVICE_INTR_TEST_RXERR, 1}});
- EXPECT_EQ(dif_spi_device_irq_force(&spi_, kDifSpiDeviceIrqTypeRxError),
- kDifSpiDeviceResultOk);
+ EXPECT_EQ(dif_spi_device_irq_force(&spi_, kDifSpiDeviceIrqRxError),
+ kDifSpiDeviceOk);
EXPECT_WRITE32(SPI_DEVICE_INTR_TEST_REG_OFFSET,
{{SPI_DEVICE_INTR_TEST_TXUNDERFLOW, 1}});
- EXPECT_EQ(dif_spi_device_irq_force(&spi_, kDifSpiDeviceIrqTypeTxUnderflow),
- kDifSpiDeviceResultOk);
+ EXPECT_EQ(dif_spi_device_irq_force(&spi_, kDifSpiDeviceIrqTxUnderflow),
+ kDifSpiDeviceOk);
EXPECT_WRITE32(SPI_DEVICE_INTR_TEST_REG_OFFSET,
{{SPI_DEVICE_INTR_TEST_TXLVL, 1}});
- EXPECT_EQ(dif_spi_device_irq_force(&spi_, kDifSpiDeviceIrqTypeTxBelowLevel),
- kDifSpiDeviceResultOk);
+ EXPECT_EQ(dif_spi_device_irq_force(&spi_, kDifSpiDeviceIrqTxBelowLevel),
+ kDifSpiDeviceOk);
}
TEST_F(IrqTest, ForceNull) {
- EXPECT_EQ(dif_spi_device_irq_force(nullptr, kDifSpiDeviceIrqTypeRxFull),
- kDifSpiDeviceResultBadArg);
+ EXPECT_EQ(dif_spi_device_irq_force(nullptr, kDifSpiDeviceIrqRxFull),
+ kDifSpiDeviceBadArg);
}
TEST_F(IrqTest, Levels) {
EXPECT_WRITE32(SPI_DEVICE_FIFO_LEVEL_REG_OFFSET,
{{SPI_DEVICE_FIFO_LEVEL_RXLVL_OFFSET, 42},
{SPI_DEVICE_FIFO_LEVEL_TXLVL_OFFSET, 123}});
- EXPECT_EQ(dif_spi_device_set_irq_levels(&spi_, 42, 123),
- kDifSpiDeviceResultOk);
+ EXPECT_EQ(dif_spi_device_set_irq_levels(&spi_, 42, 123), kDifSpiDeviceOk);
}
TEST_F(IrqTest, LevelsNull) {
EXPECT_EQ(dif_spi_device_set_irq_levels(nullptr, 123, 456),
- kDifSpiDeviceResultBadArg);
+ kDifSpiDeviceBadArg);
}
class RxPendingTest : public SpiTest {};
@@ -306,7 +271,7 @@
{SPI_DEVICE_RXF_PTR_RPTR_OFFSET, 0x0}});
size_t bytes_remaining;
EXPECT_EQ(dif_spi_device_rx_pending(&spi_, &bytes_remaining),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(bytes_remaining, 0);
}
@@ -316,7 +281,7 @@
{SPI_DEVICE_RXF_PTR_RPTR_OFFSET, FifoPtr(0x42, true)}});
size_t bytes_remaining;
EXPECT_EQ(dif_spi_device_rx_pending(&spi_, &bytes_remaining),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(bytes_remaining, 0);
}
@@ -326,7 +291,7 @@
{SPI_DEVICE_RXF_PTR_RPTR_OFFSET, FifoPtr(0x42, true)}});
size_t bytes_remaining;
EXPECT_EQ(dif_spi_device_rx_pending(&spi_, &bytes_remaining),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(bytes_remaining, 0x15);
}
@@ -336,7 +301,7 @@
{SPI_DEVICE_RXF_PTR_RPTR_OFFSET, FifoPtr(0x42, true)}});
size_t bytes_remaining;
EXPECT_EQ(dif_spi_device_rx_pending(&spi_, &bytes_remaining),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(bytes_remaining, 0x400);
}
@@ -346,16 +311,15 @@
{SPI_DEVICE_RXF_PTR_RPTR_OFFSET, FifoPtr(0x57, true)}});
size_t bytes_remaining;
EXPECT_EQ(dif_spi_device_rx_pending(&spi_, &bytes_remaining),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(bytes_remaining, 0x3eb);
}
TEST_F(RxPendingTest, NullArgs) {
size_t bytes_remaining;
EXPECT_EQ(dif_spi_device_rx_pending(nullptr, &bytes_remaining),
- kDifSpiDeviceResultBadArg);
- EXPECT_EQ(dif_spi_device_rx_pending(&spi_, nullptr),
- kDifSpiDeviceResultBadArg);
+ kDifSpiDeviceBadArg);
+ EXPECT_EQ(dif_spi_device_rx_pending(&spi_, nullptr), kDifSpiDeviceBadArg);
}
class TxPendingTest : public SpiTest {};
@@ -366,7 +330,7 @@
{SPI_DEVICE_TXF_PTR_RPTR_OFFSET, 0x0}});
size_t bytes_remaining;
EXPECT_EQ(dif_spi_device_tx_pending(&spi_, &bytes_remaining),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(bytes_remaining, 0);
}
@@ -376,7 +340,7 @@
{SPI_DEVICE_TXF_PTR_RPTR_OFFSET, FifoPtr(0x42, true)}});
size_t bytes_remaining;
EXPECT_EQ(dif_spi_device_tx_pending(&spi_, &bytes_remaining),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(bytes_remaining, 0);
}
@@ -386,7 +350,7 @@
{SPI_DEVICE_TXF_PTR_RPTR_OFFSET, FifoPtr(0x42, true)}});
size_t bytes_remaining;
EXPECT_EQ(dif_spi_device_tx_pending(&spi_, &bytes_remaining),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(bytes_remaining, 0x15);
}
@@ -396,7 +360,7 @@
{SPI_DEVICE_TXF_PTR_RPTR_OFFSET, FifoPtr(0x42, true)}});
size_t bytes_remaining;
EXPECT_EQ(dif_spi_device_tx_pending(&spi_, &bytes_remaining),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(bytes_remaining, 0x400);
}
@@ -406,16 +370,15 @@
{SPI_DEVICE_TXF_PTR_RPTR_OFFSET, FifoPtr(0x57, true)}});
size_t bytes_remaining;
EXPECT_EQ(dif_spi_device_tx_pending(&spi_, &bytes_remaining),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(bytes_remaining, 0x3eb);
}
TEST_F(TxPendingTest, NullArgs) {
size_t bytes_remaining;
EXPECT_EQ(dif_spi_device_tx_pending(nullptr, &bytes_remaining),
- kDifSpiDeviceResultBadArg);
- EXPECT_EQ(dif_spi_device_tx_pending(&spi_, nullptr),
- kDifSpiDeviceResultBadArg);
+ kDifSpiDeviceBadArg);
+ EXPECT_EQ(dif_spi_device_tx_pending(&spi_, nullptr), kDifSpiDeviceBadArg);
}
class RecvTest : public SpiTest {};
@@ -429,7 +392,7 @@
size_t recv_len = 0;
EXPECT_EQ(dif_spi_device_recv(&spi_, const_cast<char *>(buf.data()),
buf.size(), &recv_len),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(recv_len, 0);
buf.resize(recv_len);
EXPECT_EQ(buf, "");
@@ -441,7 +404,7 @@
{SPI_DEVICE_RXF_PTR_RPTR_OFFSET, FifoPtr(0x50, false)}});
auto message = MakeBlob(kFifoLen);
- auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.rx_fifo_base;
+ auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET;
for (int i = 0; i < kFifoLen; i += 4) {
auto idx = fifo_base + (i + 0x50) % kFifoLen;
EXPECT_READ32(idx, LeInt(&message[i]));
@@ -455,7 +418,7 @@
buf.resize(message.size() * 2);
size_t recv_len = 0;
EXPECT_EQ(dif_spi_device_recv(&spi_, buf.data(), buf.size(), &recv_len),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(recv_len, message.size());
buf.resize(recv_len);
EXPECT_EQ(buf, message);
@@ -469,7 +432,7 @@
{SPI_DEVICE_RXF_PTR_RPTR_OFFSET, FifoPtr(0x50, false)}});
auto message = MakeBlob(kFifoLen);
- auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.rx_fifo_base;
+ auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET;
for (size_t i = 0; i < buf_len; i += 4) {
auto idx = fifo_base + (i + 0x50) % kFifoLen;
EXPECT_READ32(idx, LeInt(&message[i]));
@@ -484,7 +447,7 @@
buf.resize(buf_len);
size_t recv_len = 0;
EXPECT_EQ(dif_spi_device_recv(&spi_, buf.data(), buf.size(), &recv_len),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(recv_len, buf_len);
buf.resize(recv_len);
message.resize(recv_len);
@@ -500,7 +463,7 @@
{{SPI_DEVICE_RXF_PTR_WPTR_OFFSET, FifoPtr(message.size(), false)},
{SPI_DEVICE_RXF_PTR_RPTR_OFFSET, FifoPtr(0x00, false)}});
- auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.rx_fifo_base;
+ auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET;
EXPECT_READ32(fifo_base + 0x0, LeInt(&message[0x0]));
EXPECT_READ32(fifo_base + 0x4, LeInt(&message[0x4]));
EXPECT_READ32(fifo_base + 0x8, LeInt(&message[0x8]));
@@ -514,7 +477,7 @@
size_t recv_len = 0;
EXPECT_EQ(dif_spi_device_recv(&spi_, const_cast<char *>(buf.data()),
buf.size(), &recv_len),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(recv_len, message.size());
buf.resize(recv_len);
EXPECT_EQ(buf, message);
@@ -529,7 +492,7 @@
{{SPI_DEVICE_RXF_PTR_WPTR_OFFSET, FifoPtr(cropped_len, false)},
{SPI_DEVICE_RXF_PTR_RPTR_OFFSET, FifoPtr(0x00, false)}});
- auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.rx_fifo_base;
+ auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET;
EXPECT_READ32(fifo_base + 0x0, LeInt(&message[0x0]));
EXPECT_READ32(fifo_base + 0x4, LeInt(&message[0x4]));
EXPECT_READ32(fifo_base + 0x8, LeInt(&message[0x8]));
@@ -543,7 +506,7 @@
size_t recv_len = 0;
EXPECT_EQ(dif_spi_device_recv(&spi_, const_cast<char *>(buf.data()),
buf.size(), &recv_len),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(recv_len, cropped_len);
buf.resize(message.size());
@@ -564,7 +527,7 @@
{{SPI_DEVICE_RXF_PTR_WPTR_OFFSET, FifoPtr(cropped_len, false)},
{SPI_DEVICE_RXF_PTR_RPTR_OFFSET, FifoPtr(cropped_start, false)}});
- auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.rx_fifo_base;
+ auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET;
EXPECT_READ32(fifo_base + 0x0, LeInt(&message[0x0]));
EXPECT_READ32(fifo_base + 0x4, LeInt(&message[0x4]));
EXPECT_READ32(fifo_base + 0x8, LeInt(&message[0x8]));
@@ -578,7 +541,7 @@
size_t recv_len = 0;
EXPECT_EQ(dif_spi_device_recv(&spi_, const_cast<char *>(buf.data()),
buf.size(), &recv_len),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(recv_len, cropped_len - cropped_start);
buf.resize(message.size());
@@ -599,7 +562,7 @@
{{SPI_DEVICE_RXF_PTR_WPTR_OFFSET, FifoPtr(cropped_len, false)},
{SPI_DEVICE_RXF_PTR_RPTR_OFFSET, FifoPtr(cropped_start, false)}});
- auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.rx_fifo_base;
+ auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET;
EXPECT_READ32(fifo_base + 0x0, LeInt(&message[0x0]));
EXPECT_WRITE32(
@@ -611,7 +574,7 @@
size_t recv_len = 0;
EXPECT_EQ(dif_spi_device_recv(&spi_, const_cast<char *>(buf.data()),
buf.size(), &recv_len),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(recv_len, cropped_len - cropped_start);
buf.resize(message.size());
@@ -627,16 +590,16 @@
EXPECT_EQ(dif_spi_device_recv(nullptr, const_cast<char *>(buf.data()),
buf.size(), &recv_len),
- kDifSpiDeviceResultBadArg);
+ kDifSpiDeviceBadArg);
EXPECT_EQ(dif_spi_device_recv(&spi_, nullptr, buf.size(), &recv_len),
- kDifSpiDeviceResultBadArg);
+ kDifSpiDeviceBadArg);
EXPECT_READ32(SPI_DEVICE_RXF_PTR_REG_OFFSET,
{{SPI_DEVICE_RXF_PTR_WPTR_OFFSET, FifoPtr(0x5a, false)},
{SPI_DEVICE_RXF_PTR_RPTR_OFFSET, FifoPtr(0x5a, false)}});
EXPECT_EQ(dif_spi_device_recv(&spi_, const_cast<char *>(buf.data()),
buf.size(), nullptr),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
}
class SendTest : public SpiTest {};
@@ -650,7 +613,7 @@
size_t send_len = 0;
EXPECT_EQ(
dif_spi_device_send(&spi_, message.data(), message.size(), &send_len),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(send_len, 0);
}
@@ -660,7 +623,7 @@
{SPI_DEVICE_TXF_PTR_RPTR_OFFSET, FifoPtr(0x50, true)}});
auto message = MakeBlob(kFifoLen);
- auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.tx_fifo_base;
+ auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.rx_fifo_len;
for (int i = 0; i < kFifoLen; i += 4) {
auto idx = fifo_base + (i + 0x50) % kFifoLen;
EXPECT_WRITE32(idx, LeInt(&message[i]));
@@ -673,7 +636,7 @@
size_t sent_len = 0;
EXPECT_EQ(
dif_spi_device_send(&spi_, message.data(), message.size(), &sent_len),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(sent_len, message.size());
}
@@ -686,7 +649,7 @@
uintptr_t value = 0;
memcpy(&value, message.data(), 2);
- auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.tx_fifo_base;
+ auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.rx_fifo_len;
EXPECT_MASK32(fifo_base + 0x4c, {{0x10, 0xffff, value}});
EXPECT_WRITE32(SPI_DEVICE_TXF_PTR_REG_OFFSET,
@@ -696,7 +659,7 @@
size_t sent_len = 0;
EXPECT_EQ(
dif_spi_device_send(&spi_, message.data(), message.size(), &sent_len),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(sent_len, 2);
}
@@ -708,7 +671,7 @@
{{SPI_DEVICE_TXF_PTR_WPTR_OFFSET, FifoPtr(0x00, false)},
{SPI_DEVICE_TXF_PTR_RPTR_OFFSET, FifoPtr(0x00, false)}});
- auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.tx_fifo_base;
+ auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.rx_fifo_len;
EXPECT_WRITE32(fifo_base + 0x0, LeInt(&message[0x0]));
EXPECT_WRITE32(fifo_base + 0x4, LeInt(&message[0x4]));
EXPECT_WRITE32(fifo_base + 0x8, LeInt(&message[0x8]));
@@ -721,7 +684,7 @@
size_t send_len = 0;
EXPECT_EQ(
dif_spi_device_send(&spi_, message.data(), message.size(), &send_len),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(send_len, message.size());
}
@@ -734,7 +697,7 @@
{{SPI_DEVICE_TXF_PTR_WPTR_OFFSET, FifoPtr(0x00, false)},
{SPI_DEVICE_TXF_PTR_RPTR_OFFSET, FifoPtr(0x00, false)}});
- auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.tx_fifo_base;
+ auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.rx_fifo_len;
EXPECT_WRITE32(fifo_base + 0x0, LeInt(&message[0x0]));
EXPECT_WRITE32(fifo_base + 0x4, LeInt(&message[0x4]));
@@ -748,7 +711,7 @@
size_t send_len = 0;
EXPECT_EQ(dif_spi_device_send(&spi_, message.data(), cropped_len, &send_len),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(send_len, cropped_len);
}
@@ -763,7 +726,7 @@
{{SPI_DEVICE_TXF_PTR_WPTR_OFFSET, FifoPtr(cropped_start, false)},
{SPI_DEVICE_TXF_PTR_RPTR_OFFSET, FifoPtr(cropped_start, false)}});
- auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.tx_fifo_base;
+ auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.rx_fifo_len;
uintptr_t start_value = 0;
memcpy(&start_value, &message[0x0], 3);
@@ -782,7 +745,7 @@
size_t send_len = 0;
EXPECT_EQ(dif_spi_device_send(&spi_, message.data(), cropped_len, &send_len),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(send_len, cropped_len);
}
@@ -797,7 +760,7 @@
{{SPI_DEVICE_TXF_PTR_WPTR_OFFSET, FifoPtr(cropped_start, false)},
{SPI_DEVICE_TXF_PTR_RPTR_OFFSET, FifoPtr(cropped_start, false)}});
- auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.tx_fifo_base;
+ auto fifo_base = SPI_DEVICE_BUFFER_REG_OFFSET + spi_.rx_fifo_len;
uintptr_t start_value = 0;
memcpy(&start_value, &message[0x0], 2);
@@ -811,7 +774,7 @@
size_t send_len = 0;
EXPECT_EQ(dif_spi_device_send(&spi_, message.data(), cropped_len, &send_len),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
EXPECT_EQ(send_len, cropped_len);
}
@@ -820,15 +783,15 @@
size_t recv_len;
EXPECT_EQ(dif_spi_device_send(nullptr, buf.data(), buf.size(), &recv_len),
- kDifSpiDeviceResultBadArg);
+ kDifSpiDeviceBadArg);
EXPECT_EQ(dif_spi_device_send(&spi_, nullptr, buf.size(), &recv_len),
- kDifSpiDeviceResultBadArg);
+ kDifSpiDeviceBadArg);
EXPECT_READ32(SPI_DEVICE_TXF_PTR_REG_OFFSET,
{{SPI_DEVICE_TXF_PTR_WPTR_OFFSET, FifoPtr(0x5a, true)},
{SPI_DEVICE_TXF_PTR_RPTR_OFFSET, FifoPtr(0x5a, false)}});
EXPECT_EQ(dif_spi_device_send(&spi_, buf.data(), buf.size(), nullptr),
- kDifSpiDeviceResultOk);
+ kDifSpiDeviceOk);
}
} // namespace
} // namespace dif_spi_device_unittest
