| commit | 66c509296798cdd9dbeba4deeb381d0cecf3b429 | [log] [tgz] |
|---|---|---|
| author | Mark Hayter <mark.hayter@gmail.com> | Sun Jul 05 19:30:54 2020 -0700 |
| committer | Pirmin Vogel <vogelpi@lowrisc.org> | Tue Sep 29 16:17:52 2020 +0200 |
| tree | fc3fe2eb408f53c352f60a59e340648986bdd28a | |
| parent | 3ad4fd1bb674ea103204af0892b5c8d870b2159f [diff] |
[usbdev] Fixes for I/O modes and expand their tests The differental mode reception and conversion was being done in the iomux and potentially not passing all information to the usb_fs_rx module. Reworked to pass the single ended and differential data to usb_fs_rx, recover them both and use the configured mode to forward appropriately. This changes the usbdev_iomux to only synchronize and pinflip I/O and pass the rx d, d+ and d- to receive logic. As part of debug fixed verilator UNOPTFLAT complaint and added a link state representing the link being active but never seen SOF because this is where a flipped link gets stuck between FPGA board and Linux. (The flipped pullup will make it look like a LS not FS link so the 1.5Mbit chatter is enough to get rx PID erros but also keeps resetting the link so host_lost never fires). Update verilator top and usbdpi to manage all the I/Os. And add code to the usbdpi to be able to simulate pinflip and differential as well as the normal pin mode. Note that because there is no other signal it uses the tx_mode_se signal to control use of differential mode in both tx and rx directions (so it only works if both phy config bits are the same). It uses the DN PULLUP being asserted to detect flip. Update hello_usbdev.c to set the phy config from gpio pins. These are switches on the nexysvideo and can be set using gpio-dpi in verilator. Update top_earlgrey_nexysvideo to be able to fake swapping of USB pins. Uses DN pullup to cause the pins used for DP and DN to be swapped, allows testing of both flip options with one FPGA build. Tested with verilator that all four settings of PINFLIP and DIFFIO in hello_usb.c get the same expected output. Added a script to run all four simulations (setting the GPIOs to control). Tested with FPGA that PINFLIP=0,1 both work by setting the switch. Included changes requested in software and hardware reviews. Fixes lowRISC/OpenTitan#2598 Signed-off-by: Mark Hayter <mark.hayter@gmail.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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