| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| { |
| name: "sysrst_ctrl", |
| design_spec: "../doc", |
| dv_doc: "../doc/dv", |
| hw_checklist: "../doc/checklist", |
| sw_checklist: "/sw/device/lib/dif/dif_sysrst_ctrl", |
| version: "1.0", |
| life_stage: "L1", |
| design_stage: "D3", |
| verification_stage: "V2S", |
| dif_stage: "S2", |
| clocking: [ |
| {clock: "clk_i", reset: "rst_ni", primary: true}, |
| {clock: "clk_aon_i", reset: "rst_aon_ni"} |
| ] |
| bus_interfaces: [ |
| { protocol: "tlul", direction: "device" } |
| ], |
| interrupt_list: [ |
| { name: "event_detected", |
| desc: "Common interrupt triggered by combo or keyboard events.", |
| } |
| ], |
| alert_list: [ |
| { name: "fatal_fault", |
| desc: ''' |
| This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. |
| ''' |
| } |
| ], |
| wakeup_list: [ |
| { name: "wkup_req", |
| desc: "OpenTitan wake request signal to `pwrmgr` (running on AON clock).", |
| } |
| ], |
| reset_request_list: [ |
| { name: "rst_req", |
| desc: "OpenTitan reset request to `rstmgr` (running on AON clock)." |
| }, |
| ], |
| param_list: [ |
| { name: "NumCombo", |
| type: "int", |
| default: "4", |
| desc: "Number of keyboard combos", |
| local: "true", |
| } |
| { name: "TimerWidth", |
| type: "int", |
| default: "16", |
| desc: "Number of timer bits", |
| local: "true", |
| } |
| { name: "DetTimerWidth", |
| type: "int", |
| default: "32", |
| desc: "Number of detection timer bits", |
| local: "true", |
| } |
| ], |
| available_inout_list: [ |
| { name: "ec_rst_l", desc: "ec_rst_l as an inout to/from the open drain IO" } |
| { name: "flash_wp_l", desc: "flash_wp_l as an inout to/from the open drain IO" } |
| ], |
| available_input_list: [ |
| { name: "ac_present", desc: "A/C power is present" } |
| { name: "key0_in", desc: "VolUp button in tablet; column output from the EC in a laptop" } |
| { name: "key1_in", desc: "VolDown button in tablet; row input from keyboard matrix in a laptop" } |
| { name: "key2_in", desc: "TBD button in tablet; row input from keyboard matrix in a laptop" } |
| { name: "pwrb_in", desc: "Power button in both tablet and laptop" } |
| { name: "lid_open", desc: "Lid is open" } |
| ], |
| available_output_list: [ |
| { name: "bat_disable", desc: "Battery is disconnected" } |
| { name: "key0_out", desc: "Passthrough from key0_in, can be configured to invert" } |
| { name: "key1_out", desc: "Passthrough from key1_in, can be configured to invert" } |
| { name: "key2_out", desc: "Passthrough from key2_in, can be configured to invert" } |
| { name: "pwrb_out", desc: "Passthrough from pwrb_in, can be configured to invert" } |
| { name: "z3_wakeup", desc: "To enter Z3 mode and exit from Z4 sleep mode" } |
| ], |
| inter_signal_list: [ |
| { name: "wkup_req", |
| package: "", |
| struct: "logic", |
| act: "req" |
| type: "uni", |
| width: "1" |
| } |
| { name: "rst_req", |
| package: "", |
| struct: "logic", |
| act: "req" |
| type: "uni", |
| width: "1" |
| } |
| ], |
| countermeasures: [ |
| { name: "BUS.INTEGRITY", |
| desc: "End-to-end bus integrity scheme." |
| } |
| ] |
| regwidth: "32", |
| registers: [ |
| { name: "REGWEN", |
| desc: "Configuration write enable control register", |
| swaccess: "rw0c", |
| hwaccess: "none", |
| resval: "1", |
| fields: [ |
| { bits: "0", |
| name: "write_en", |
| desc: '''config write enable. |
| 0: cfg is locked(not writable); 1: cfg is not locked(writable) |
| ''', |
| } |
| ] |
| } |
| { name: "EC_RST_CTL", |
| desc: "EC reset control register", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "REGWEN", |
| resval: "2000", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "TimerWidth-1:0", |
| name: "ec_rst_pulse", |
| desc: "Configure the pulse width of ec_rst_l. 10-200ms, each step is 5us(200KHz clock)", |
| } |
| ], |
| } |
| { name: "ULP_AC_DEBOUNCE_CTL", |
| desc: "Ultra low power AC debounce control register", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "REGWEN", |
| resval: "8000", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "TimerWidth-1:0", |
| name: "ulp_ac_debounce_timer", |
| desc: "Configure the debounce timer. 10-200ms, each step is 5us(200KHz clock)", |
| } |
| ], |
| } |
| { name: "ULP_LID_DEBOUNCE_CTL", |
| desc: "Ultra low power lid debounce control register", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "REGWEN", |
| resval: "8000", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "TimerWidth-1:0", |
| name: "ulp_lid_debounce_timer", |
| desc: "Configure the debounce timer. 10-200ms, each step is 5us(200KHz clock)", |
| } |
| ], |
| } |
| { name: "ULP_PWRB_DEBOUNCE_CTL", |
| desc: "Ultra low power pwrb debounce control register", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "REGWEN", |
| resval: "8000", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "TimerWidth-1:0", |
| name: "ulp_pwrb_debounce_timer", |
| desc: "Configure the debounce timer. 10-200ms, each step is 5us(200KHz clock)", |
| } |
| ], |
| } |
| { name: "ULP_CTL", |
| desc: "Ultra low power control register", |
| swaccess: "rw", |
| hwaccess: "hro", |
| resval: "0", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "0", |
| name: "ulp_enable", |
| desc: "0: disable ULP wakeup feature and reset the ULP FSM; 1: enable ULP wakeup feature", |
| } |
| ], |
| } |
| { name: "ULP_STATUS", |
| desc: "Ultra low power status", |
| swaccess: "rw1c", |
| hwaccess: "hwo", |
| resval: "0", |
| async: "clk_aon_i", |
| tags: [ // the value of these regs is determined by the |
| // value on the pins, hence it cannot be predicted. |
| "excl:CsrNonInitTests:CsrExclCheck"], |
| fields: [ |
| { bits: "0", |
| name: "ulp_wakeup", |
| desc: "0: ULP wakeup not detected; 1: ULP wakeup event is detected", |
| } |
| ], |
| } |
| { name: "WKUP_STATUS", |
| desc: "wakeup status", |
| swaccess: "rw1c", |
| hwaccess: "hrw", |
| resval: "0", |
| async: "clk_aon_i", |
| tags: [ // the value of these regs is determined by the |
| // value on the pins, hence it cannot be predicted. |
| "excl:CsrNonInitTests:CsrExclCheck"], |
| fields: [ |
| { bits: "0", |
| name: "wakeup_sts", |
| desc: "0: wakeup event not detected; 1: wakeup event is detected", |
| } |
| ], |
| } |
| { name: "KEY_INVERT_CTL", |
| desc: "configure key input output invert property", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "REGWEN", |
| resval: "0", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "0", |
| name: "key0_in", |
| desc: "0: don't invert; 1: invert", |
| resval: "0", |
| } |
| { bits: "1", |
| name: "key0_out", |
| desc: "0: don't invert; 1: invert", |
| resval: "0", |
| } |
| { bits: "2", |
| name: "key1_in", |
| desc: "0: don't invert; 1: invert", |
| resval: "0", |
| } |
| { bits: "3", |
| name: "key1_out", |
| desc: "0: don't invert; 1: invert", |
| resval: "0", |
| } |
| { bits: "4", |
| name: "key2_in", |
| desc: "0: don't invert; 1: invert", |
| resval: "0", |
| } |
| { bits: "5", |
| name: "key2_out", |
| desc: "0: don't invert; 1: invert", |
| resval: "0", |
| } |
| { bits: "6", |
| name: "pwrb_in", |
| desc: "0: don't invert; 1: invert", |
| resval: "0", |
| } |
| { bits: "7", |
| name: "pwrb_out", |
| desc: "0: don't invert; 1: invert", |
| resval: "0", |
| } |
| { bits: "8", |
| name: "ac_present", |
| desc: "0: don't invert; 1: invert", |
| resval: "0", |
| } |
| { bits: "9", |
| name: "bat_disable", |
| desc: "0: don't invert; 1: invert", |
| resval: "0", |
| } |
| { bits: "10", |
| name: "lid_open", |
| desc: "0: don't invert; 1: invert", |
| resval: "0", |
| } |
| { bits: "11", |
| name: "z3_wakeup", |
| desc: "0: don't invert; 1: invert", |
| resval: "0", |
| } |
| ] |
| } |
| { name: "PIN_ALLOWED_CTL", |
| desc: ''' |
| This register determines which override values are allowed for a given output. |
| If an override value programmed via !!PIN_OUT_VALUE is not configured as an allowed value, |
| it will not have any effect. |
| ''', |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "REGWEN", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "0", |
| name: "bat_disable_0", |
| desc: "0: not allowed; 1: allowed", |
| resval: "0", |
| } |
| { bits: "1", |
| name: "ec_rst_l_0", |
| desc: "0: not allowed; 1: allowed", |
| resval: "1", |
| } |
| { bits: "2", |
| name: "pwrb_out_0", |
| desc: "0: not allowed; 1: allowed", |
| resval: "0", |
| } |
| { bits: "3", |
| name: "key0_out_0", |
| desc: "0: not allowed; 1: allowed", |
| resval: "0", |
| } |
| { bits: "4", |
| name: "key1_out_0", |
| desc: "0: not allowed; 1: allowed", |
| resval: "0", |
| } |
| { bits: "5", |
| name: "key2_out_0", |
| desc: "0: not allowed; 1: allowed", |
| resval: "0", |
| } |
| { bits: "6", |
| name: "z3_wakeup_0", |
| desc: "0: not allowed; 1: allowed", |
| resval: "0", |
| } |
| { bits: "7", |
| name: "flash_wp_l_0", |
| desc: "0: not allowed; 1: allowed", |
| resval: "1", |
| } |
| { bits: "8", |
| name: "bat_disable_1", |
| desc: "0: not allowed; 1: allowed", |
| resval: "0", |
| } |
| { bits: "9", |
| name: "ec_rst_l_1", |
| desc: "0: not allowed; 1: allowed", |
| resval: "0", |
| } |
| { bits: "10", |
| name: "pwrb_out_1", |
| desc: "0: not allowed; 1: allowed", |
| resval: "0", |
| } |
| { bits: "11", |
| name: "key0_out_1", |
| desc: "0: not allowed; 1: allowed", |
| resval: "0", |
| } |
| { bits: "12", |
| name: "key1_out_1", |
| desc: "0: not allowed; 1: allowed", |
| resval: "0", |
| } |
| { bits: "13", |
| name: "key2_out_1", |
| desc: "0: not allowed; 1: allowed", |
| resval: "0", |
| } |
| { bits: "14", |
| name: "z3_wakeup_1", |
| desc: "0: not allowed; 1: allowed", |
| resval: "0", |
| } |
| { bits: "15", |
| name: "flash_wp_l_1", |
| desc: "0: not allowed; 1: allowed", |
| resval: "0", |
| } |
| ] |
| } |
| { name: "PIN_OUT_CTL", |
| desc: "Enables the override function for a specific pin.", |
| swaccess: "rw", |
| hwaccess: "hro", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "0", |
| name: "bat_disable", |
| desc: "0: disable override; 1: enable override", |
| resval: "0", |
| } |
| { bits: "1", |
| name: "ec_rst_l", |
| desc: "0: disable override; 1: enable override", |
| resval: "1", |
| } |
| { bits: "2", |
| name: "pwrb_out", |
| desc: "0: disable override; 1: enable override", |
| resval: "0", |
| } |
| { bits: "3", |
| name: "key0_out", |
| desc: "0: disable override; 1: enable override", |
| resval: "0", |
| } |
| { bits: "4", |
| name: "key1_out", |
| desc: "0: disable override; 1: enable override", |
| resval: "0", |
| } |
| { bits: "5", |
| name: "key2_out", |
| desc: "0: disable override; 1: enable override", |
| resval: "0", |
| } |
| { bits: "6", |
| name: "z3_wakeup", |
| desc: "0: disable override; 1: enable override", |
| resval: "0", |
| } |
| { bits: "7", |
| name: "flash_wp_l", |
| desc: "0: disable override; 1: enable override", |
| resval: "1", |
| } |
| ] |
| } |
| { name: "PIN_OUT_VALUE", |
| desc: ''' |
| Sets the pin override value. Note that only the values |
| configured as 'allowed' in !!PIN_ALLOWED_CTL will have |
| an effect. Otherwise the pin value will not be overridden. |
| ''', |
| swaccess: "rw", |
| hwaccess: "hro", |
| resval: "0", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "0", |
| name: "bat_disable", |
| desc: "0: override to 1b0; 1: override to 1b1", |
| resval: "0", |
| } |
| { bits: "1", |
| name: "ec_rst_l", |
| desc: "0: override to 1b0; 1: override to 1b1", |
| resval: "0", |
| } |
| { bits: "2", |
| name: "pwrb_out", |
| desc: "0: override to 1b0; 1: override to 1b1", |
| resval: "0", |
| } |
| { bits: "3", |
| name: "key0_out", |
| desc: "0: override to 1b0; 1: override to 1b1", |
| resval: "0", |
| } |
| { bits: "4", |
| name: "key1_out", |
| desc: "0: override to 1b0; 1: override to 1b1", |
| resval: "0", |
| } |
| { bits: "5", |
| name: "key2_out", |
| desc: "0: override to 1b0; 1: override to 1b1", |
| resval: "0", |
| } |
| { bits: "6", |
| name: "z3_wakeup", |
| desc: "0: override to 1b0; 1: override to 1b1", |
| resval: "0", |
| } |
| { bits: "7", |
| name: "flash_wp_l", |
| desc: "0: override to 1b0; 1: override to 1b1", |
| resval: "0", |
| } |
| ] |
| } |
| { name: "PIN_IN_VALUE", |
| desc: "For SW to read the sysrst_ctrl inputs like GPIO", |
| swaccess: "ro", |
| hwaccess: "hwo", |
| resval: "0", |
| tags: [ // the value of these regs is determined by the |
| // value on the pins, hence it cannot be predicted. |
| "excl:CsrAllTests:CsrExclCheck"], |
| fields: [ |
| { bits: "0", |
| name: "pwrb_in", |
| desc: "raw pwrb_in value; before the invert logic", |
| resval: "0", |
| } |
| { bits: "1", |
| name: "key0_in", |
| desc: "raw key0_in value; before the invert logic", |
| resval: "0", |
| } |
| { bits: "2", |
| name: "key1_in", |
| desc: "raw key1_in value; before the invert logic", |
| resval: "0", |
| } |
| { bits: "3", |
| name: "key2_in", |
| desc: "raw key2_in value; before the invert logic", |
| resval: "0", |
| } |
| { bits: "4", |
| name: "lid_open", |
| desc: "raw lid_open value; before the invert logic", |
| resval: "0", |
| } |
| { bits: "5", |
| name: "ac_present", |
| desc: "raw ac_present value; before the invert logic", |
| resval: "0", |
| } |
| { bits: "6", |
| name: "ec_rst_l", |
| desc: "raw ec_rst_l value; before the invert logic", |
| resval: "0", |
| } |
| { bits: "7", |
| name: "flash_wp_l", |
| desc: "raw flash_wp_l value; before the invert logic", |
| resval: "0", |
| } |
| ] |
| } |
| { name: "KEY_INTR_CTL", |
| desc: "Define the keys or inputs that can trigger the interrupt ", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "REGWEN", |
| resval: "0", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "0", |
| name: "pwrb_in_H2L", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "1", |
| name: "key0_in_H2L", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "2", |
| name: "key1_in_H2L", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "3", |
| name: "key2_in_H2L", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "4", |
| name: "ac_present_H2L", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "5", |
| name: "ec_rst_l_H2L", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "6", |
| name: "flash_wp_l_H2L", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "7", |
| name: "pwrb_in_L2H", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "8", |
| name: "key0_in_L2H", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "9", |
| name: "key1_in_L2H", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "10", |
| name: "key2_in_L2H", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "11", |
| name: "ac_present_L2H", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "12", |
| name: "ec_rst_l_L2H", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "13", |
| name: "flash_wp_l_L2H", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| ] |
| } |
| { name: "KEY_INTR_DEBOUNCE_CTL", |
| desc: "Debounce timer control register for key-triggered interrupt", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "REGWEN", |
| resval: "2000", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "TimerWidth-1:0", |
| name: "debounce_timer", |
| desc: "Define the timer value so that the key or input is not oscillating for 0-200ms, each step is 5us(200KHz clock)", |
| } |
| ], |
| } |
| { name: "AUTO_BLOCK_DEBOUNCE_CTL", |
| desc: "Debounce timer control register for pwrb_in H2L transition", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "REGWEN", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "TimerWidth-1:0", |
| name: "debounce_timer", |
| desc: "Define the timer value so that pwrb_in is not oscillating for 0-200ms, each step is 5us(200KHz clock)", |
| resval: "2000", |
| } |
| { bits: "16", |
| name: "auto_block_enable", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| ], |
| } |
| { name: "AUTO_BLOCK_OUT_CTL", |
| desc: "configure the key outputs to auto-override and their value", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "REGWEN", |
| resval: "0", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "0", |
| name: "key0_out_sel", |
| desc: "0: disable auto-block; 1: enable auto-block", |
| resval: "0", |
| } |
| { bits: "1", |
| name: "key1_out_sel", |
| desc: "0: disable auto-block; 1: enable auto-block", |
| resval: "0", |
| } |
| { bits: "2", |
| name: "key2_out_sel", |
| desc: "0: disable auto-block; 1: enable auto-block", |
| resval: "0", |
| } |
| { bits: "4", |
| name: "key0_out_value", |
| desc: "0: override to 1'b0; 1: override to 1'b1", |
| resval: "0", |
| } |
| { bits: "5", |
| name: "key1_out_value", |
| desc: "0: override to 1'b0; 1: override to 1'b1", |
| resval: "0", |
| } |
| { bits: "6", |
| name: "key2_out_value", |
| desc: "0: override to 1'b0; 1: override to 1'b1", |
| resval: "0", |
| } |
| ] |
| } |
| { multireg: { |
| name: "COM_PRE_SEL_CTL", |
| desc: ''' |
| To define the keys that define the pre-condition of the combo |
| [0]: key0_in_sel |
| [1]: key1_in_sel |
| [2]: key2_in_sel |
| [3]: pwrb_in_sel |
| [4]: ac_present_sel |
| HW will start matching the combo as defined by !!COM_SEL_CTL if this precondition is fulfilled. |
| |
| If no keys are configured for the pre-condition, the pre-condition always evaluates to true. |
| |
| The debounce timing is defined via !!KEY_INTR_DEBOUNCE_CTL whereas the pre-condition pressed timing is defined via !!COM_PRE_DET_CTL. |
| ''', |
| count: "NumCombo", |
| cname: "sysrst_ctrl", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "REGWEN", |
| resval: "0", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "0", |
| name: "key0_in_sel", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "1", |
| name: "key1_in_sel", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "2", |
| name: "key2_in_sel", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "3", |
| name: "pwrb_in_sel", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "4", |
| name: "ac_present_sel", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| ], |
| } |
| } |
| { multireg: { |
| name: "COM_PRE_DET_CTL", |
| desc: '''To define the duration that the combo pre-condition should be pressed |
| 0-60s, each step is 5us(200KHz clock) |
| ''', |
| count: "NumCombo", |
| cname: "sysrst_ctrl", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "REGWEN", |
| resval: "0", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "DetTimerWidth-1:0", |
| name: "precondition_timer", |
| desc: "0-60s, each step is 5us(200KHz clock)", |
| } |
| ], |
| } |
| } |
| { multireg: { |
| name: "COM_SEL_CTL", |
| desc: ''' |
| To define the keys that trigger the combo |
| [0]: key0_in_sel |
| [1]: key1_in_sel |
| [2]: key2_in_sel |
| [3]: pwrb_in_sel |
| [4]: ac_present_sel |
| HW will detect H2L transition in the combo use case. |
| |
| Optionally, a pre-condition can be configured for the combo detection via !!COM_PRE_SEL_CTL. |
| |
| If no keys are configured for the combo, the combo detection is disabled. |
| |
| The debounce timing is defined via !!KEY_INTR_DEBOUNCE_CTL whereas the key-pressed timing is defined via !!COM_DET_CTL. |
| ''', |
| count: "NumCombo", |
| cname: "sysrst_ctrl", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "REGWEN", |
| resval: "0", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "0", |
| name: "key0_in_sel", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "1", |
| name: "key1_in_sel", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "2", |
| name: "key2_in_sel", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "3", |
| name: "pwrb_in_sel", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "4", |
| name: "ac_present_sel", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| ], |
| } |
| } |
| { multireg: { |
| name: "COM_DET_CTL", |
| desc: '''To define the duration that the combo should be pressed |
| 0-60s, each step is 5us(200KHz clock) |
| ''', |
| count: "NumCombo", |
| cname: "sysrst_ctrl", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "REGWEN", |
| resval: "0", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "DetTimerWidth-1:0", |
| name: "detection_timer", |
| desc: "0-60s, each step is 5us(200KHz clock)", |
| } |
| ], |
| } |
| } |
| { multireg: { |
| name: "COM_OUT_CTL", |
| desc: ''' |
| To define the actions once the combo is detected |
| [0]: bat_disable |
| [1]: interrupt (to OpenTitan processor) |
| [2]: ec_rst (for Embedded Controller) |
| [3]: rst_req (to OpenTitan reset manager) |
| ''', |
| count: "NumCombo", |
| cname: "sysrst_ctrl", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "REGWEN", |
| resval: "0", |
| async: "clk_aon_i", |
| fields: [ |
| { bits: "0", |
| name: "bat_disable", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "1", |
| name: "interrupt", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "2", |
| name: "ec_rst", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| { bits: "3", |
| name: "rst_req", |
| desc: "0: disable, 1: enable", |
| resval: "0", |
| } |
| ], |
| } |
| } |
| { name: "COMBO_INTR_STATUS", |
| desc: ''' |
| Combo interrupt source. These registers will only be set if the |
| interrupt action is configured in the corresponding !!COM_OUT_CTL register. |
| ''', |
| swaccess: "rw1c", |
| hwaccess: "hwo", |
| resval: "0", |
| async: "clk_aon_i", |
| tags: [ // the value of these regs is determined by the |
| // value on the pins, hence it cannot be predicted. |
| "excl:CsrNonInitTests:CsrExclCheck"], |
| fields: [ |
| { bits: "0", |
| name: "combo0_H2L", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "1", |
| name: "combo1_H2L", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "2", |
| name: "combo2_H2L", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "3", |
| name: "combo3_H2L", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| ] |
| } |
| { name: "KEY_INTR_STATUS", |
| desc: "key interrupt source", |
| swaccess: "rw1c", |
| hwaccess: "hwo", |
| resval: "0", |
| async: "clk_aon_i", |
| tags: [ // the value of these regs is determined by the value on the pins |
| // or other CSRs, hence it cannot be predicted. |
| "excl:CsrNonInitTests:CsrExclCheck"], |
| fields: [ |
| { bits: "0", |
| name: "pwrb_H2L", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "1", |
| name: "key0_in_H2L", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "2", |
| name: "key1_in_H2L", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "3", |
| name: "key2_in_H2L", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "4", |
| name: "ac_present_H2L", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "5", |
| name: "ec_rst_l_H2L", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "6", |
| name: "flash_wp_l_H2L", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "7", |
| name: "pwrb_L2H", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "8", |
| name: "key0_in_L2H", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "9", |
| name: "key1_in_L2H", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "10", |
| name: "key2_in_L2H", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "11", |
| name: "ac_present_L2H", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "12", |
| name: "ec_rst_l_L2H", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| { bits: "13", |
| name: "flash_wp_l_L2H", |
| desc: "0: case not detected;1: case detected", |
| resval: "0", |
| } |
| ] |
| } |
| ], |
| } |
