| commit | f75bdf7019c26d5192d2f155d6cde514e5c2423d | [log] [tgz] |
|---|---|---|
| author | Srikrishna Iyer <sriyer@google.com> | Tue Dec 01 14:28:33 2020 -0800 |
| committer | Srikrishna Iyer <46467186+sriyerg@users.noreply.github.com> | Fri Dec 04 11:31:06 2020 -0800 |
| tree | 8cfb39253082b6e266bc40c8f9f0c924085f2fa5 | |
| parent | 3cca442c199943a688dcdf5296031dff8280bf1f [diff] |
[DV common] Fixes in sim.mk for Verilator This commit fixes two of the pre-build steps - copying tool sources and SV filelist generation. Verilator build is invoked from within FuseSoC, so the filelist generation is skipped. Also, Verilator does not have additional tool sources that need to be copied over. This fixes the sim.mk in preparation of adding Verilator support to DVSim. Signed-off-by: Srikrishna Iyer <sriyer@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).