tree 8cfb39253082b6e266bc40c8f9f0c924085f2fa5
parent 3cca442c199943a688dcdf5296031dff8280bf1f
author Srikrishna Iyer <sriyer@google.com> 1606861713 -0800
committer Srikrishna Iyer <46467186+sriyerg@users.noreply.github.com> 1607110266 -0800

[DV common] Fixes in sim.mk for Verilator

This commit fixes two of the pre-build steps - copying tool sources and
SV filelist generation. Verilator build is invoked from within FuseSoC,
so the filelist generation is skipped. Also, Verilator does not have
additional tool sources that need to be copied over. This fixes the
sim.mk in preparation of adding Verilator support to DVSim.

Signed-off-by: Srikrishna Iyer <sriyer@google.com>