[hw/test] Disable dif_csrng_smoketest.
The smoketest fails to match the expected output for the generate
command even though the internal state `{K,V}` matches.
Signed-off-by: Miguel Osorio <miguelosorio@google.com>
diff --git a/hw/top_earlgrey/data/chip_testplan.hjson b/hw/top_earlgrey/data/chip_testplan.hjson
index a87dd11..fb2e729 100644
--- a/hw/top_earlgrey/data/chip_testplan.hjson
+++ b/hw/top_earlgrey/data/chip_testplan.hjson
@@ -1956,7 +1956,8 @@
tests: ["chip_dif_aes_smoketest",
"chip_dif_aon_timer_smoketest",
"chip_dif_clkmgr_smoketest",
- "chip_dif_csrng_smoketest",
+ // TODO(lowrisc/opentitan#7505): Debug CSRNG generate bits mismatch.
+ // "chip_dif_csrng_smoketest",
"chip_dif_entropy_smoketest",
"chip_dif_gpio_smoketest",
"chip_dif_hmac_smoketest",
diff --git a/hw/top_earlgrey/dv/chip_dif_tests.hjson b/hw/top_earlgrey/dv/chip_dif_tests.hjson
index 313fa69..bbb8833 100644
--- a/hw/top_earlgrey/dv/chip_dif_tests.hjson
+++ b/hw/top_earlgrey/dv/chip_dif_tests.hjson
@@ -25,12 +25,13 @@
sw_images: ["sw/device/tests/dif_clkmgr_smoketest:1"]
en_run_modes: ["sw_test_mode"]
}
- {
- name: chip_dif_csrng_smoketest
- uvm_test_seq: chip_sw_base_vseq
- sw_images: ["sw/device/tests/dif_csrng_smoketest:1"]
- en_run_modes: ["sw_test_mode"]
- }
+ // TODO(lowrisc/opentitan#7505): Debug CSRNG generate bits mismatch.
+ // {
+ // name: chip_dif_csrng_smoketest
+ // uvm_test_seq: chip_sw_base_vseq
+ // sw_images: ["sw/device/tests/dif_csrng_smoketest:1"]
+ // en_run_modes: ["sw_test_mode"]
+ // }
{
name: chip_dif_entropy_smoketest
uvm_test_seq: chip_sw_base_vseq
@@ -117,7 +118,8 @@
tests: ["chip_dif_aes_smoketest",
"chip_dif_aon_timer_smoketest",
"chip_dif_clkmgr_smoketest",
- "chip_dif_csrng_smoketest",
+ // TODO(lowrisc/opentitan#7505): Debug CSRNG generate bits mismatch.
+ // "chip_dif_csrng_smoketest",
"chip_dif_entropy_smoketest",
"chip_dif_gpio_smoketest",
"chip_dif_hmac_smoketest",
diff --git a/hw/top_earlgrey/dv/verilator_sim_cfg.hjson b/hw/top_earlgrey/dv/verilator_sim_cfg.hjson
index 5c3d490..e43ea52 100644
--- a/hw/top_earlgrey/dv/verilator_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/verilator_sim_cfg.hjson
@@ -109,10 +109,11 @@
name: dif_clkmgr_smoketest
sw_images: ["sw/device/tests/dif_clkmgr_smoketest:1"]
}
- {
- name: dif_csrng_smoketest
- sw_images: ["sw/device/tests/dif_csrng_smoketest:1"]
- }
+ // TODO(lowrisc/opentitan#7505): Debug CSRNG generate bits mismatch.
+ // {
+ // name: dif_csrng_smoketest
+ // sw_images: ["sw/device/tests/dif_csrng_smoketest:1"]
+ // }
{
name: dif_entropy_smoketest
sw_images: ["sw/device/tests/dif_entropy_smoketest:1"]
diff --git a/sw/device/lib/dif/dif_csrng_unittest.cc b/sw/device/lib/dif/dif_csrng_unittest.cc
index 10d76b9..e1259d8 100644
--- a/sw/device/lib/dif/dif_csrng_unittest.cc
+++ b/sw/device/lib/dif/dif_csrng_unittest.cc
@@ -16,6 +16,8 @@
namespace dif_entropy_unittest {
namespace {
+using ::testing::ElementsAreArray;
+
class DifCsrngTest : public testing::Test, public mock_mmio::MmioTest {
protected:
const dif_csrng_params_t params_ = {.base_addr = dev().region()};
@@ -271,6 +273,12 @@
dif_csrng_internal_state_t got;
EXPECT_EQ(dif_csrng_get_internal_state(&csrng_, instance_id, &got),
kDifCsrngOk);
+
+ EXPECT_EQ(got.reseed_counter, expected.reseed_counter);
+ EXPECT_THAT(got.key, ElementsAreArray(expected.key));
+ EXPECT_THAT(got.v, ElementsAreArray(expected.v));
+ EXPECT_EQ(got.instantiated, expected.instantiated);
+ EXPECT_EQ(got.fips_compliance, expected.fips_compliance);
}
TEST_F(GetInternalStateTest, GetInternalStateBadArgs) {
diff --git a/test/systemtest/config.py b/test/systemtest/config.py
index cf06729..d2ac461 100644
--- a/test/systemtest/config.py
+++ b/test/systemtest/config.py
@@ -85,10 +85,11 @@
"name": "dif_clkmgr_smoketest",
"targets": ["sim_verilator", "fpga_cw310", "fpga_nexysvideo"],
},
- {
- "name": "dif_csrng_smoketest",
- "targets": ["sim_verilator", "fpga_cw310"],
- },
+ # TODO(lowrisc/opentitan#7505): Debug CSRNG generate bits mismatch.
+ # {
+ # "name": "dif_csrng_smoketest",
+ # "targets": ["sim_verilator", "fpga_cw310"],
+ # },
{
"name": "dif_entropy_smoketest",
"targets": ["sim_verilator", "fpga_cw310"],
