blob: e48462b12c57dbc0d2ae5c6cb9582aee204220bc [file] [log] [blame]
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
// Name of the sim cfg - typically same as the name of the DUT.
name: aon_timer
// Top level dut name (sv module).
dut: aon_timer
// Top level testbench name (sv module).
tb: tb
// Simulator used to sign off this block
tool: vcs
// Fusesoc core file used for building the file list.
fusesoc_core: lowrisc:dv:aon_timer_sim:0.1
// Testplan hjson file.
testplan: "{proj_root}/hw/ip/aon_timer/data/aon_timer_testplan.hjson"
// RAL spec - used to generate the RAL model.
ral_spec: "{proj_root}/hw/ip/aon_timer/data/aon_timer.hjson"
// Import additional common sim cfg files.
// TODO: remove imported cfgs that do not apply.
import_cfgs: [// Project wide common sim cfg file
"{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
// Common CIP test lists
"{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]
// Add additional tops for simulation.
sim_tops: ["aon_timer_bind", "sec_cm_prim_onehot_check_bind"]
// Default iterations for all tests - each test entry can override this.
reseed: 50
// Default UVM test and seq class name.
uvm_test: aon_timer_base_test
uvm_test_seq: aon_timer_base_vseq
// List of test specifications.
tests: [
{
name: aon_timer_smoke
uvm_test_seq: aon_timer_smoke_vseq
}
{
name: aon_timer_prescaler
uvm_test_seq: aon_timer_prescaler_vseq
}
{
name: aon_timer_jump
uvm_test_seq: aon_timer_jump_vseq
}
// TODO: add more tests here
]
// List of regressions.
regressions: [
{
name: smoke
tests: ["aon_timer_smoke"]
}
]
}