| commit | efb811bdb2bca2e2e6113f84cb9ca0bd0b4fd8f3 | [log] [tgz] |
|---|---|---|
| author | Udi Jonnalagadda <udij@google.com> | Tue May 11 15:22:11 2021 -0700 |
| committer | udinator <udij@google.com> | Tue May 11 23:54:13 2021 -0700 |
| tree | ebf37708bb0ba63954608f4d83e08205498f2b67 | |
| parent | c48b9195507755e58235583f6ceed8261a792954 [diff] |
[dv/sram] fix initialization checks currently to trigger memory initialization the base sequence calls `csr_wr` to fetch a new key, then calls `csr_update` to write the next control bit, however due to the behavior of `csr_update`, a new key request is also triggered at the same time. This sometimes messes up the scoreboard timing model, but is also entirely unnecessary, so this PR removes it and replaces with a single call to `csr_wr` to write both bits at once to simplify things. Signed-off-by: Udi Jonnalagadda <udij@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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