)]}'
{
  "commit": "efb811bdb2bca2e2e6113f84cb9ca0bd0b4fd8f3",
  "tree": "ebf37708bb0ba63954608f4d83e08205498f2b67",
  "parents": [
    "c48b9195507755e58235583f6ceed8261a792954"
  ],
  "author": {
    "name": "Udi Jonnalagadda",
    "email": "udij@google.com",
    "time": "Tue May 11 15:22:11 2021 -0700"
  },
  "committer": {
    "name": "udinator",
    "email": "udij@google.com",
    "time": "Tue May 11 23:54:13 2021 -0700"
  },
  "message": "[dv/sram] fix initialization checks\n\ncurrently to trigger memory initialization the base sequence calls\n`csr_wr` to fetch a new key, then calls `csr_update` to write the next\ncontrol bit, however due to the behavior of `csr_update`, a new key\nrequest is also triggered at the same time.\n\nThis sometimes messes up the scoreboard timing model, but is also\nentirely unnecessary, so this PR removes it and replaces with a single\ncall to `csr_wr` to write both bits at once to simplify things.\n\nSigned-off-by: Udi Jonnalagadda \u003cudij@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4eb4dbb450a810228329d02cd73c5709e63d70bb",
      "old_mode": 33188,
      "old_path": "hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_base_vseq.sv",
      "new_id": "d628532736c83248833dd76181be81f447085ba2",
      "new_mode": 33188,
      "new_path": "hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_base_vseq.sv"
    }
  ]
}