hw/ip/i2c/dv/i2c_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: i2c

  // Top level dut name (sv module).
  dut: i2c

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: xcelium

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:i2c_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/i2c/data/i2c_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/i2c/data/i2c.hjson"

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/data/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/data/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/data/tests/intr_test.hjson",
                //"{proj_root}/hw/dv/data/tests/stress_tests.hjson",
                "{proj_root}/hw/dv/data/tests/tl_access_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: ["-top i2c_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Default UVM test and seq class name.
  uvm_test: i2c_base_test
  uvm_test_seq: i2c_base_vseq

  // List of test specifications.
  tests: [
    {
      name: i2c_sanity
      uvm_test_seq: i2c_sanity_vseq
    }
  ]

  // List of regressions.
  //regressions: [
  //  {
  //     name: sanity
  //     tests: ["i2c_sanity"]
  //  }
  //]
}