hw/ip/trial1/rtl/trial1_reg_pkg.sv

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Package auto-generated by `reggen` containing data structure

package trial1_reg_pkg;

// Register to internal design logic
typedef struct packed {

  struct packed {
    logic [31:0] q; // [556:525]
  } rwtype0;
  struct packed {
    struct packed {
      logic q; // [524]
    } field0;
    struct packed {
      logic q; // [523]
    } field1;
    struct packed {
      logic q; // [522]
    } field4;
    struct packed {
      logic [7:0] q; // [521:514]
    } field15_8;
  } rwtype1;
  struct packed {
    logic [31:0] q; // [513:482]
  } rwtype2;
  struct packed {
    struct packed {
      logic [15:0] q; // [481:466]
    } field0;
    struct packed {
      logic [15:0] q; // [465:450]
    } field1;
  } rwtype3;
  struct packed {
    struct packed {
      logic [15:0] q; // [449:434]
    } field0;
    struct packed {
      logic [15:0] q; // [433:418]
    } field1;
  } rwtype4;
  struct packed {
    logic [31:0] q; // [417:386]
  } rotype0;
  struct packed {
    logic [31:0] q; // [385:354]
  } w1ctype0;
  struct packed {
    struct packed {
      logic [15:0] q; // [353:338]
    } field0;
    struct packed {
      logic [15:0] q; // [337:322]
    } field1;
  } w1ctype1;
  struct packed {
    logic [31:0] q; // [321:290]
  } w1ctype2;
  struct packed {
    logic [31:0] q; // [289:258]
  } w1stype2;
  struct packed {
    logic [31:0] q; // [257:226]
  } w0ctype2;
  struct packed {
    logic [31:0] q; // [225:194]
  } r0w1ctype2;
  struct packed {
    logic [31:0] q; // [193:162]
  } rctype0;
  struct packed {
    logic [31:0] q; // [161:130]
  } wotype0;
  struct packed {
    struct packed {
      logic [3:0] q; // [129:126]
    } field0;
    struct packed {
      logic [3:0] q; // [125:122]
    } field1;
    struct packed {
      logic [3:0] q; // [121:118]
    } field2;
    struct packed {
      logic [3:0] q; // [117:114]
    } field3;
    struct packed {
      logic [3:0] q; // [113:110]
    } field4;
    struct packed {
      logic [3:0] q; // [109:106]
    } field5;
    struct packed {
      logic [3:0] q; // [105:102]
    } field6;
    struct packed {
      logic [3:0] q; // [101:98]
    } field7;
  } mixtype0;
  struct packed {
    logic [31:0] q; // [97:66]
    logic qe; // [65]
  } rwtype5;
  struct packed {
    logic [31:0] q; // [64:33]
    logic qe; // [32]
  } rwtype6;
  struct packed {
    logic [31:0] q; // [31:0]
  } rotype1;
} trial1_reg2hw_t;

// Internal design logic to register
typedef struct packed {

  struct packed {
    logic [31:0] d; // [386:355]
    logic de; // [354]
  } rwtype2;
  struct packed {
    struct packed {
      logic [15:0] d; // [353:338]
      logic de; // [337]
    } field0;
    struct packed {
      logic [15:0] d; // [336:321]
      logic de; // [320]
    } field1;
  } rwtype3;
  struct packed {
    logic [31:0] d; // [319:288]
    logic de; // [287]
  } rotype0;
  struct packed {
    logic [31:0] d; // [286:255]
    logic de; // [254]
  } w1ctype2;
  struct packed {
    logic [31:0] d; // [253:222]
    logic de; // [221]
  } w1stype2;
  struct packed {
    logic [31:0] d; // [220:189]
    logic de; // [188]
  } w0ctype2;
  struct packed {
    logic [31:0] d; // [187:156]
    logic de; // [155]
  } r0w1ctype2;
  struct packed {
    logic [31:0] d; // [154:123]
    logic de; // [122]
  } rctype0;
  struct packed {
    struct packed {
      logic [3:0] d; // [121:118]
      logic de; // [117]
    } field1;
    struct packed {
      logic [3:0] d; // [116:113]
      logic de; // [112]
    } field3;
    struct packed {
      logic [3:0] d; // [111:108]
      logic de; // [107]
    } field4;
    struct packed {
      logic [3:0] d; // [106:103]
      logic de; // [102]
    } field5;
    struct packed {
      logic [3:0] d; // [101:98]
      logic de; // [97]
    } field6;
  } mixtype0;
  struct packed {
    logic [31:0] d; // [96:65]
    logic de; // [64]
  } rwtype5;
  struct packed {
    logic [31:0] d; // [63:32]
  } rwtype6;
  struct packed {
    logic [31:0] d; // [31:0]
  } rotype1;
} trial1_hw2reg_t;

// Register Address
  parameter TRIAL1_RWTYPE0_OFFSET = 10'h 0;
  parameter TRIAL1_RWTYPE1_OFFSET = 10'h 4;
  parameter TRIAL1_RWTYPE2_OFFSET = 10'h 8;
  parameter TRIAL1_RWTYPE3_OFFSET = 10'h c;
  parameter TRIAL1_RWTYPE4_OFFSET = 10'h 200;
  parameter TRIAL1_ROTYPE0_OFFSET = 10'h 204;
  parameter TRIAL1_W1CTYPE0_OFFSET = 10'h 208;
  parameter TRIAL1_W1CTYPE1_OFFSET = 10'h 20c;
  parameter TRIAL1_W1CTYPE2_OFFSET = 10'h 210;
  parameter TRIAL1_W1STYPE2_OFFSET = 10'h 214;
  parameter TRIAL1_W0CTYPE2_OFFSET = 10'h 218;
  parameter TRIAL1_R0W1CTYPE2_OFFSET = 10'h 21c;
  parameter TRIAL1_RCTYPE0_OFFSET = 10'h 220;
  parameter TRIAL1_WOTYPE0_OFFSET = 10'h 224;
  parameter TRIAL1_MIXTYPE0_OFFSET = 10'h 228;
  parameter TRIAL1_RWTYPE5_OFFSET = 10'h 22c;
  parameter TRIAL1_RWTYPE6_OFFSET = 10'h 230;
  parameter TRIAL1_ROTYPE1_OFFSET = 10'h 234;
  parameter TRIAL1_ROTYPE2_OFFSET = 10'h 238;
  parameter TRIAL1_RWTYPE7_OFFSET = 10'h 23c;

endpackage