| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| * Control / status register primitive |
| `include "prim_assert.sv" |
| parameter int unsigned Width = 32, |
| parameter bit ShadowCopy = 1'b0, |
| parameter bit [Width-1:0] ResetValue = '0 |
| input logic [Width-1:0] wr_data_i, |
| output logic [Width-1:0] rd_data_o, |
| logic [Width-1:0] rdata_q; |
| always_ff @(posedge clk_i or negedge rst_ni) begin |
| end else if (wr_en_i) begin |
| assign rd_data_o = rdata_q; |
| if (ShadowCopy) begin : gen_shadow |
| logic [Width-1:0] shadow_q; |
| always_ff @(posedge clk_i or negedge rst_ni) begin |
| end else if (wr_en_i) begin |
| assign rd_error_o = rdata_q != ~shadow_q; |
| end else begin : gen_no_shadow |
| assign rd_error_o = 1'b0; |
| `ASSERT_KNOWN(IbexCSREnValid, wr_en_i) |