[ast] Temporary hacks to integrate with clkmgr changes

Signed-off-by: Timothy Chen <timothytim@google.com>

hw/top_earlgrey/ip/ast/rtl/ast.sv

diff --git a/hw/top_earlgrey/ip/ast/rtl/ast.sv b/hw/top_earlgrey/ip/ast/rtl/ast.sv
index 19cd2f3..9019730 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast.sv
@@ -71,7 +71,7 @@
 
   // system source clock
   input clk_src_sys_en_i,                     // SYS Source Clock Enable
-  input clk_src_sys_jen_i,                    // SYS Source Clock Jitter Enable
+  input prim_mubi_pkg::mubi4_t clk_src_sys_jen_i, // SYS Source Clock Jitter Enable
   output logic clk_src_sys_o,                 // SYS Source Clock
   output logic clk_src_sys_val_o,             // SYS Source Clock Valid
 
@@ -139,7 +139,7 @@
 `endif
 
   // flash and external clocks
-  input ext_freq_is_96m_i,                          // External clock frequecy is 96MHz
+  input prim_mubi_pkg::mubi4_t ext_freq_is_96m_i,   // External clock frequecy is 96MHz
   input prim_mubi_pkg::mubi4_t all_clk_byp_req_i,   // All clocks bypass request
   output prim_mubi_pkg::mubi4_t all_clk_byp_ack_o,  // Switch all clocks to External clocks
   input prim_mubi_pkg::mubi4_t io_clk_byp_req_i,    // IO clock bypass request (for OTP bootstrap)
@@ -168,6 +168,9 @@
 logic vcaon_pok, vcaon_pok_h, vcmain_pok;
 logic vcaon_pok_por, vcmain_pok_por;
 
+
+prim_mubi_pkg::mubi4_t jen;
+
 // Local (AST) System clock buffer
 ////////////////////////////////////////
 logic clk_sys_scn, clk_sys;
@@ -368,7 +371,7 @@
 `endif
 
 sys_clk u_sys_clk (
-  .clk_src_sys_jen_i ( clk_src_sys_jen_i ),
+  .clk_src_sys_jen_i ( prim_mubi_pkg::mubi4_test_true_strict(jen) ),
   .clk_src_sys_en_i ( clk_src_sys_en_i ),
   .clk_sys_pd_ni ( clk_sys_pd_n ),
   .rst_sys_clk_ni ( rst_sys_clk_n ),
@@ -592,6 +595,19 @@
 logic [EntropyRateWidth-1:0] entropy_rate_o;
 logic vcmain_pok_por_sys, rst_src_sys_n;
 
+prim_mubi4_sync #(
+  .NumCopies(1),
+  .AsyncOn(1),
+  .StabilityCheck(1),
+  .ResetValue(prim_mubi_pkg::MuBi4False)
+) u_jitter_en_sync (
+  // not sure if the right clock / reset is used
+  .clk_i(clk_sys),
+  .rst_ni(rst_src_sys_n),
+  .mubi_i(clk_src_sys_jen_i),
+  .mubi_o(jen)
+);
+
 // Reset De-Assert Sync
 prim_flop_2sync #(
   .Width ( 1 ),
@@ -617,7 +633,7 @@
   .clk_src_sys_i ( clk_sys ),
   .rst_src_sys_ni ( rst_src_sys_n ),
   .clk_src_sys_val_i ( clk_src_sys_val_o ),
-  .clk_src_sys_jen_i ( clk_src_sys_jen_i ),
+  .clk_src_sys_jen_i ( prim_mubi_pkg::mubi4_test_true_strict(jen) ),
   .entropy_req_o ( entropy_req_o )
 );  // of u_entropy
 

hw/top_earlgrey/ip/ast/rtl/ast_clks_byp.sv

diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_clks_byp.sv b/hw/top_earlgrey/ip/ast/rtl/ast_clks_byp.sv
index c9e7f23..cf81ca7 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast_clks_byp.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_clks_byp.sv
@@ -25,7 +25,7 @@
   input clk_ast_ext_i,                      // External Clock
   input prim_mubi_pkg::mubi4_t io_clk_byp_req_i,  // External IO clock mux for OTP bootstrap
   input prim_mubi_pkg::mubi4_t all_clk_byp_req_i, // External all clock mux override
-  input ext_freq_is_96m_i,                  // External Clock Frequecy is 96MHz (else 48MHz)
+  input prim_mubi_pkg::mubi4_t ext_freq_is_96m_i, // External Clock Frequecy is 96MHz (else 48MHz)
   output prim_mubi_pkg::mubi4_t io_clk_byp_ack_o,   // Switch IO clock to External clock
   output prim_mubi_pkg::mubi4_t all_clk_byp_ack_o,  // Switch all clocks to External clock
   output logic clk_src_sys_o,               // SYS Source Clock
@@ -202,7 +202,7 @@
 
 // Sync to local AON clcok
 prim_mubi_pkg::mubi4_t io_clk_byp_req, all_clk_byp_req;
-logic sw_ext_freq_is_96m;
+prim_mubi_pkg::mubi4_t sw_ext_freq_is_96m;
 
 prim_mubi4_sync #(
   .StabilityCheck ( 1 ),
@@ -224,14 +224,14 @@
   .mubi_o ( all_clk_byp_req )
 );
 
-prim_flop_2sync #(
-  .Width ( 1 ),
-  .ResetValue ( 1'b0 )
+prim_mubi4_sync #(
+  .StabilityCheck ( 1 ),
+  .ResetValue ( prim_mubi_pkg::MuBi4False )
 ) u_sw_ext_freq_sync (
   .clk_i ( clk_ext ),
   .rst_ni ( rst_aon_n ),
-  .d_i ( ext_freq_is_96m_i ),
-  .q_o ( sw_ext_freq_is_96m )
+  .mubi_i ( ext_freq_is_96m_i ),
+  .mubi_o ( sw_ext_freq_is_96m )
 );
 
 // Decode logic
@@ -268,7 +268,7 @@
 assign io_clk_byp_sel  = sw_io_clk_byp || sw_all_clk_byp;
 assign usb_clk_byp_sel = sw_usb_clk_byp;
 assign aon_clk_byp_sel = sw_aon_clk_byp;
-assign ext_freq_is_96m = sw_ext_freq_is_96m;
+assign ext_freq_is_96m = prim_mubi_pkg::mubi4_test_true_strict(sw_ext_freq_is_96m);
 
 
 ////////////////////////////////////////