[doc] Review rv_plic for markdown_style consistency.

- very minor changes

hw/ip/rv_plic/doc/index.md

diff --git a/hw/ip/rv_plic/doc/index.md b/hw/ip/rv_plic/doc/index.md
index 4e0e6fa..9c7d5a0 100644
--- a/hw/ip/rv_plic/doc/index.md
+++ b/hw/ip/rv_plic/doc/index.md
@@ -6,7 +6,7 @@
 
 This document specifies the Interrupt Controller (RV_PLIC) functionality. This
 module conforms to the
-[Comportable guideline for peripheral functionality.]({{< relref "doc/rm/comportability_specification" >}})
+[Comportable guideline for peripheral functionality]({{< relref "doc/rm/comportability_specification" >}}).
 See that document for integration overview within the broader top level system.
 
 
@@ -33,7 +33,11 @@
 
 ![RV_PLIC Block Diagram](block_diagram.svg)
 
-## Details
+## Hardware Interfaces
+
+{{< hwcfg "hw/ip/rv_plic/data/rv_plic.hjson" >}}
+
+## Design Details
 
 ### Identifier
 
@@ -55,7 +59,7 @@
 priority value.
 
 `MAX_PRIO` parameter is most area contributing option in RV_PLIC. If `MAX_PRIO`
-is big, then finding the highest priority in Process module consumes a lot of
+is big, then finding the highest priority in Process module may consume a lot of
 logic gates.
 
 ### Interrupt Gateways
@@ -67,11 +71,11 @@
 
 When the gateway detects an interrupt event it raises the interrupt pending bit
 ({{< regref "IP" >}}) for that interrupt source. When an interrupt is claimed by a target the
-relevant bit of {{< regref "IP" >}} is cleared. A bit in {{< regref "IP" >}} will be not reasserted until the
+relevant bit of {{< regref "IP" >}} is cleared. A bit in {{< regref "IP" >}} will not be reasserted until the
 target signals completion of the interrupt. Any new interrupt event between a
 bit in {{< regref "IP" >}} asserting and completing that interrupt is ignored. In particular
 this means that for edge triggered interrupts if a new edge is seen after the
-source's {{< regref "IP" >}} bit is asserted and before completion that edge will be ignored
+source's {{< regref "IP" >}} bit is asserted but before completion, that edge will be ignored
 (counting missed edges as discussed in the RISC-V PLIC specification is not
 supported).
 
@@ -140,9 +144,6 @@
 asserted. At g the interrupt is completed (by writing `i+1` to it's
 Claim/Complete register) so at h `irq_o` is asserted due to the new interrupt.
 
-## Hardware Interfaces
-
-{{< hwcfg "hw/ip/rv_plic/data/rv_plic.hjson" >}}
 
 # Programmers Guide
 
@@ -231,9 +232,9 @@
 file. As of Jan. 2019, `regtool.py` supports only one nested multiple register
 format `multireg`.
 
-The below register description doesn't match with Top Earlgrey RV_PLIC design. The
-RV_PLIC in the top_earlgrey is generated by topgen tool so that the number of
-interrupt sources is different.
+The below register description may not match with top level design. The
+RV_PLIC in the top level is generated by topgen tool so that the number of
+interrupt sources may be different.
 
 -   LE: CEILING(N_SOURCE / DW)
     Value 1 indicates the interrupt source's behavior is edge-triggered It is
@@ -252,4 +253,3 @@
     Claim by read, complete by write
 
 {{< registers "hw/ip/rv_plic/data/rv_plic.hjson" >}}
-