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opensecura / 3p / lowrisc / opentitan / e0efec7382823e0e8b27e94ec8cf9e5d726d514d / . / hw / ip / kmac / rtl / kmac_reg_top.sv
blob: c92bba61d3529a6e40bc132765a5c906135cfeb0 [file] [log] [blame]
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `reggen`
`include "prim_assert.sv"
module kmac_reg_top (
input clk_i,
input rst_ni,
input rst_shadowed_ni,
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
// Output port for window
output tlul_pkg::tl_h2d_t tl_win_o [2],
input tlul_pkg::tl_d2h_t tl_win_i [2],
// To HW
output kmac_reg_pkg::kmac_reg2hw_t reg2hw, // Write
input kmac_reg_pkg::kmac_hw2reg_t hw2reg, // Read
output logic shadowed_storage_err_o,
output logic shadowed_update_err_o,
// Integrity check errors
output logic intg_err_o,
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
import kmac_reg_pkg::* ;
localparam int AW = 12;
localparam int DW = 32;
localparam int DBW = DW/8; // Byte Width
// register signals
logic reg_we;
logic reg_re;
logic [AW-1:0] reg_addr;
logic [DW-1:0] reg_wdata;
logic [DBW-1:0] reg_be;
logic [DW-1:0] reg_rdata;
logic reg_error;
logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
logic reg_busy;
tlul_pkg::tl_h2d_t tl_reg_h2d;
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
logic intg_err;
tlul_cmd_intg_chk u_chk (
.tl_i(tl_i),
.err_o(intg_err)
);
// also check for spurious write enables
logic reg_we_err;
logic [60:0] reg_we_check;
prim_reg_we_check #(
.OneHotWidth(61)
) u_prim_reg_we_check (
.clk_i(clk_i),
.rst_ni(rst_ni),
.oh_i (reg_we_check),
.en_i (reg_we && !addrmiss),
.err_o (reg_we_err)
);
logic err_q;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
err_q <= '0;
end else if (intg_err || reg_we_err) begin
err_q <= 1'b1;
end
end
// integrity error output is permanent and should be used for alert generation
// register errors are transactional
assign intg_err_o = err_q | intg_err | reg_we_err;
// outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
tlul_rsp_intg_gen #(
.EnableRspIntgGen(1),
.EnableDataIntgGen(1)
) u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o(tl_o)
);
tlul_pkg::tl_h2d_t tl_socket_h2d [3];
tlul_pkg::tl_d2h_t tl_socket_d2h [3];
logic [1:0] reg_steer;
// socket_1n connection
assign tl_reg_h2d = tl_socket_h2d[2];
assign tl_socket_d2h[2] = tl_reg_d2h;
assign tl_win_o[0] = tl_socket_h2d[0];
assign tl_socket_d2h[0] = tl_win_i[0];
assign tl_win_o[1] = tl_socket_h2d[1];
assign tl_socket_d2h[1] = tl_win_i[1];
// Create Socket_1n
tlul_socket_1n #(
.N (3),
.HReqPass (1'b1),
.HRspPass (1'b1),
.DReqPass ({3{1'b1}}),
.DRspPass ({3{1'b1}}),
.HReqDepth (4'h0),
.HRspDepth (4'h0),
.DReqDepth ({3{4'h0}}),
.DRspDepth ({3{4'h0}}),
.ExplicitErrs (1'b0)
) u_socket (
.clk_i (clk_i),
.rst_ni (rst_ni),
.tl_h_i (tl_i),
.tl_h_o (tl_o_pre),
.tl_d_o (tl_socket_h2d),
.tl_d_i (tl_socket_d2h),
.dev_select_i (reg_steer)
);
// Create steering logic
always_comb begin
reg_steer =
tl_i.a_address[AW-1:0] inside {[1024:1535]} ? 2'd0 :
tl_i.a_address[AW-1:0] inside {[2048:4095]} ? 2'd1 :
// Default set to register
2'd2;
// Override this in case of an integrity error
if (intg_err) begin
reg_steer = 2'd2;
end
end
tlul_adapter_reg #(
.RegAw(AW),
.RegDw(DW),
.EnableDataIntgGen(0)
) u_reg_if (
.clk_i (clk_i),
.rst_ni (rst_ni),
.tl_i (tl_reg_h2d),
.tl_o (tl_reg_d2h),
.en_ifetch_i(prim_mubi_pkg::MuBi4False),
.intg_error_o(),
.we_o (reg_we),
.re_o (reg_re),
.addr_o (reg_addr),
.wdata_o (reg_wdata),
.be_o (reg_be),
.busy_i (reg_busy),
.rdata_i (reg_rdata),
.error_i (reg_error)
);
// cdc oversampling signals
assign reg_rdata = reg_rdata_next ;
assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
logic intr_state_we;
logic intr_state_kmac_done_qs;
logic intr_state_kmac_done_wd;
logic intr_state_fifo_empty_qs;
logic intr_state_fifo_empty_wd;
logic intr_state_kmac_err_qs;
logic intr_state_kmac_err_wd;
logic intr_enable_we;
logic intr_enable_kmac_done_qs;
logic intr_enable_kmac_done_wd;
logic intr_enable_fifo_empty_qs;
logic intr_enable_fifo_empty_wd;
logic intr_enable_kmac_err_qs;
logic intr_enable_kmac_err_wd;
logic intr_test_we;
logic intr_test_kmac_done_wd;
logic intr_test_fifo_empty_wd;
logic intr_test_kmac_err_wd;
logic alert_test_we;
logic alert_test_recov_operation_err_wd;
logic alert_test_fatal_fault_err_wd;
logic cfg_regwen_re;
logic cfg_regwen_qs;
logic cfg_shadowed_re;
logic cfg_shadowed_we;
logic cfg_shadowed_kmac_en_qs;
logic cfg_shadowed_kmac_en_wd;
logic cfg_shadowed_kmac_en_storage_err;
logic cfg_shadowed_kmac_en_update_err;
logic [2:0] cfg_shadowed_kstrength_qs;
logic [2:0] cfg_shadowed_kstrength_wd;
logic cfg_shadowed_kstrength_storage_err;
logic cfg_shadowed_kstrength_update_err;
logic [1:0] cfg_shadowed_mode_qs;
logic [1:0] cfg_shadowed_mode_wd;
logic cfg_shadowed_mode_storage_err;
logic cfg_shadowed_mode_update_err;
logic cfg_shadowed_msg_endianness_qs;
logic cfg_shadowed_msg_endianness_wd;
logic cfg_shadowed_msg_endianness_storage_err;
logic cfg_shadowed_msg_endianness_update_err;
logic cfg_shadowed_state_endianness_qs;
logic cfg_shadowed_state_endianness_wd;
logic cfg_shadowed_state_endianness_storage_err;
logic cfg_shadowed_state_endianness_update_err;
logic cfg_shadowed_sideload_qs;
logic cfg_shadowed_sideload_wd;
logic cfg_shadowed_sideload_storage_err;
logic cfg_shadowed_sideload_update_err;
logic [1:0] cfg_shadowed_entropy_mode_qs;
logic [1:0] cfg_shadowed_entropy_mode_wd;
logic cfg_shadowed_entropy_mode_storage_err;
logic cfg_shadowed_entropy_mode_update_err;
logic cfg_shadowed_entropy_fast_process_qs;
logic cfg_shadowed_entropy_fast_process_wd;
logic cfg_shadowed_entropy_fast_process_storage_err;
logic cfg_shadowed_entropy_fast_process_update_err;
logic cfg_shadowed_msg_mask_qs;
logic cfg_shadowed_msg_mask_wd;
logic cfg_shadowed_msg_mask_storage_err;
logic cfg_shadowed_msg_mask_update_err;
logic cfg_shadowed_entropy_ready_qs;
logic cfg_shadowed_entropy_ready_wd;
logic cfg_shadowed_entropy_ready_storage_err;
logic cfg_shadowed_entropy_ready_update_err;
logic cfg_shadowed_err_processed_qs;
logic cfg_shadowed_err_processed_wd;
logic cfg_shadowed_err_processed_storage_err;
logic cfg_shadowed_err_processed_update_err;
logic cfg_shadowed_en_unsupported_modestrength_qs;
logic cfg_shadowed_en_unsupported_modestrength_wd;
logic cfg_shadowed_en_unsupported_modestrength_storage_err;
logic cfg_shadowed_en_unsupported_modestrength_update_err;
logic cmd_we;
logic [5:0] cmd_cmd_wd;
logic cmd_entropy_req_wd;
logic cmd_hash_cnt_clr_wd;
logic status_re;
logic status_sha3_idle_qs;
logic status_sha3_absorb_qs;
logic status_sha3_squeeze_qs;
logic [4:0] status_fifo_depth_qs;
logic status_fifo_empty_qs;
logic status_fifo_full_qs;
logic status_alert_fatal_fault_qs;
logic status_alert_recov_ctrl_update_err_qs;
logic entropy_period_we;
logic [9:0] entropy_period_prescaler_qs;
logic [9:0] entropy_period_prescaler_wd;
logic [15:0] entropy_period_wait_timer_qs;
logic [15:0] entropy_period_wait_timer_wd;
logic [9:0] entropy_refresh_hash_cnt_qs;
logic entropy_refresh_threshold_shadowed_re;
logic entropy_refresh_threshold_shadowed_we;
logic [9:0] entropy_refresh_threshold_shadowed_qs;
logic [9:0] entropy_refresh_threshold_shadowed_wd;
logic entropy_refresh_threshold_shadowed_storage_err;
logic entropy_refresh_threshold_shadowed_update_err;
logic entropy_seed_0_we;
logic [31:0] entropy_seed_0_wd;
logic entropy_seed_1_we;
logic [31:0] entropy_seed_1_wd;
logic entropy_seed_2_we;
logic [31:0] entropy_seed_2_wd;
logic entropy_seed_3_we;
logic [31:0] entropy_seed_3_wd;
logic entropy_seed_4_we;
logic [31:0] entropy_seed_4_wd;
logic key_share0_0_we;
logic [31:0] key_share0_0_wd;
logic key_share0_1_we;
logic [31:0] key_share0_1_wd;
logic key_share0_2_we;
logic [31:0] key_share0_2_wd;
logic key_share0_3_we;
logic [31:0] key_share0_3_wd;
logic key_share0_4_we;
logic [31:0] key_share0_4_wd;
logic key_share0_5_we;
logic [31:0] key_share0_5_wd;
logic key_share0_6_we;
logic [31:0] key_share0_6_wd;
logic key_share0_7_we;
logic [31:0] key_share0_7_wd;
logic key_share0_8_we;
logic [31:0] key_share0_8_wd;
logic key_share0_9_we;
logic [31:0] key_share0_9_wd;
logic key_share0_10_we;
logic [31:0] key_share0_10_wd;
logic key_share0_11_we;
logic [31:0] key_share0_11_wd;
logic key_share0_12_we;
logic [31:0] key_share0_12_wd;
logic key_share0_13_we;
logic [31:0] key_share0_13_wd;
logic key_share0_14_we;
logic [31:0] key_share0_14_wd;
logic key_share0_15_we;
logic [31:0] key_share0_15_wd;
logic key_share1_0_we;
logic [31:0] key_share1_0_wd;
logic key_share1_1_we;
logic [31:0] key_share1_1_wd;
logic key_share1_2_we;
logic [31:0] key_share1_2_wd;
logic key_share1_3_we;
logic [31:0] key_share1_3_wd;
logic key_share1_4_we;
logic [31:0] key_share1_4_wd;
logic key_share1_5_we;
logic [31:0] key_share1_5_wd;
logic key_share1_6_we;
logic [31:0] key_share1_6_wd;
logic key_share1_7_we;
logic [31:0] key_share1_7_wd;
logic key_share1_8_we;
logic [31:0] key_share1_8_wd;
logic key_share1_9_we;
logic [31:0] key_share1_9_wd;
logic key_share1_10_we;
logic [31:0] key_share1_10_wd;
logic key_share1_11_we;
logic [31:0] key_share1_11_wd;
logic key_share1_12_we;
logic [31:0] key_share1_12_wd;
logic key_share1_13_we;
logic [31:0] key_share1_13_wd;
logic key_share1_14_we;
logic [31:0] key_share1_14_wd;
logic key_share1_15_we;
logic [31:0] key_share1_15_wd;
logic key_len_we;
logic [2:0] key_len_wd;
logic prefix_0_we;
logic [31:0] prefix_0_qs;
logic [31:0] prefix_0_wd;
logic prefix_1_we;
logic [31:0] prefix_1_qs;
logic [31:0] prefix_1_wd;
logic prefix_2_we;
logic [31:0] prefix_2_qs;
logic [31:0] prefix_2_wd;
logic prefix_3_we;
logic [31:0] prefix_3_qs;
logic [31:0] prefix_3_wd;
logic prefix_4_we;
logic [31:0] prefix_4_qs;
logic [31:0] prefix_4_wd;
logic prefix_5_we;
logic [31:0] prefix_5_qs;
logic [31:0] prefix_5_wd;
logic prefix_6_we;
logic [31:0] prefix_6_qs;
logic [31:0] prefix_6_wd;
logic prefix_7_we;
logic [31:0] prefix_7_qs;
logic [31:0] prefix_7_wd;
logic prefix_8_we;
logic [31:0] prefix_8_qs;
logic [31:0] prefix_8_wd;
logic prefix_9_we;
logic [31:0] prefix_9_qs;
logic [31:0] prefix_9_wd;
logic prefix_10_we;
logic [31:0] prefix_10_qs;
logic [31:0] prefix_10_wd;
logic [31:0] err_code_qs;
// Register instances
// R[intr_state]: V(False)
// F[kmac_done]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_intr_state_kmac_done (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
.wd (intr_state_kmac_done_wd),
// from internal hardware
.de (hw2reg.intr_state.kmac_done.de),
.d (hw2reg.intr_state.kmac_done.d),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.kmac_done.q),
.ds (),
// to register interface (read)
.qs (intr_state_kmac_done_qs)
);
// F[fifo_empty]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_intr_state_fifo_empty (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
.wd (intr_state_fifo_empty_wd),
// from internal hardware
.de (hw2reg.intr_state.fifo_empty.de),
.d (hw2reg.intr_state.fifo_empty.d),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.fifo_empty.q),
.ds (),
// to register interface (read)
.qs (intr_state_fifo_empty_qs)
);
// F[kmac_err]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_intr_state_kmac_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
.wd (intr_state_kmac_err_wd),
// from internal hardware
.de (hw2reg.intr_state.kmac_err.de),
.d (hw2reg.intr_state.kmac_err.d),
// to internal hardware
.qe (),
.q (reg2hw.intr_state.kmac_err.q),
.ds (),
// to register interface (read)
.qs (intr_state_kmac_err_qs)
);
// R[intr_enable]: V(False)
// F[kmac_done]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_intr_enable_kmac_done (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
.wd (intr_enable_kmac_done_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.kmac_done.q),
.ds (),
// to register interface (read)
.qs (intr_enable_kmac_done_qs)
);
// F[fifo_empty]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_intr_enable_fifo_empty (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
.wd (intr_enable_fifo_empty_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.fifo_empty.q),
.ds (),
// to register interface (read)
.qs (intr_enable_fifo_empty_qs)
);
// F[kmac_err]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_intr_enable_kmac_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
.wd (intr_enable_kmac_err_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.intr_enable.kmac_err.q),
.ds (),
// to register interface (read)
.qs (intr_enable_kmac_err_qs)
);
// R[intr_test]: V(True)
logic intr_test_qe;
logic [2:0] intr_test_flds_we;
assign intr_test_qe = &intr_test_flds_we;
// F[kmac_done]: 0:0
prim_subreg_ext #(
.DW (1)
) u_intr_test_kmac_done (
.re (1'b0),
.we (intr_test_we),
.wd (intr_test_kmac_done_wd),
.d ('0),
.qre (),
.qe (intr_test_flds_we[0]),
.q (reg2hw.intr_test.kmac_done.q),
.ds (),
.qs ()
);
assign reg2hw.intr_test.kmac_done.qe = intr_test_qe;
// F[fifo_empty]: 1:1
prim_subreg_ext #(
.DW (1)
) u_intr_test_fifo_empty (
.re (1'b0),
.we (intr_test_we),
.wd (intr_test_fifo_empty_wd),
.d ('0),
.qre (),
.qe (intr_test_flds_we[1]),
.q (reg2hw.intr_test.fifo_empty.q),
.ds (),
.qs ()
);
assign reg2hw.intr_test.fifo_empty.qe = intr_test_qe;
// F[kmac_err]: 2:2
prim_subreg_ext #(
.DW (1)
) u_intr_test_kmac_err (
.re (1'b0),
.we (intr_test_we),
.wd (intr_test_kmac_err_wd),
.d ('0),
.qre (),
.qe (intr_test_flds_we[2]),
.q (reg2hw.intr_test.kmac_err.q),
.ds (),
.qs ()
);
assign reg2hw.intr_test.kmac_err.qe = intr_test_qe;
// R[alert_test]: V(True)
logic alert_test_qe;
logic [1:0] alert_test_flds_we;
assign alert_test_qe = &alert_test_flds_we;
// F[recov_operation_err]: 0:0
prim_subreg_ext #(
.DW (1)
) u_alert_test_recov_operation_err (
.re (1'b0),
.we (alert_test_we),
.wd (alert_test_recov_operation_err_wd),
.d ('0),
.qre (),
.qe (alert_test_flds_we[0]),
.q (reg2hw.alert_test.recov_operation_err.q),
.ds (),
.qs ()
);
assign reg2hw.alert_test.recov_operation_err.qe = alert_test_qe;
// F[fatal_fault_err]: 1:1
prim_subreg_ext #(
.DW (1)
) u_alert_test_fatal_fault_err (
.re (1'b0),
.we (alert_test_we),
.wd (alert_test_fatal_fault_err_wd),
.d ('0),
.qre (),
.qe (alert_test_flds_we[1]),
.q (reg2hw.alert_test.fatal_fault_err.q),
.ds (),
.qs ()
);
assign reg2hw.alert_test.fatal_fault_err.qe = alert_test_qe;
// R[cfg_regwen]: V(True)
prim_subreg_ext #(
.DW (1)
) u_cfg_regwen (
.re (cfg_regwen_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.cfg_regwen.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (cfg_regwen_qs)
);
// R[cfg_shadowed]: V(False)
logic cfg_shadowed_qe;
logic [11:0] cfg_shadowed_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_cfg_shadowed0_qe (
.clk_i(clk_i),
.rst_ni(rst_ni),
.d_i(&cfg_shadowed_flds_we),
.q_o(cfg_shadowed_qe)
);
// Create REGWEN-gated WE signal
logic cfg_shadowed_gated_we;
assign cfg_shadowed_gated_we = cfg_shadowed_we & cfg_regwen_qs;
// F[kmac_en]: 0:0
prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_cfg_shadowed_kmac_en (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (cfg_shadowed_re),
.we (cfg_shadowed_gated_we),
.wd (cfg_shadowed_kmac_en_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (cfg_shadowed_flds_we[0]),
.q (reg2hw.cfg_shadowed.kmac_en.q),
.ds (),
// to register interface (read)
.qs (cfg_shadowed_kmac_en_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (cfg_shadowed_kmac_en_update_err),
.err_storage (cfg_shadowed_kmac_en_storage_err)
);
assign reg2hw.cfg_shadowed.kmac_en.qe = cfg_shadowed_qe;
// F[kstrength]: 3:1
prim_subreg_shadow #(
.DW (3),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (3'h0)
) u_cfg_shadowed_kstrength (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (cfg_shadowed_re),
.we (cfg_shadowed_gated_we),
.wd (cfg_shadowed_kstrength_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (cfg_shadowed_flds_we[1]),
.q (reg2hw.cfg_shadowed.kstrength.q),
.ds (),
// to register interface (read)
.qs (cfg_shadowed_kstrength_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (cfg_shadowed_kstrength_update_err),
.err_storage (cfg_shadowed_kstrength_storage_err)
);
assign reg2hw.cfg_shadowed.kstrength.qe = cfg_shadowed_qe;
// F[mode]: 5:4
prim_subreg_shadow #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_cfg_shadowed_mode (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (cfg_shadowed_re),
.we (cfg_shadowed_gated_we),
.wd (cfg_shadowed_mode_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (cfg_shadowed_flds_we[2]),
.q (reg2hw.cfg_shadowed.mode.q),
.ds (),
// to register interface (read)
.qs (cfg_shadowed_mode_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (cfg_shadowed_mode_update_err),
.err_storage (cfg_shadowed_mode_storage_err)
);
assign reg2hw.cfg_shadowed.mode.qe = cfg_shadowed_qe;
// F[msg_endianness]: 8:8
prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_cfg_shadowed_msg_endianness (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (cfg_shadowed_re),
.we (cfg_shadowed_gated_we),
.wd (cfg_shadowed_msg_endianness_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (cfg_shadowed_flds_we[3]),
.q (reg2hw.cfg_shadowed.msg_endianness.q),
.ds (),
// to register interface (read)
.qs (cfg_shadowed_msg_endianness_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (cfg_shadowed_msg_endianness_update_err),
.err_storage (cfg_shadowed_msg_endianness_storage_err)
);
assign reg2hw.cfg_shadowed.msg_endianness.qe = cfg_shadowed_qe;
// F[state_endianness]: 9:9
prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_cfg_shadowed_state_endianness (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (cfg_shadowed_re),
.we (cfg_shadowed_gated_we),
.wd (cfg_shadowed_state_endianness_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (cfg_shadowed_flds_we[4]),
.q (reg2hw.cfg_shadowed.state_endianness.q),
.ds (),
// to register interface (read)
.qs (cfg_shadowed_state_endianness_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (cfg_shadowed_state_endianness_update_err),
.err_storage (cfg_shadowed_state_endianness_storage_err)
);
assign reg2hw.cfg_shadowed.state_endianness.qe = cfg_shadowed_qe;
// F[sideload]: 12:12
prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_cfg_shadowed_sideload (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (cfg_shadowed_re),
.we (cfg_shadowed_gated_we),
.wd (cfg_shadowed_sideload_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (cfg_shadowed_flds_we[5]),
.q (reg2hw.cfg_shadowed.sideload.q),
.ds (),
// to register interface (read)
.qs (cfg_shadowed_sideload_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (cfg_shadowed_sideload_update_err),
.err_storage (cfg_shadowed_sideload_storage_err)
);
assign reg2hw.cfg_shadowed.sideload.qe = cfg_shadowed_qe;
// F[entropy_mode]: 17:16
prim_subreg_shadow #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
) u_cfg_shadowed_entropy_mode (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (cfg_shadowed_re),
.we (cfg_shadowed_gated_we),
.wd (cfg_shadowed_entropy_mode_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (cfg_shadowed_flds_we[6]),
.q (reg2hw.cfg_shadowed.entropy_mode.q),
.ds (),
// to register interface (read)
.qs (cfg_shadowed_entropy_mode_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (cfg_shadowed_entropy_mode_update_err),
.err_storage (cfg_shadowed_entropy_mode_storage_err)
);
assign reg2hw.cfg_shadowed.entropy_mode.qe = cfg_shadowed_qe;
// F[entropy_fast_process]: 19:19
prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_cfg_shadowed_entropy_fast_process (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (cfg_shadowed_re),
.we (cfg_shadowed_gated_we),
.wd (cfg_shadowed_entropy_fast_process_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (cfg_shadowed_flds_we[7]),
.q (reg2hw.cfg_shadowed.entropy_fast_process.q),
.ds (),
// to register interface (read)
.qs (cfg_shadowed_entropy_fast_process_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (cfg_shadowed_entropy_fast_process_update_err),
.err_storage (cfg_shadowed_entropy_fast_process_storage_err)
);
assign reg2hw.cfg_shadowed.entropy_fast_process.qe = cfg_shadowed_qe;
// F[msg_mask]: 20:20
prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_cfg_shadowed_msg_mask (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (cfg_shadowed_re),
.we (cfg_shadowed_gated_we),
.wd (cfg_shadowed_msg_mask_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (cfg_shadowed_flds_we[8]),
.q (reg2hw.cfg_shadowed.msg_mask.q),
.ds (),
// to register interface (read)
.qs (cfg_shadowed_msg_mask_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (cfg_shadowed_msg_mask_update_err),
.err_storage (cfg_shadowed_msg_mask_storage_err)
);
assign reg2hw.cfg_shadowed.msg_mask.qe = cfg_shadowed_qe;
// F[entropy_ready]: 24:24
prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_cfg_shadowed_entropy_ready (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (cfg_shadowed_re),
.we (cfg_shadowed_gated_we),
.wd (cfg_shadowed_entropy_ready_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (cfg_shadowed_flds_we[9]),
.q (reg2hw.cfg_shadowed.entropy_ready.q),
.ds (),
// to register interface (read)
.qs (cfg_shadowed_entropy_ready_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (cfg_shadowed_entropy_ready_update_err),
.err_storage (cfg_shadowed_entropy_ready_storage_err)
);
assign reg2hw.cfg_shadowed.entropy_ready.qe = cfg_shadowed_qe;
// F[err_processed]: 25:25
prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_cfg_shadowed_err_processed (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (cfg_shadowed_re),
.we (cfg_shadowed_gated_we),
.wd (cfg_shadowed_err_processed_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (cfg_shadowed_flds_we[10]),
.q (reg2hw.cfg_shadowed.err_processed.q),
.ds (),
// to register interface (read)
.qs (cfg_shadowed_err_processed_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (cfg_shadowed_err_processed_update_err),
.err_storage (cfg_shadowed_err_processed_storage_err)
);
assign reg2hw.cfg_shadowed.err_processed.qe = cfg_shadowed_qe;
// F[en_unsupported_modestrength]: 26:26
prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_cfg_shadowed_en_unsupported_modestrength (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (cfg_shadowed_re),
.we (cfg_shadowed_gated_we),
.wd (cfg_shadowed_en_unsupported_modestrength_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (cfg_shadowed_flds_we[11]),
.q (reg2hw.cfg_shadowed.en_unsupported_modestrength.q),
.ds (),
// to register interface (read)
.qs (cfg_shadowed_en_unsupported_modestrength_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (cfg_shadowed_en_unsupported_modestrength_update_err),
.err_storage (cfg_shadowed_en_unsupported_modestrength_storage_err)
);
assign reg2hw.cfg_shadowed.en_unsupported_modestrength.qe = cfg_shadowed_qe;
// R[cmd]: V(True)
logic cmd_qe;
logic [2:0] cmd_flds_we;
assign cmd_qe = &cmd_flds_we;
// F[cmd]: 5:0
prim_subreg_ext #(
.DW (6)
) u_cmd_cmd (
.re (1'b0),
.we (cmd_we),
.wd (cmd_cmd_wd),
.d ('0),
.qre (),
.qe (cmd_flds_we[0]),
.q (reg2hw.cmd.cmd.q),
.ds (),
.qs ()
);
assign reg2hw.cmd.cmd.qe = cmd_qe;
// F[entropy_req]: 8:8
prim_subreg_ext #(
.DW (1)
) u_cmd_entropy_req (
.re (1'b0),
.we (cmd_we),
.wd (cmd_entropy_req_wd),
.d ('0),
.qre (),
.qe (cmd_flds_we[1]),
.q (reg2hw.cmd.entropy_req.q),
.ds (),
.qs ()
);
assign reg2hw.cmd.entropy_req.qe = cmd_qe;
// F[hash_cnt_clr]: 9:9
prim_subreg_ext #(
.DW (1)
) u_cmd_hash_cnt_clr (
.re (1'b0),
.we (cmd_we),
.wd (cmd_hash_cnt_clr_wd),
.d ('0),
.qre (),
.qe (cmd_flds_we[2]),
.q (reg2hw.cmd.hash_cnt_clr.q),
.ds (),
.qs ()
);
assign reg2hw.cmd.hash_cnt_clr.qe = cmd_qe;
// R[status]: V(True)
// F[sha3_idle]: 0:0
prim_subreg_ext #(
.DW (1)
) u_status_sha3_idle (
.re (status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.status.sha3_idle.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (status_sha3_idle_qs)
);
// F[sha3_absorb]: 1:1
prim_subreg_ext #(
.DW (1)
) u_status_sha3_absorb (
.re (status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.status.sha3_absorb.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (status_sha3_absorb_qs)
);
// F[sha3_squeeze]: 2:2
prim_subreg_ext #(
.DW (1)
) u_status_sha3_squeeze (
.re (status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.status.sha3_squeeze.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (status_sha3_squeeze_qs)
);
// F[fifo_depth]: 12:8
prim_subreg_ext #(
.DW (5)
) u_status_fifo_depth (
.re (status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.status.fifo_depth.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (status_fifo_depth_qs)
);
// F[fifo_empty]: 14:14
prim_subreg_ext #(
.DW (1)
) u_status_fifo_empty (
.re (status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.status.fifo_empty.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (status_fifo_empty_qs)
);
// F[fifo_full]: 15:15
prim_subreg_ext #(
.DW (1)
) u_status_fifo_full (
.re (status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.status.fifo_full.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (status_fifo_full_qs)
);
// F[alert_fatal_fault]: 16:16
prim_subreg_ext #(
.DW (1)
) u_status_alert_fatal_fault (
.re (status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.status.alert_fatal_fault.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (status_alert_fatal_fault_qs)
);
// F[alert_recov_ctrl_update_err]: 17:17
prim_subreg_ext #(
.DW (1)
) u_status_alert_recov_ctrl_update_err (
.re (status_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.status.alert_recov_ctrl_update_err.d),
.qre (),
.qe (),
.q (),
.ds (),
.qs (status_alert_recov_ctrl_update_err_qs)
);
// R[entropy_period]: V(False)
// Create REGWEN-gated WE signal
logic entropy_period_gated_we;
assign entropy_period_gated_we = entropy_period_we & cfg_regwen_qs;
// F[prescaler]: 9:0
prim_subreg #(
.DW (10),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (10'h0)
) u_entropy_period_prescaler (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (entropy_period_gated_we),
.wd (entropy_period_prescaler_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.entropy_period.prescaler.q),
.ds (),
// to register interface (read)
.qs (entropy_period_prescaler_qs)
);
// F[wait_timer]: 31:16
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_entropy_period_wait_timer (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (entropy_period_gated_we),
.wd (entropy_period_wait_timer_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.entropy_period.wait_timer.q),
.ds (),
// to register interface (read)
.qs (entropy_period_wait_timer_qs)
);
// R[entropy_refresh_hash_cnt]: V(False)
prim_subreg #(
.DW (10),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (10'h0)
) u_entropy_refresh_hash_cnt (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.entropy_refresh_hash_cnt.de),
.d (hw2reg.entropy_refresh_hash_cnt.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (entropy_refresh_hash_cnt_qs)
);
// R[entropy_refresh_threshold_shadowed]: V(False)
// Create REGWEN-gated WE signal
logic entropy_refresh_threshold_shadowed_gated_we;
assign entropy_refresh_threshold_shadowed_gated_we =
entropy_refresh_threshold_shadowed_we & cfg_regwen_qs;
prim_subreg_shadow #(
.DW (10),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (10'h0)
) u_entropy_refresh_threshold_shadowed (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rst_shadowed_ni (rst_shadowed_ni),
// from register interface
.re (entropy_refresh_threshold_shadowed_re),
.we (entropy_refresh_threshold_shadowed_gated_we),
.wd (entropy_refresh_threshold_shadowed_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.entropy_refresh_threshold_shadowed.q),
.ds (),
// to register interface (read)
.qs (entropy_refresh_threshold_shadowed_qs),
// Shadow register phase. Relevant for hwext only.
.phase (),
// Shadow register error conditions
.err_update (entropy_refresh_threshold_shadowed_update_err),
.err_storage (entropy_refresh_threshold_shadowed_storage_err)
);
// Subregister 0 of Multireg entropy_seed
// R[entropy_seed_0]: V(True)
logic entropy_seed_0_qe;
logic [0:0] entropy_seed_0_flds_we;
assign entropy_seed_0_qe = &entropy_seed_0_flds_we;
prim_subreg_ext #(
.DW (32)
) u_entropy_seed_0 (
.re (1'b0),
.we (entropy_seed_0_we),
.wd (entropy_seed_0_wd),
.d ('0),
.qre (),
.qe (entropy_seed_0_flds_we[0]),
.q (reg2hw.entropy_seed[0].q),
.ds (),
.qs ()
);
assign reg2hw.entropy_seed[0].qe = entropy_seed_0_qe;
// Subregister 1 of Multireg entropy_seed
// R[entropy_seed_1]: V(True)
logic entropy_seed_1_qe;
logic [0:0] entropy_seed_1_flds_we;
assign entropy_seed_1_qe = &entropy_seed_1_flds_we;
prim_subreg_ext #(
.DW (32)
) u_entropy_seed_1 (
.re (1'b0),
.we (entropy_seed_1_we),
.wd (entropy_seed_1_wd),
.d ('0),
.qre (),
.qe (entropy_seed_1_flds_we[0]),
.q (reg2hw.entropy_seed[1].q),
.ds (),
.qs ()
);
assign reg2hw.entropy_seed[1].qe = entropy_seed_1_qe;
// Subregister 2 of Multireg entropy_seed
// R[entropy_seed_2]: V(True)
logic entropy_seed_2_qe;
logic [0:0] entropy_seed_2_flds_we;
assign entropy_seed_2_qe = &entropy_seed_2_flds_we;
prim_subreg_ext #(
.DW (32)
) u_entropy_seed_2 (
.re (1'b0),
.we (entropy_seed_2_we),
.wd (entropy_seed_2_wd),
.d ('0),
.qre (),
.qe (entropy_seed_2_flds_we[0]),
.q (reg2hw.entropy_seed[2].q),
.ds (),
.qs ()
);
assign reg2hw.entropy_seed[2].qe = entropy_seed_2_qe;
// Subregister 3 of Multireg entropy_seed
// R[entropy_seed_3]: V(True)
logic entropy_seed_3_qe;
logic [0:0] entropy_seed_3_flds_we;
assign entropy_seed_3_qe = &entropy_seed_3_flds_we;
prim_subreg_ext #(
.DW (32)
) u_entropy_seed_3 (
.re (1'b0),
.we (entropy_seed_3_we),
.wd (entropy_seed_3_wd),
.d ('0),
.qre (),
.qe (entropy_seed_3_flds_we[0]),
.q (reg2hw.entropy_seed[3].q),
.ds (),
.qs ()
);
assign reg2hw.entropy_seed[3].qe = entropy_seed_3_qe;
// Subregister 4 of Multireg entropy_seed
// R[entropy_seed_4]: V(True)
logic entropy_seed_4_qe;
logic [0:0] entropy_seed_4_flds_we;
assign entropy_seed_4_qe = &entropy_seed_4_flds_we;
prim_subreg_ext #(
.DW (32)
) u_entropy_seed_4 (
.re (1'b0),
.we (entropy_seed_4_we),
.wd (entropy_seed_4_wd),
.d ('0),
.qre (),
.qe (entropy_seed_4_flds_we[0]),
.q (reg2hw.entropy_seed[4].q),
.ds (),
.qs ()
);
assign reg2hw.entropy_seed[4].qe = entropy_seed_4_qe;
// Subregister 0 of Multireg key_share0
// R[key_share0_0]: V(True)
logic key_share0_0_qe;
logic [0:0] key_share0_0_flds_we;
assign key_share0_0_qe = &key_share0_0_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_0_gated_we;
assign key_share0_0_gated_we = key_share0_0_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_0 (
.re (1'b0),
.we (key_share0_0_gated_we),
.wd (key_share0_0_wd),
.d ('0),
.qre (),
.qe (key_share0_0_flds_we[0]),
.q (reg2hw.key_share0[0].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[0].qe = key_share0_0_qe;
// Subregister 1 of Multireg key_share0
// R[key_share0_1]: V(True)
logic key_share0_1_qe;
logic [0:0] key_share0_1_flds_we;
assign key_share0_1_qe = &key_share0_1_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_1_gated_we;
assign key_share0_1_gated_we = key_share0_1_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_1 (
.re (1'b0),
.we (key_share0_1_gated_we),
.wd (key_share0_1_wd),
.d ('0),
.qre (),
.qe (key_share0_1_flds_we[0]),
.q (reg2hw.key_share0[1].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[1].qe = key_share0_1_qe;
// Subregister 2 of Multireg key_share0
// R[key_share0_2]: V(True)
logic key_share0_2_qe;
logic [0:0] key_share0_2_flds_we;
assign key_share0_2_qe = &key_share0_2_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_2_gated_we;
assign key_share0_2_gated_we = key_share0_2_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_2 (
.re (1'b0),
.we (key_share0_2_gated_we),
.wd (key_share0_2_wd),
.d ('0),
.qre (),
.qe (key_share0_2_flds_we[0]),
.q (reg2hw.key_share0[2].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[2].qe = key_share0_2_qe;
// Subregister 3 of Multireg key_share0
// R[key_share0_3]: V(True)
logic key_share0_3_qe;
logic [0:0] key_share0_3_flds_we;
assign key_share0_3_qe = &key_share0_3_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_3_gated_we;
assign key_share0_3_gated_we = key_share0_3_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_3 (
.re (1'b0),
.we (key_share0_3_gated_we),
.wd (key_share0_3_wd),
.d ('0),
.qre (),
.qe (key_share0_3_flds_we[0]),
.q (reg2hw.key_share0[3].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[3].qe = key_share0_3_qe;
// Subregister 4 of Multireg key_share0
// R[key_share0_4]: V(True)
logic key_share0_4_qe;
logic [0:0] key_share0_4_flds_we;
assign key_share0_4_qe = &key_share0_4_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_4_gated_we;
assign key_share0_4_gated_we = key_share0_4_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_4 (
.re (1'b0),
.we (key_share0_4_gated_we),
.wd (key_share0_4_wd),
.d ('0),
.qre (),
.qe (key_share0_4_flds_we[0]),
.q (reg2hw.key_share0[4].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[4].qe = key_share0_4_qe;
// Subregister 5 of Multireg key_share0
// R[key_share0_5]: V(True)
logic key_share0_5_qe;
logic [0:0] key_share0_5_flds_we;
assign key_share0_5_qe = &key_share0_5_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_5_gated_we;
assign key_share0_5_gated_we = key_share0_5_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_5 (
.re (1'b0),
.we (key_share0_5_gated_we),
.wd (key_share0_5_wd),
.d ('0),
.qre (),
.qe (key_share0_5_flds_we[0]),
.q (reg2hw.key_share0[5].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[5].qe = key_share0_5_qe;
// Subregister 6 of Multireg key_share0
// R[key_share0_6]: V(True)
logic key_share0_6_qe;
logic [0:0] key_share0_6_flds_we;
assign key_share0_6_qe = &key_share0_6_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_6_gated_we;
assign key_share0_6_gated_we = key_share0_6_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_6 (
.re (1'b0),
.we (key_share0_6_gated_we),
.wd (key_share0_6_wd),
.d ('0),
.qre (),
.qe (key_share0_6_flds_we[0]),
.q (reg2hw.key_share0[6].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[6].qe = key_share0_6_qe;
// Subregister 7 of Multireg key_share0
// R[key_share0_7]: V(True)
logic key_share0_7_qe;
logic [0:0] key_share0_7_flds_we;
assign key_share0_7_qe = &key_share0_7_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_7_gated_we;
assign key_share0_7_gated_we = key_share0_7_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_7 (
.re (1'b0),
.we (key_share0_7_gated_we),
.wd (key_share0_7_wd),
.d ('0),
.qre (),
.qe (key_share0_7_flds_we[0]),
.q (reg2hw.key_share0[7].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[7].qe = key_share0_7_qe;
// Subregister 8 of Multireg key_share0
// R[key_share0_8]: V(True)
logic key_share0_8_qe;
logic [0:0] key_share0_8_flds_we;
assign key_share0_8_qe = &key_share0_8_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_8_gated_we;
assign key_share0_8_gated_we = key_share0_8_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_8 (
.re (1'b0),
.we (key_share0_8_gated_we),
.wd (key_share0_8_wd),
.d ('0),
.qre (),
.qe (key_share0_8_flds_we[0]),
.q (reg2hw.key_share0[8].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[8].qe = key_share0_8_qe;
// Subregister 9 of Multireg key_share0
// R[key_share0_9]: V(True)
logic key_share0_9_qe;
logic [0:0] key_share0_9_flds_we;
assign key_share0_9_qe = &key_share0_9_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_9_gated_we;
assign key_share0_9_gated_we = key_share0_9_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_9 (
.re (1'b0),
.we (key_share0_9_gated_we),
.wd (key_share0_9_wd),
.d ('0),
.qre (),
.qe (key_share0_9_flds_we[0]),
.q (reg2hw.key_share0[9].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[9].qe = key_share0_9_qe;
// Subregister 10 of Multireg key_share0
// R[key_share0_10]: V(True)
logic key_share0_10_qe;
logic [0:0] key_share0_10_flds_we;
assign key_share0_10_qe = &key_share0_10_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_10_gated_we;
assign key_share0_10_gated_we = key_share0_10_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_10 (
.re (1'b0),
.we (key_share0_10_gated_we),
.wd (key_share0_10_wd),
.d ('0),
.qre (),
.qe (key_share0_10_flds_we[0]),
.q (reg2hw.key_share0[10].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[10].qe = key_share0_10_qe;
// Subregister 11 of Multireg key_share0
// R[key_share0_11]: V(True)
logic key_share0_11_qe;
logic [0:0] key_share0_11_flds_we;
assign key_share0_11_qe = &key_share0_11_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_11_gated_we;
assign key_share0_11_gated_we = key_share0_11_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_11 (
.re (1'b0),
.we (key_share0_11_gated_we),
.wd (key_share0_11_wd),
.d ('0),
.qre (),
.qe (key_share0_11_flds_we[0]),
.q (reg2hw.key_share0[11].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[11].qe = key_share0_11_qe;
// Subregister 12 of Multireg key_share0
// R[key_share0_12]: V(True)
logic key_share0_12_qe;
logic [0:0] key_share0_12_flds_we;
assign key_share0_12_qe = &key_share0_12_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_12_gated_we;
assign key_share0_12_gated_we = key_share0_12_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_12 (
.re (1'b0),
.we (key_share0_12_gated_we),
.wd (key_share0_12_wd),
.d ('0),
.qre (),
.qe (key_share0_12_flds_we[0]),
.q (reg2hw.key_share0[12].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[12].qe = key_share0_12_qe;
// Subregister 13 of Multireg key_share0
// R[key_share0_13]: V(True)
logic key_share0_13_qe;
logic [0:0] key_share0_13_flds_we;
assign key_share0_13_qe = &key_share0_13_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_13_gated_we;
assign key_share0_13_gated_we = key_share0_13_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_13 (
.re (1'b0),
.we (key_share0_13_gated_we),
.wd (key_share0_13_wd),
.d ('0),
.qre (),
.qe (key_share0_13_flds_we[0]),
.q (reg2hw.key_share0[13].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[13].qe = key_share0_13_qe;
// Subregister 14 of Multireg key_share0
// R[key_share0_14]: V(True)
logic key_share0_14_qe;
logic [0:0] key_share0_14_flds_we;
assign key_share0_14_qe = &key_share0_14_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_14_gated_we;
assign key_share0_14_gated_we = key_share0_14_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_14 (
.re (1'b0),
.we (key_share0_14_gated_we),
.wd (key_share0_14_wd),
.d ('0),
.qre (),
.qe (key_share0_14_flds_we[0]),
.q (reg2hw.key_share0[14].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[14].qe = key_share0_14_qe;
// Subregister 15 of Multireg key_share0
// R[key_share0_15]: V(True)
logic key_share0_15_qe;
logic [0:0] key_share0_15_flds_we;
assign key_share0_15_qe = &key_share0_15_flds_we;
// Create REGWEN-gated WE signal
logic key_share0_15_gated_we;
assign key_share0_15_gated_we = key_share0_15_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share0_15 (
.re (1'b0),
.we (key_share0_15_gated_we),
.wd (key_share0_15_wd),
.d ('0),
.qre (),
.qe (key_share0_15_flds_we[0]),
.q (reg2hw.key_share0[15].q),
.ds (),
.qs ()
);
assign reg2hw.key_share0[15].qe = key_share0_15_qe;
// Subregister 0 of Multireg key_share1
// R[key_share1_0]: V(True)
logic key_share1_0_qe;
logic [0:0] key_share1_0_flds_we;
assign key_share1_0_qe = &key_share1_0_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_0_gated_we;
assign key_share1_0_gated_we = key_share1_0_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_0 (
.re (1'b0),
.we (key_share1_0_gated_we),
.wd (key_share1_0_wd),
.d ('0),
.qre (),
.qe (key_share1_0_flds_we[0]),
.q (reg2hw.key_share1[0].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[0].qe = key_share1_0_qe;
// Subregister 1 of Multireg key_share1
// R[key_share1_1]: V(True)
logic key_share1_1_qe;
logic [0:0] key_share1_1_flds_we;
assign key_share1_1_qe = &key_share1_1_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_1_gated_we;
assign key_share1_1_gated_we = key_share1_1_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_1 (
.re (1'b0),
.we (key_share1_1_gated_we),
.wd (key_share1_1_wd),
.d ('0),
.qre (),
.qe (key_share1_1_flds_we[0]),
.q (reg2hw.key_share1[1].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[1].qe = key_share1_1_qe;
// Subregister 2 of Multireg key_share1
// R[key_share1_2]: V(True)
logic key_share1_2_qe;
logic [0:0] key_share1_2_flds_we;
assign key_share1_2_qe = &key_share1_2_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_2_gated_we;
assign key_share1_2_gated_we = key_share1_2_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_2 (
.re (1'b0),
.we (key_share1_2_gated_we),
.wd (key_share1_2_wd),
.d ('0),
.qre (),
.qe (key_share1_2_flds_we[0]),
.q (reg2hw.key_share1[2].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[2].qe = key_share1_2_qe;
// Subregister 3 of Multireg key_share1
// R[key_share1_3]: V(True)
logic key_share1_3_qe;
logic [0:0] key_share1_3_flds_we;
assign key_share1_3_qe = &key_share1_3_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_3_gated_we;
assign key_share1_3_gated_we = key_share1_3_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_3 (
.re (1'b0),
.we (key_share1_3_gated_we),
.wd (key_share1_3_wd),
.d ('0),
.qre (),
.qe (key_share1_3_flds_we[0]),
.q (reg2hw.key_share1[3].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[3].qe = key_share1_3_qe;
// Subregister 4 of Multireg key_share1
// R[key_share1_4]: V(True)
logic key_share1_4_qe;
logic [0:0] key_share1_4_flds_we;
assign key_share1_4_qe = &key_share1_4_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_4_gated_we;
assign key_share1_4_gated_we = key_share1_4_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_4 (
.re (1'b0),
.we (key_share1_4_gated_we),
.wd (key_share1_4_wd),
.d ('0),
.qre (),
.qe (key_share1_4_flds_we[0]),
.q (reg2hw.key_share1[4].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[4].qe = key_share1_4_qe;
// Subregister 5 of Multireg key_share1
// R[key_share1_5]: V(True)
logic key_share1_5_qe;
logic [0:0] key_share1_5_flds_we;
assign key_share1_5_qe = &key_share1_5_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_5_gated_we;
assign key_share1_5_gated_we = key_share1_5_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_5 (
.re (1'b0),
.we (key_share1_5_gated_we),
.wd (key_share1_5_wd),
.d ('0),
.qre (),
.qe (key_share1_5_flds_we[0]),
.q (reg2hw.key_share1[5].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[5].qe = key_share1_5_qe;
// Subregister 6 of Multireg key_share1
// R[key_share1_6]: V(True)
logic key_share1_6_qe;
logic [0:0] key_share1_6_flds_we;
assign key_share1_6_qe = &key_share1_6_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_6_gated_we;
assign key_share1_6_gated_we = key_share1_6_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_6 (
.re (1'b0),
.we (key_share1_6_gated_we),
.wd (key_share1_6_wd),
.d ('0),
.qre (),
.qe (key_share1_6_flds_we[0]),
.q (reg2hw.key_share1[6].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[6].qe = key_share1_6_qe;
// Subregister 7 of Multireg key_share1
// R[key_share1_7]: V(True)
logic key_share1_7_qe;
logic [0:0] key_share1_7_flds_we;
assign key_share1_7_qe = &key_share1_7_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_7_gated_we;
assign key_share1_7_gated_we = key_share1_7_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_7 (
.re (1'b0),
.we (key_share1_7_gated_we),
.wd (key_share1_7_wd),
.d ('0),
.qre (),
.qe (key_share1_7_flds_we[0]),
.q (reg2hw.key_share1[7].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[7].qe = key_share1_7_qe;
// Subregister 8 of Multireg key_share1
// R[key_share1_8]: V(True)
logic key_share1_8_qe;
logic [0:0] key_share1_8_flds_we;
assign key_share1_8_qe = &key_share1_8_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_8_gated_we;
assign key_share1_8_gated_we = key_share1_8_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_8 (
.re (1'b0),
.we (key_share1_8_gated_we),
.wd (key_share1_8_wd),
.d ('0),
.qre (),
.qe (key_share1_8_flds_we[0]),
.q (reg2hw.key_share1[8].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[8].qe = key_share1_8_qe;
// Subregister 9 of Multireg key_share1
// R[key_share1_9]: V(True)
logic key_share1_9_qe;
logic [0:0] key_share1_9_flds_we;
assign key_share1_9_qe = &key_share1_9_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_9_gated_we;
assign key_share1_9_gated_we = key_share1_9_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_9 (
.re (1'b0),
.we (key_share1_9_gated_we),
.wd (key_share1_9_wd),
.d ('0),
.qre (),
.qe (key_share1_9_flds_we[0]),
.q (reg2hw.key_share1[9].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[9].qe = key_share1_9_qe;
// Subregister 10 of Multireg key_share1
// R[key_share1_10]: V(True)
logic key_share1_10_qe;
logic [0:0] key_share1_10_flds_we;
assign key_share1_10_qe = &key_share1_10_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_10_gated_we;
assign key_share1_10_gated_we = key_share1_10_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_10 (
.re (1'b0),
.we (key_share1_10_gated_we),
.wd (key_share1_10_wd),
.d ('0),
.qre (),
.qe (key_share1_10_flds_we[0]),
.q (reg2hw.key_share1[10].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[10].qe = key_share1_10_qe;
// Subregister 11 of Multireg key_share1
// R[key_share1_11]: V(True)
logic key_share1_11_qe;
logic [0:0] key_share1_11_flds_we;
assign key_share1_11_qe = &key_share1_11_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_11_gated_we;
assign key_share1_11_gated_we = key_share1_11_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_11 (
.re (1'b0),
.we (key_share1_11_gated_we),
.wd (key_share1_11_wd),
.d ('0),
.qre (),
.qe (key_share1_11_flds_we[0]),
.q (reg2hw.key_share1[11].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[11].qe = key_share1_11_qe;
// Subregister 12 of Multireg key_share1
// R[key_share1_12]: V(True)
logic key_share1_12_qe;
logic [0:0] key_share1_12_flds_we;
assign key_share1_12_qe = &key_share1_12_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_12_gated_we;
assign key_share1_12_gated_we = key_share1_12_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_12 (
.re (1'b0),
.we (key_share1_12_gated_we),
.wd (key_share1_12_wd),
.d ('0),
.qre (),
.qe (key_share1_12_flds_we[0]),
.q (reg2hw.key_share1[12].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[12].qe = key_share1_12_qe;
// Subregister 13 of Multireg key_share1
// R[key_share1_13]: V(True)
logic key_share1_13_qe;
logic [0:0] key_share1_13_flds_we;
assign key_share1_13_qe = &key_share1_13_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_13_gated_we;
assign key_share1_13_gated_we = key_share1_13_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_13 (
.re (1'b0),
.we (key_share1_13_gated_we),
.wd (key_share1_13_wd),
.d ('0),
.qre (),
.qe (key_share1_13_flds_we[0]),
.q (reg2hw.key_share1[13].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[13].qe = key_share1_13_qe;
// Subregister 14 of Multireg key_share1
// R[key_share1_14]: V(True)
logic key_share1_14_qe;
logic [0:0] key_share1_14_flds_we;
assign key_share1_14_qe = &key_share1_14_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_14_gated_we;
assign key_share1_14_gated_we = key_share1_14_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_14 (
.re (1'b0),
.we (key_share1_14_gated_we),
.wd (key_share1_14_wd),
.d ('0),
.qre (),
.qe (key_share1_14_flds_we[0]),
.q (reg2hw.key_share1[14].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[14].qe = key_share1_14_qe;
// Subregister 15 of Multireg key_share1
// R[key_share1_15]: V(True)
logic key_share1_15_qe;
logic [0:0] key_share1_15_flds_we;
assign key_share1_15_qe = &key_share1_15_flds_we;
// Create REGWEN-gated WE signal
logic key_share1_15_gated_we;
assign key_share1_15_gated_we = key_share1_15_we & cfg_regwen_qs;
prim_subreg_ext #(
.DW (32)
) u_key_share1_15 (
.re (1'b0),
.we (key_share1_15_gated_we),
.wd (key_share1_15_wd),
.d ('0),
.qre (),
.qe (key_share1_15_flds_we[0]),
.q (reg2hw.key_share1[15].q),
.ds (),
.qs ()
);
assign reg2hw.key_share1[15].qe = key_share1_15_qe;
// R[key_len]: V(False)
// Create REGWEN-gated WE signal
logic key_len_gated_we;
assign key_len_gated_we = key_len_we & cfg_regwen_qs;
prim_subreg #(
.DW (3),
.SwAccess(prim_subreg_pkg::SwAccessWO),
.RESVAL (3'h0)
) u_key_len (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (key_len_gated_we),
.wd (key_len_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.key_len.q),
.ds (),
// to register interface (read)
.qs ()
);
// Subregister 0 of Multireg prefix
// R[prefix_0]: V(False)
// Create REGWEN-gated WE signal
logic prefix_0_gated_we;
assign prefix_0_gated_we = prefix_0_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_prefix_0 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prefix_0_gated_we),
.wd (prefix_0_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prefix[0].q),
.ds (),
// to register interface (read)
.qs (prefix_0_qs)
);
// Subregister 1 of Multireg prefix
// R[prefix_1]: V(False)
// Create REGWEN-gated WE signal
logic prefix_1_gated_we;
assign prefix_1_gated_we = prefix_1_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_prefix_1 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prefix_1_gated_we),
.wd (prefix_1_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prefix[1].q),
.ds (),
// to register interface (read)
.qs (prefix_1_qs)
);
// Subregister 2 of Multireg prefix
// R[prefix_2]: V(False)
// Create REGWEN-gated WE signal
logic prefix_2_gated_we;
assign prefix_2_gated_we = prefix_2_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_prefix_2 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prefix_2_gated_we),
.wd (prefix_2_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prefix[2].q),
.ds (),
// to register interface (read)
.qs (prefix_2_qs)
);
// Subregister 3 of Multireg prefix
// R[prefix_3]: V(False)
// Create REGWEN-gated WE signal
logic prefix_3_gated_we;
assign prefix_3_gated_we = prefix_3_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_prefix_3 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prefix_3_gated_we),
.wd (prefix_3_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prefix[3].q),
.ds (),
// to register interface (read)
.qs (prefix_3_qs)
);
// Subregister 4 of Multireg prefix
// R[prefix_4]: V(False)
// Create REGWEN-gated WE signal
logic prefix_4_gated_we;
assign prefix_4_gated_we = prefix_4_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_prefix_4 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prefix_4_gated_we),
.wd (prefix_4_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prefix[4].q),
.ds (),
// to register interface (read)
.qs (prefix_4_qs)
);
// Subregister 5 of Multireg prefix
// R[prefix_5]: V(False)
// Create REGWEN-gated WE signal
logic prefix_5_gated_we;
assign prefix_5_gated_we = prefix_5_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_prefix_5 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prefix_5_gated_we),
.wd (prefix_5_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prefix[5].q),
.ds (),
// to register interface (read)
.qs (prefix_5_qs)
);
// Subregister 6 of Multireg prefix
// R[prefix_6]: V(False)
// Create REGWEN-gated WE signal
logic prefix_6_gated_we;
assign prefix_6_gated_we = prefix_6_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_prefix_6 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prefix_6_gated_we),
.wd (prefix_6_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prefix[6].q),
.ds (),
// to register interface (read)
.qs (prefix_6_qs)
);
// Subregister 7 of Multireg prefix
// R[prefix_7]: V(False)
// Create REGWEN-gated WE signal
logic prefix_7_gated_we;
assign prefix_7_gated_we = prefix_7_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_prefix_7 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prefix_7_gated_we),
.wd (prefix_7_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prefix[7].q),
.ds (),
// to register interface (read)
.qs (prefix_7_qs)
);
// Subregister 8 of Multireg prefix
// R[prefix_8]: V(False)
// Create REGWEN-gated WE signal
logic prefix_8_gated_we;
assign prefix_8_gated_we = prefix_8_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_prefix_8 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prefix_8_gated_we),
.wd (prefix_8_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prefix[8].q),
.ds (),
// to register interface (read)
.qs (prefix_8_qs)
);
// Subregister 9 of Multireg prefix
// R[prefix_9]: V(False)
// Create REGWEN-gated WE signal
logic prefix_9_gated_we;
assign prefix_9_gated_we = prefix_9_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_prefix_9 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prefix_9_gated_we),
.wd (prefix_9_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prefix[9].q),
.ds (),
// to register interface (read)
.qs (prefix_9_qs)
);
// Subregister 10 of Multireg prefix
// R[prefix_10]: V(False)
// Create REGWEN-gated WE signal
logic prefix_10_gated_we;
assign prefix_10_gated_we = prefix_10_we & cfg_regwen_qs;
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (32'h0)
) u_prefix_10 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (prefix_10_gated_we),
.wd (prefix_10_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (reg2hw.prefix[10].q),
.ds (),
// to register interface (read)
.qs (prefix_10_qs)
);
// R[err_code]: V(False)
prim_subreg #(
.DW (32),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (32'h0)
) u_err_code (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (1'b0),
.wd ('0),
// from internal hardware
.de (hw2reg.err_code.de),
.d (hw2reg.err_code.d),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (err_code_qs)
);
logic [60:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == KMAC_INTR_STATE_OFFSET);
addr_hit[ 1] = (reg_addr == KMAC_INTR_ENABLE_OFFSET);
addr_hit[ 2] = (reg_addr == KMAC_INTR_TEST_OFFSET);
addr_hit[ 3] = (reg_addr == KMAC_ALERT_TEST_OFFSET);
addr_hit[ 4] = (reg_addr == KMAC_CFG_REGWEN_OFFSET);
addr_hit[ 5] = (reg_addr == KMAC_CFG_SHADOWED_OFFSET);
addr_hit[ 6] = (reg_addr == KMAC_CMD_OFFSET);
addr_hit[ 7] = (reg_addr == KMAC_STATUS_OFFSET);
addr_hit[ 8] = (reg_addr == KMAC_ENTROPY_PERIOD_OFFSET);
addr_hit[ 9] = (reg_addr == KMAC_ENTROPY_REFRESH_HASH_CNT_OFFSET);
addr_hit[10] = (reg_addr == KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED_OFFSET);
addr_hit[11] = (reg_addr == KMAC_ENTROPY_SEED_0_OFFSET);
addr_hit[12] = (reg_addr == KMAC_ENTROPY_SEED_1_OFFSET);
addr_hit[13] = (reg_addr == KMAC_ENTROPY_SEED_2_OFFSET);
addr_hit[14] = (reg_addr == KMAC_ENTROPY_SEED_3_OFFSET);
addr_hit[15] = (reg_addr == KMAC_ENTROPY_SEED_4_OFFSET);
addr_hit[16] = (reg_addr == KMAC_KEY_SHARE0_0_OFFSET);
addr_hit[17] = (reg_addr == KMAC_KEY_SHARE0_1_OFFSET);
addr_hit[18] = (reg_addr == KMAC_KEY_SHARE0_2_OFFSET);
addr_hit[19] = (reg_addr == KMAC_KEY_SHARE0_3_OFFSET);
addr_hit[20] = (reg_addr == KMAC_KEY_SHARE0_4_OFFSET);
addr_hit[21] = (reg_addr == KMAC_KEY_SHARE0_5_OFFSET);
addr_hit[22] = (reg_addr == KMAC_KEY_SHARE0_6_OFFSET);
addr_hit[23] = (reg_addr == KMAC_KEY_SHARE0_7_OFFSET);
addr_hit[24] = (reg_addr == KMAC_KEY_SHARE0_8_OFFSET);
addr_hit[25] = (reg_addr == KMAC_KEY_SHARE0_9_OFFSET);
addr_hit[26] = (reg_addr == KMAC_KEY_SHARE0_10_OFFSET);
addr_hit[27] = (reg_addr == KMAC_KEY_SHARE0_11_OFFSET);
addr_hit[28] = (reg_addr == KMAC_KEY_SHARE0_12_OFFSET);
addr_hit[29] = (reg_addr == KMAC_KEY_SHARE0_13_OFFSET);
addr_hit[30] = (reg_addr == KMAC_KEY_SHARE0_14_OFFSET);
addr_hit[31] = (reg_addr == KMAC_KEY_SHARE0_15_OFFSET);
addr_hit[32] = (reg_addr == KMAC_KEY_SHARE1_0_OFFSET);
addr_hit[33] = (reg_addr == KMAC_KEY_SHARE1_1_OFFSET);
addr_hit[34] = (reg_addr == KMAC_KEY_SHARE1_2_OFFSET);
addr_hit[35] = (reg_addr == KMAC_KEY_SHARE1_3_OFFSET);
addr_hit[36] = (reg_addr == KMAC_KEY_SHARE1_4_OFFSET);
addr_hit[37] = (reg_addr == KMAC_KEY_SHARE1_5_OFFSET);
addr_hit[38] = (reg_addr == KMAC_KEY_SHARE1_6_OFFSET);
addr_hit[39] = (reg_addr == KMAC_KEY_SHARE1_7_OFFSET);
addr_hit[40] = (reg_addr == KMAC_KEY_SHARE1_8_OFFSET);
addr_hit[41] = (reg_addr == KMAC_KEY_SHARE1_9_OFFSET);
addr_hit[42] = (reg_addr == KMAC_KEY_SHARE1_10_OFFSET);
addr_hit[43] = (reg_addr == KMAC_KEY_SHARE1_11_OFFSET);
addr_hit[44] = (reg_addr == KMAC_KEY_SHARE1_12_OFFSET);
addr_hit[45] = (reg_addr == KMAC_KEY_SHARE1_13_OFFSET);
addr_hit[46] = (reg_addr == KMAC_KEY_SHARE1_14_OFFSET);
addr_hit[47] = (reg_addr == KMAC_KEY_SHARE1_15_OFFSET);
addr_hit[48] = (reg_addr == KMAC_KEY_LEN_OFFSET);
addr_hit[49] = (reg_addr == KMAC_PREFIX_0_OFFSET);
addr_hit[50] = (reg_addr == KMAC_PREFIX_1_OFFSET);
addr_hit[51] = (reg_addr == KMAC_PREFIX_2_OFFSET);
addr_hit[52] = (reg_addr == KMAC_PREFIX_3_OFFSET);
addr_hit[53] = (reg_addr == KMAC_PREFIX_4_OFFSET);
addr_hit[54] = (reg_addr == KMAC_PREFIX_5_OFFSET);
addr_hit[55] = (reg_addr == KMAC_PREFIX_6_OFFSET);
addr_hit[56] = (reg_addr == KMAC_PREFIX_7_OFFSET);
addr_hit[57] = (reg_addr == KMAC_PREFIX_8_OFFSET);
addr_hit[58] = (reg_addr == KMAC_PREFIX_9_OFFSET);
addr_hit[59] = (reg_addr == KMAC_PREFIX_10_OFFSET);
addr_hit[60] = (reg_addr == KMAC_ERR_CODE_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
// Check sub-word write is permitted
always_comb begin
wr_err = (reg_we &
((addr_hit[ 0] & (|(KMAC_PERMIT[ 0] & ~reg_be))) |
(addr_hit[ 1] & (|(KMAC_PERMIT[ 1] & ~reg_be))) |
(addr_hit[ 2] & (|(KMAC_PERMIT[ 2] & ~reg_be))) |
(addr_hit[ 3] & (|(KMAC_PERMIT[ 3] & ~reg_be))) |
(addr_hit[ 4] & (|(KMAC_PERMIT[ 4] & ~reg_be))) |
(addr_hit[ 5] & (|(KMAC_PERMIT[ 5] & ~reg_be))) |
(addr_hit[ 6] & (|(KMAC_PERMIT[ 6] & ~reg_be))) |
(addr_hit[ 7] & (|(KMAC_PERMIT[ 7] & ~reg_be))) |
(addr_hit[ 8] & (|(KMAC_PERMIT[ 8] & ~reg_be))) |
(addr_hit[ 9] & (|(KMAC_PERMIT[ 9] & ~reg_be))) |
(addr_hit[10] & (|(KMAC_PERMIT[10] & ~reg_be))) |
(addr_hit[11] & (|(KMAC_PERMIT[11] & ~reg_be))) |
(addr_hit[12] & (|(KMAC_PERMIT[12] & ~reg_be))) |
(addr_hit[13] & (|(KMAC_PERMIT[13] & ~reg_be))) |
(addr_hit[14] & (|(KMAC_PERMIT[14] & ~reg_be))) |
(addr_hit[15] & (|(KMAC_PERMIT[15] & ~reg_be))) |
(addr_hit[16] & (|(KMAC_PERMIT[16] & ~reg_be))) |
(addr_hit[17] & (|(KMAC_PERMIT[17] & ~reg_be))) |
(addr_hit[18] & (|(KMAC_PERMIT[18] & ~reg_be))) |
(addr_hit[19] & (|(KMAC_PERMIT[19] & ~reg_be))) |
(addr_hit[20] & (|(KMAC_PERMIT[20] & ~reg_be))) |
(addr_hit[21] & (|(KMAC_PERMIT[21] & ~reg_be))) |
(addr_hit[22] & (|(KMAC_PERMIT[22] & ~reg_be))) |
(addr_hit[23] & (|(KMAC_PERMIT[23] & ~reg_be))) |
(addr_hit[24] & (|(KMAC_PERMIT[24] & ~reg_be))) |
(addr_hit[25] & (|(KMAC_PERMIT[25] & ~reg_be))) |
(addr_hit[26] & (|(KMAC_PERMIT[26] & ~reg_be))) |
(addr_hit[27] & (|(KMAC_PERMIT[27] & ~reg_be))) |
(addr_hit[28] & (|(KMAC_PERMIT[28] & ~reg_be))) |
(addr_hit[29] & (|(KMAC_PERMIT[29] & ~reg_be))) |
(addr_hit[30] & (|(KMAC_PERMIT[30] & ~reg_be))) |
(addr_hit[31] & (|(KMAC_PERMIT[31] & ~reg_be))) |
(addr_hit[32] & (|(KMAC_PERMIT[32] & ~reg_be))) |
(addr_hit[33] & (|(KMAC_PERMIT[33] & ~reg_be))) |
(addr_hit[34] & (|(KMAC_PERMIT[34] & ~reg_be))) |
(addr_hit[35] & (|(KMAC_PERMIT[35] & ~reg_be))) |
(addr_hit[36] & (|(KMAC_PERMIT[36] & ~reg_be))) |
(addr_hit[37] & (|(KMAC_PERMIT[37] & ~reg_be))) |
(addr_hit[38] & (|(KMAC_PERMIT[38] & ~reg_be))) |
(addr_hit[39] & (|(KMAC_PERMIT[39] & ~reg_be))) |
(addr_hit[40] & (|(KMAC_PERMIT[40] & ~reg_be))) |
(addr_hit[41] & (|(KMAC_PERMIT[41] & ~reg_be))) |
(addr_hit[42] & (|(KMAC_PERMIT[42] & ~reg_be))) |
(addr_hit[43] & (|(KMAC_PERMIT[43] & ~reg_be))) |
(addr_hit[44] & (|(KMAC_PERMIT[44] & ~reg_be))) |
(addr_hit[45] & (|(KMAC_PERMIT[45] & ~reg_be))) |
(addr_hit[46] & (|(KMAC_PERMIT[46] & ~reg_be))) |
(addr_hit[47] & (|(KMAC_PERMIT[47] & ~reg_be))) |
(addr_hit[48] & (|(KMAC_PERMIT[48] & ~reg_be))) |
(addr_hit[49] & (|(KMAC_PERMIT[49] & ~reg_be))) |
(addr_hit[50] & (|(KMAC_PERMIT[50] & ~reg_be))) |
(addr_hit[51] & (|(KMAC_PERMIT[51] & ~reg_be))) |
(addr_hit[52] & (|(KMAC_PERMIT[52] & ~reg_be))) |
(addr_hit[53] & (|(KMAC_PERMIT[53] & ~reg_be))) |
(addr_hit[54] & (|(KMAC_PERMIT[54] & ~reg_be))) |
(addr_hit[55] & (|(KMAC_PERMIT[55] & ~reg_be))) |
(addr_hit[56] & (|(KMAC_PERMIT[56] & ~reg_be))) |
(addr_hit[57] & (|(KMAC_PERMIT[57] & ~reg_be))) |
(addr_hit[58] & (|(KMAC_PERMIT[58] & ~reg_be))) |
(addr_hit[59] & (|(KMAC_PERMIT[59] & ~reg_be))) |
(addr_hit[60] & (|(KMAC_PERMIT[60] & ~reg_be)))));
end
// Generate write-enables
assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
assign intr_state_kmac_done_wd = reg_wdata[0];
assign intr_state_fifo_empty_wd = reg_wdata[1];
assign intr_state_kmac_err_wd = reg_wdata[2];
assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
assign intr_enable_kmac_done_wd = reg_wdata[0];
assign intr_enable_fifo_empty_wd = reg_wdata[1];
assign intr_enable_kmac_err_wd = reg_wdata[2];
assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
assign intr_test_kmac_done_wd = reg_wdata[0];
assign intr_test_fifo_empty_wd = reg_wdata[1];
assign intr_test_kmac_err_wd = reg_wdata[2];
assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
assign alert_test_recov_operation_err_wd = reg_wdata[0];
assign alert_test_fatal_fault_err_wd = reg_wdata[1];
assign cfg_regwen_re = addr_hit[4] & reg_re & !reg_error;
assign cfg_shadowed_re = addr_hit[5] & reg_re & !reg_error;
assign cfg_shadowed_we = addr_hit[5] & reg_we & !reg_error;
assign cfg_shadowed_kmac_en_wd = reg_wdata[0];
assign cfg_shadowed_kstrength_wd = reg_wdata[3:1];
assign cfg_shadowed_mode_wd = reg_wdata[5:4];
assign cfg_shadowed_msg_endianness_wd = reg_wdata[8];
assign cfg_shadowed_state_endianness_wd = reg_wdata[9];
assign cfg_shadowed_sideload_wd = reg_wdata[12];
assign cfg_shadowed_entropy_mode_wd = reg_wdata[17:16];
assign cfg_shadowed_entropy_fast_process_wd = reg_wdata[19];
assign cfg_shadowed_msg_mask_wd = reg_wdata[20];
assign cfg_shadowed_entropy_ready_wd = reg_wdata[24];
assign cfg_shadowed_err_processed_wd = reg_wdata[25];
assign cfg_shadowed_en_unsupported_modestrength_wd = reg_wdata[26];
assign cmd_we = addr_hit[6] & reg_we & !reg_error;
assign cmd_cmd_wd = reg_wdata[5:0];
assign cmd_entropy_req_wd = reg_wdata[8];
assign cmd_hash_cnt_clr_wd = reg_wdata[9];
assign status_re = addr_hit[7] & reg_re & !reg_error;
assign entropy_period_we = addr_hit[8] & reg_we & !reg_error;
assign entropy_period_prescaler_wd = reg_wdata[9:0];
assign entropy_period_wait_timer_wd = reg_wdata[31:16];
assign entropy_refresh_threshold_shadowed_re = addr_hit[10] & reg_re & !reg_error;
assign entropy_refresh_threshold_shadowed_we = addr_hit[10] & reg_we & !reg_error;
assign entropy_refresh_threshold_shadowed_wd = reg_wdata[9:0];
assign entropy_seed_0_we = addr_hit[11] & reg_we & !reg_error;
assign entropy_seed_0_wd = reg_wdata[31:0];
assign entropy_seed_1_we = addr_hit[12] & reg_we & !reg_error;
assign entropy_seed_1_wd = reg_wdata[31:0];
assign entropy_seed_2_we = addr_hit[13] & reg_we & !reg_error;
assign entropy_seed_2_wd = reg_wdata[31:0];
assign entropy_seed_3_we = addr_hit[14] & reg_we & !reg_error;
assign entropy_seed_3_wd = reg_wdata[31:0];
assign entropy_seed_4_we = addr_hit[15] & reg_we & !reg_error;
assign entropy_seed_4_wd = reg_wdata[31:0];
assign key_share0_0_we = addr_hit[16] & reg_we & !reg_error;
assign key_share0_0_wd = reg_wdata[31:0];
assign key_share0_1_we = addr_hit[17] & reg_we & !reg_error;
assign key_share0_1_wd = reg_wdata[31:0];
assign key_share0_2_we = addr_hit[18] & reg_we & !reg_error;
assign key_share0_2_wd = reg_wdata[31:0];
assign key_share0_3_we = addr_hit[19] & reg_we & !reg_error;
assign key_share0_3_wd = reg_wdata[31:0];
assign key_share0_4_we = addr_hit[20] & reg_we & !reg_error;
assign key_share0_4_wd = reg_wdata[31:0];
assign key_share0_5_we = addr_hit[21] & reg_we & !reg_error;
assign key_share0_5_wd = reg_wdata[31:0];
assign key_share0_6_we = addr_hit[22] & reg_we & !reg_error;
assign key_share0_6_wd = reg_wdata[31:0];
assign key_share0_7_we = addr_hit[23] & reg_we & !reg_error;
assign key_share0_7_wd = reg_wdata[31:0];
assign key_share0_8_we = addr_hit[24] & reg_we & !reg_error;
assign key_share0_8_wd = reg_wdata[31:0];
assign key_share0_9_we = addr_hit[25] & reg_we & !reg_error;
assign key_share0_9_wd = reg_wdata[31:0];
assign key_share0_10_we = addr_hit[26] & reg_we & !reg_error;
assign key_share0_10_wd = reg_wdata[31:0];
assign key_share0_11_we = addr_hit[27] & reg_we & !reg_error;
assign key_share0_11_wd = reg_wdata[31:0];
assign key_share0_12_we = addr_hit[28] & reg_we & !reg_error;
assign key_share0_12_wd = reg_wdata[31:0];
assign key_share0_13_we = addr_hit[29] & reg_we & !reg_error;
assign key_share0_13_wd = reg_wdata[31:0];
assign key_share0_14_we = addr_hit[30] & reg_we & !reg_error;
assign key_share0_14_wd = reg_wdata[31:0];
assign key_share0_15_we = addr_hit[31] & reg_we & !reg_error;
assign key_share0_15_wd = reg_wdata[31:0];
assign key_share1_0_we = addr_hit[32] & reg_we & !reg_error;
assign key_share1_0_wd = reg_wdata[31:0];
assign key_share1_1_we = addr_hit[33] & reg_we & !reg_error;
assign key_share1_1_wd = reg_wdata[31:0];
assign key_share1_2_we = addr_hit[34] & reg_we & !reg_error;
assign key_share1_2_wd = reg_wdata[31:0];
assign key_share1_3_we = addr_hit[35] & reg_we & !reg_error;
assign key_share1_3_wd = reg_wdata[31:0];
assign key_share1_4_we = addr_hit[36] & reg_we & !reg_error;
assign key_share1_4_wd = reg_wdata[31:0];
assign key_share1_5_we = addr_hit[37] & reg_we & !reg_error;
assign key_share1_5_wd = reg_wdata[31:0];
assign key_share1_6_we = addr_hit[38] & reg_we & !reg_error;
assign key_share1_6_wd = reg_wdata[31:0];
assign key_share1_7_we = addr_hit[39] & reg_we & !reg_error;
assign key_share1_7_wd = reg_wdata[31:0];
assign key_share1_8_we = addr_hit[40] & reg_we & !reg_error;
assign key_share1_8_wd = reg_wdata[31:0];
assign key_share1_9_we = addr_hit[41] & reg_we & !reg_error;
assign key_share1_9_wd = reg_wdata[31:0];
assign key_share1_10_we = addr_hit[42] & reg_we & !reg_error;
assign key_share1_10_wd = reg_wdata[31:0];
assign key_share1_11_we = addr_hit[43] & reg_we & !reg_error;
assign key_share1_11_wd = reg_wdata[31:0];
assign key_share1_12_we = addr_hit[44] & reg_we & !reg_error;
assign key_share1_12_wd = reg_wdata[31:0];
assign key_share1_13_we = addr_hit[45] & reg_we & !reg_error;
assign key_share1_13_wd = reg_wdata[31:0];
assign key_share1_14_we = addr_hit[46] & reg_we & !reg_error;
assign key_share1_14_wd = reg_wdata[31:0];
assign key_share1_15_we = addr_hit[47] & reg_we & !reg_error;
assign key_share1_15_wd = reg_wdata[31:0];
assign key_len_we = addr_hit[48] & reg_we & !reg_error;
assign key_len_wd = reg_wdata[2:0];
assign prefix_0_we = addr_hit[49] & reg_we & !reg_error;
assign prefix_0_wd = reg_wdata[31:0];
assign prefix_1_we = addr_hit[50] & reg_we & !reg_error;
assign prefix_1_wd = reg_wdata[31:0];
assign prefix_2_we = addr_hit[51] & reg_we & !reg_error;
assign prefix_2_wd = reg_wdata[31:0];
assign prefix_3_we = addr_hit[52] & reg_we & !reg_error;
assign prefix_3_wd = reg_wdata[31:0];
assign prefix_4_we = addr_hit[53] & reg_we & !reg_error;
assign prefix_4_wd = reg_wdata[31:0];
assign prefix_5_we = addr_hit[54] & reg_we & !reg_error;
assign prefix_5_wd = reg_wdata[31:0];
assign prefix_6_we = addr_hit[55] & reg_we & !reg_error;
assign prefix_6_wd = reg_wdata[31:0];
assign prefix_7_we = addr_hit[56] & reg_we & !reg_error;
assign prefix_7_wd = reg_wdata[31:0];
assign prefix_8_we = addr_hit[57] & reg_we & !reg_error;
assign prefix_8_wd = reg_wdata[31:0];
assign prefix_9_we = addr_hit[58] & reg_we & !reg_error;
assign prefix_9_wd = reg_wdata[31:0];
assign prefix_10_we = addr_hit[59] & reg_we & !reg_error;
assign prefix_10_wd = reg_wdata[31:0];
// Assign write-enables to checker logic vector.
always_comb begin
reg_we_check = '0;
reg_we_check[0] = intr_state_we;
reg_we_check[1] = intr_enable_we;
reg_we_check[2] = intr_test_we;
reg_we_check[3] = alert_test_we;
reg_we_check[4] = 1'b0;
reg_we_check[5] = cfg_shadowed_gated_we;
reg_we_check[6] = cmd_we;
reg_we_check[7] = 1'b0;
reg_we_check[8] = entropy_period_gated_we;
reg_we_check[9] = 1'b0;
reg_we_check[10] = entropy_refresh_threshold_shadowed_gated_we;
reg_we_check[11] = entropy_seed_0_we;
reg_we_check[12] = entropy_seed_1_we;
reg_we_check[13] = entropy_seed_2_we;
reg_we_check[14] = entropy_seed_3_we;
reg_we_check[15] = entropy_seed_4_we;
reg_we_check[16] = key_share0_0_gated_we;
reg_we_check[17] = key_share0_1_gated_we;
reg_we_check[18] = key_share0_2_gated_we;
reg_we_check[19] = key_share0_3_gated_we;
reg_we_check[20] = key_share0_4_gated_we;
reg_we_check[21] = key_share0_5_gated_we;
reg_we_check[22] = key_share0_6_gated_we;
reg_we_check[23] = key_share0_7_gated_we;
reg_we_check[24] = key_share0_8_gated_we;
reg_we_check[25] = key_share0_9_gated_we;
reg_we_check[26] = key_share0_10_gated_we;
reg_we_check[27] = key_share0_11_gated_we;
reg_we_check[28] = key_share0_12_gated_we;
reg_we_check[29] = key_share0_13_gated_we;
reg_we_check[30] = key_share0_14_gated_we;
reg_we_check[31] = key_share0_15_gated_we;
reg_we_check[32] = key_share1_0_gated_we;
reg_we_check[33] = key_share1_1_gated_we;
reg_we_check[34] = key_share1_2_gated_we;
reg_we_check[35] = key_share1_3_gated_we;
reg_we_check[36] = key_share1_4_gated_we;
reg_we_check[37] = key_share1_5_gated_we;
reg_we_check[38] = key_share1_6_gated_we;
reg_we_check[39] = key_share1_7_gated_we;
reg_we_check[40] = key_share1_8_gated_we;
reg_we_check[41] = key_share1_9_gated_we;
reg_we_check[42] = key_share1_10_gated_we;
reg_we_check[43] = key_share1_11_gated_we;
reg_we_check[44] = key_share1_12_gated_we;
reg_we_check[45] = key_share1_13_gated_we;
reg_we_check[46] = key_share1_14_gated_we;
reg_we_check[47] = key_share1_15_gated_we;
reg_we_check[48] = key_len_gated_we;
reg_we_check[49] = prefix_0_gated_we;
reg_we_check[50] = prefix_1_gated_we;
reg_we_check[51] = prefix_2_gated_we;
reg_we_check[52] = prefix_3_gated_we;
reg_we_check[53] = prefix_4_gated_we;
reg_we_check[54] = prefix_5_gated_we;
reg_we_check[55] = prefix_6_gated_we;
reg_we_check[56] = prefix_7_gated_we;
reg_we_check[57] = prefix_8_gated_we;
reg_we_check[58] = prefix_9_gated_we;
reg_we_check[59] = prefix_10_gated_we;
reg_we_check[60] = 1'b0;
end
// Read data return
always_comb begin
reg_rdata_next = '0;
unique case (1'b1)
addr_hit[0]: begin
reg_rdata_next[0] = intr_state_kmac_done_qs;
reg_rdata_next[1] = intr_state_fifo_empty_qs;
reg_rdata_next[2] = intr_state_kmac_err_qs;
end
addr_hit[1]: begin
reg_rdata_next[0] = intr_enable_kmac_done_qs;
reg_rdata_next[1] = intr_enable_fifo_empty_qs;
reg_rdata_next[2] = intr_enable_kmac_err_qs;
end
addr_hit[2]: begin
reg_rdata_next[0] = '0;
reg_rdata_next[1] = '0;
reg_rdata_next[2] = '0;
end
addr_hit[3]: begin
reg_rdata_next[0] = '0;
reg_rdata_next[1] = '0;
end
addr_hit[4]: begin
reg_rdata_next[0] = cfg_regwen_qs;
end
addr_hit[5]: begin
reg_rdata_next[0] = cfg_shadowed_kmac_en_qs;
reg_rdata_next[3:1] = cfg_shadowed_kstrength_qs;
reg_rdata_next[5:4] = cfg_shadowed_mode_qs;
reg_rdata_next[8] = cfg_shadowed_msg_endianness_qs;
reg_rdata_next[9] = cfg_shadowed_state_endianness_qs;
reg_rdata_next[12] = cfg_shadowed_sideload_qs;
reg_rdata_next[17:16] = cfg_shadowed_entropy_mode_qs;
reg_rdata_next[19] = cfg_shadowed_entropy_fast_process_qs;
reg_rdata_next[20] = cfg_shadowed_msg_mask_qs;
reg_rdata_next[24] = cfg_shadowed_entropy_ready_qs;
reg_rdata_next[25] = cfg_shadowed_err_processed_qs;
reg_rdata_next[26] = cfg_shadowed_en_unsupported_modestrength_qs;
end
addr_hit[6]: begin
reg_rdata_next[5:0] = '0;
reg_rdata_next[8] = '0;
reg_rdata_next[9] = '0;
end
addr_hit[7]: begin
reg_rdata_next[0] = status_sha3_idle_qs;
reg_rdata_next[1] = status_sha3_absorb_qs;
reg_rdata_next[2] = status_sha3_squeeze_qs;
reg_rdata_next[12:8] = status_fifo_depth_qs;
reg_rdata_next[14] = status_fifo_empty_qs;
reg_rdata_next[15] = status_fifo_full_qs;
reg_rdata_next[16] = status_alert_fatal_fault_qs;
reg_rdata_next[17] = status_alert_recov_ctrl_update_err_qs;
end
addr_hit[8]: begin
reg_rdata_next[9:0] = entropy_period_prescaler_qs;
reg_rdata_next[31:16] = entropy_period_wait_timer_qs;
end
addr_hit[9]: begin
reg_rdata_next[9:0] = entropy_refresh_hash_cnt_qs;
end
addr_hit[10]: begin
reg_rdata_next[9:0] = entropy_refresh_threshold_shadowed_qs;
end
addr_hit[11]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[12]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[13]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[14]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[15]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[16]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[17]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[18]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[19]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[20]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[21]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[22]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[23]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[24]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[25]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[26]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[27]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[28]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[29]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[30]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[31]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[32]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[33]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[34]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[35]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[36]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[37]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[38]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[39]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[40]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[41]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[42]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[43]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[44]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[45]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[46]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[47]: begin
reg_rdata_next[31:0] = '0;
end
addr_hit[48]: begin
reg_rdata_next[2:0] = '0;
end
addr_hit[49]: begin
reg_rdata_next[31:0] = prefix_0_qs;
end
addr_hit[50]: begin
reg_rdata_next[31:0] = prefix_1_qs;
end
addr_hit[51]: begin
reg_rdata_next[31:0] = prefix_2_qs;
end
addr_hit[52]: begin
reg_rdata_next[31:0] = prefix_3_qs;
end
addr_hit[53]: begin
reg_rdata_next[31:0] = prefix_4_qs;
end
addr_hit[54]: begin
reg_rdata_next[31:0] = prefix_5_qs;
end
addr_hit[55]: begin
reg_rdata_next[31:0] = prefix_6_qs;
end
addr_hit[56]: begin
reg_rdata_next[31:0] = prefix_7_qs;
end
addr_hit[57]: begin
reg_rdata_next[31:0] = prefix_8_qs;
end
addr_hit[58]: begin
reg_rdata_next[31:0] = prefix_9_qs;
end
addr_hit[59]: begin
reg_rdata_next[31:0] = prefix_10_qs;
end
addr_hit[60]: begin
reg_rdata_next[31:0] = err_code_qs;
end
default: begin
reg_rdata_next = '1;
end
endcase
end
// shadow busy
logic shadow_busy;
logic rst_done;
logic shadow_rst_done;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rst_done <= '0;
end else begin
rst_done <= 1'b1;
end
end
always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin
if (!rst_shadowed_ni) begin
shadow_rst_done <= '0;
end else begin
shadow_rst_done <= 1'b1;
end
end
// both shadow and normal resets have been released
assign shadow_busy = ~(rst_done & shadow_rst_done);
// Collect up storage and update errors
assign shadowed_storage_err_o = |{
cfg_shadowed_kmac_en_storage_err,
cfg_shadowed_kstrength_storage_err,
cfg_shadowed_mode_storage_err,
cfg_shadowed_msg_endianness_storage_err,
cfg_shadowed_state_endianness_storage_err,
cfg_shadowed_sideload_storage_err,
cfg_shadowed_entropy_mode_storage_err,
cfg_shadowed_entropy_fast_process_storage_err,
cfg_shadowed_msg_mask_storage_err,
cfg_shadowed_entropy_ready_storage_err,
cfg_shadowed_err_processed_storage_err,
cfg_shadowed_en_unsupported_modestrength_storage_err,
entropy_refresh_threshold_shadowed_storage_err
};
assign shadowed_update_err_o = |{
cfg_shadowed_kmac_en_update_err,
cfg_shadowed_kstrength_update_err,
cfg_shadowed_mode_update_err,
cfg_shadowed_msg_endianness_update_err,
cfg_shadowed_state_endianness_update_err,
cfg_shadowed_sideload_update_err,
cfg_shadowed_entropy_mode_update_err,
cfg_shadowed_entropy_fast_process_update_err,
cfg_shadowed_msg_mask_update_err,
cfg_shadowed_entropy_ready_update_err,
cfg_shadowed_err_processed_update_err,
cfg_shadowed_en_unsupported_modestrength_update_err,
entropy_refresh_threshold_shadowed_update_err
};
// register busy
assign reg_busy = shadow_busy;
// Unused signal tieoff
// wdata / byte enable are not always fully used
// add a blanket unused statement to handle lint waivers
logic unused_wdata;
logic unused_be;
assign unused_wdata = ^reg_wdata;
assign unused_be = ^reg_be;
// Assertions for Register Interface
`ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
`ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
`ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
`ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
// this is formulated as an assumption such that the FPV testbenches do disprove this
// property by mistake
//`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
endmodule