blob: 76282c3aff0a952254490e239318ed7fc5b1774c [file] [log] [blame]
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Interface configuration for JTAG on the Nexys Video board through the
# FT2232H chip. This connection is labeled DTPI/DSPI in the board schematics.
# adapter speed
# Up to 30 MHz are supported by the FT2232H
adapter_khz 30000
adapter driver ftdi
transport select jtag
ftdi_vid_pid 0x0403 0x6010
# Not really required, but makes communication a bit more robust
ftdi_tdo_sample_edge falling
# Use Channel A (0), channel B (1) is taken by Xilinx JTAG
ftdi_channel 0
# FT2232H pin configuration
#
# Documentation:
# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html#Interface-Drivers
#
# Our configuration:
#
# Bit MPSSE FT2232 JTAG Type RstVal Description
# ----------------------------------------------------------------------
# Bit0 TCK ADBUS0 TCK Out 0 Clock Signal Output
# Bit1 TDI ADBUS1 TDI Out 0 Serial Data Out
# Bit2 TDO ADBUS2 TDO In 0 Serial Data In
# Bit3 TMS ADBUS3 TMS Out 1 Select Signal Out
# Bit4 GPIOL0 ADBUS4 nTRST Out 1 General Purpose I/O
# Bit5 GPIOL1 ADBUS5 nSRST Out 1 General Purpose I/O
# Bit6 GPIOL2 ADBUS6 0 Out 0 General Purpose I/O
# Bit7 GPIOL3 ADBUS7 0 Out 0 General Purpose I/O
#
# Bit6 GPIOL2 is used to select between JTAG=1 and SPI=0 and controls
# the I/O MUX inside the earlgrey_nexsysvideo. Static so it is only
# mentioned in the init command below (makes it output value 1)
#
# Bit7 GPIOL3 is used to enable boot rom boot strap
#
# This corresponds to the following reset values (first number), and
# in/out layout (second number):
ftdi_layout_init 0x0078 0x00fb
# TAP reset (nTRST)
ftdi_layout_signal nTRST -ndata 0x0010
# System Reset (nSRST)
ftdi_layout_signal nSRST -ndata 0x0020
# FT2232 doesn't support open drain GPIO for reset pins
reset_config srst_push_pull trst_push_pull