| commit | df63ec89b6cd02bb00fdf133cc5ef8e989c6585a | [log] [tgz] |
|---|---|---|
| author | Eunchan Kim <eunchan@opentitan.org> | Wed May 26 00:37:34 2021 -0700 |
| committer | Eunchan Kim <eunchan@opentitan.org> | Wed May 26 15:34:12 2021 -0700 |
| tree | fecc72d7ccf825a46cdc87ace48c3c6a478e0c6c | |
| parent | c92fa305b5443d2f2f51764d41f8d00b39e3b13d [diff] |
[rv_plic] fix Src width mismatch In the commit 88a861588795ccd2c43603096cd007600412ec2f it removes the necessity of adding position 0 of the interrupt source, which is reserved as 'no interrupt'. The interrupt source [0] is tied outside of the rv_plic by the topgen tool. @WonHoYoo reported the DC synthesis error if the number of source is set to the power of two ( issue #6718 ). While revising the design in the above commit, `rv_plic_target` was omiited by mistake. This commit addresses the issue and reduces the `SrcWidth` to `$clot2(NumSrc)`. Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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