tree fecc72d7ccf825a46cdc87ace48c3c6a478e0c6c
parent c92fa305b5443d2f2f51764d41f8d00b39e3b13d
author Eunchan Kim <eunchan@opentitan.org> 1622014654 -0700
committer Eunchan Kim <eunchan@opentitan.org> 1622068452 -0700
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[rv_plic] fix Src width mismatch

In the commit 88a861588795ccd2c43603096cd007600412ec2f it removes the
necessity of adding position 0 of the interrupt source, which is
reserved as 'no interrupt'. The interrupt source [0] is tied outside of
the rv_plic by the topgen tool.

@WonHoYoo reported the DC synthesis error if the number of source is set
to the power of two ( issue #6718 ).

While revising the design in the above commit, `rv_plic_target` was
omiited by mistake. This commit addresses the issue and reduces the
`SrcWidth` to `$clot2(NumSrc)`.

Signed-off-by: Eunchan Kim <eunchan@opentitan.org>