| From 2d91bb21434ee8b66eed93e5a9c52b29defdc525 Mon Sep 17 00:00:00 2001 |
| From: Michael Schaffner <msf@google.com> |
| Date: Thu, 17 Oct 2019 18:07:55 -0700 |
| Subject: [PATCH 5/9] [lint/cleanup] Simplify some statements |
| |
| --- |
| src/dm_csrs.sv | 17 ++++------------- |
| src/dm_mem.sv | 34 ++++++++++++++++++---------------- |
| src/dm_sba.sv | 2 +- |
| src/dm_top.sv | 38 +++++++++++++++++++------------------- |
| 4 files changed, 42 insertions(+), 49 deletions(-) |
| |
| diff --git a/src/dm_csrs.sv b/src/dm_csrs.sv |
| index ffa45ba..a6b1c6d 100644 |
| --- a/src/dm_csrs.sv |
| +++ b/src/dm_csrs.sv |
| @@ -194,8 +194,8 @@ module dm_csrs #( |
| |
| // as soon as we are out of the legal Hart region tell the debugger |
| // that there are only non-existent harts |
| - dmstatus.allnonexistent = (hartsel_o > (NrHarts - 1)) ? 1'b1 : 1'b0; |
| - dmstatus.anynonexistent = (hartsel_o > (NrHarts - 1)) ? 1'b1 : 1'b0; |
| + dmstatus.allnonexistent = logic'(hartsel_o > (NrHarts - 1)); |
| + dmstatus.anynonexistent = logic'(hartsel_o > (NrHarts - 1)); |
| |
| // We are not allowed to be in multiple states at once. This is a to |
| // make the running/halted and unavailable states exclusive. |
| @@ -534,7 +534,9 @@ module dm_csrs #( |
| sbcs_q <= '0; |
| sbaddr_q <= '0; |
| sbdata_q <= '0; |
| + havereset_q <= '1; |
| end else begin |
| + havereset_q <= SelectableHarts & havereset_d; |
| // synchronous re-set of debug module, active-low, except for dmactive |
| if (!dmcontrol_q.dmactive) begin |
| dmcontrol_q.haltreq <= '0; |
| @@ -574,17 +576,6 @@ module dm_csrs #( |
| end |
| end |
| |
| - |
| - for (genvar k = 0; k < NrHarts; k++) begin : gen_havereset |
| - always_ff @(posedge clk_i or negedge rst_ni) begin |
| - if (!rst_ni) begin |
| - havereset_q[k] <= 1'b1; |
| - end else begin |
| - havereset_q[k] <= SelectableHarts[k] ? havereset_d[k] : 1'b0; |
| - end |
| - end |
| - end |
| - |
| /////////////////////////////////////////////////////// |
| // assertions |
| /////////////////////////////////////////////////////// |
| diff --git a/src/dm_mem.sv b/src/dm_mem.sv |
| index 9de08d4..bba5234 100644 |
| --- a/src/dm_mem.sv |
| +++ b/src/dm_mem.sv |
| @@ -180,17 +180,22 @@ module dm_mem #( |
| end |
| end |
| |
| + // word mux for 32bit and 64bit buses |
| + logic [63:0] word_mux; |
| + assign word_mux = (fwd_rom_q) ? rom_rdata : rdata_q; |
| + |
| + if (BusWidth == 64) begin : gen_word_mux64 |
| + assign rdata_o = word_mux; |
| + end else begin : gen_word_mux32 |
| + assign rdata_o = (word_enable32_q) ? word_mux[32 +: 32] : word_mux[0 +: 32]; |
| + end |
| + |
| // read/write logic |
| always_comb begin : p_rw_logic |
| automatic logic [63:0] data_bits; |
| |
| halted_d = halted_q; |
| resuming_d = resuming_q; |
| - rdata_o = (BusWidth == 64) ? |
| - (fwd_rom_q ? rom_rdata : rdata_q) : |
| - (word_enable32_q ? |
| - (fwd_rom_q ? rom_rdata[63:32] : rdata_q[63:32]) : |
| - (fwd_rom_q ? rom_rdata[31: 0] : rdata_q[31: 0])); |
| rdata_d = rdata_q; |
| // convert the data in bits representation |
| data_bits = data_i; |
| @@ -438,8 +443,7 @@ module dm_mem #( |
| |
| // ROM starts at the HaltAddress of the core e.g.: it immediately jumps to |
| // the ROM base address |
| - assign fwd_rom_d = (addr_i[DbgAddressBits-1:0] >= dm::HaltAddress[DbgAddressBits-1:0]) ? |
| - 1'b1 : 1'b0; |
| + assign fwd_rom_d = logic'(addr_i[DbgAddressBits-1:0] >= dm::HaltAddress[DbgAddressBits-1:0]); |
| |
| always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs |
| if (!rst_ni) begin |
| @@ -455,15 +459,13 @@ module dm_mem #( |
| end |
| end |
| |
| - for (genvar k = 0; k < NrHarts; k++) begin : gen_halted |
| - always_ff @(posedge clk_i or negedge rst_ni) begin |
| - if (!rst_ni) begin |
| - halted_q[k] <= 1'b0; |
| - resuming_q[k] <= 1'b0; |
| - end else begin |
| - halted_q[k] <= SelectableHarts[k] ? halted_d[k] : 1'b0; |
| - resuming_q[k] <= SelectableHarts[k] ? resuming_d[k] : 1'b0; |
| - end |
| + always_ff @(posedge clk_i or negedge rst_ni) begin |
| + if (!rst_ni) begin |
| + halted_q <= 1'b0; |
| + resuming_q <= 1'b0; |
| + end else begin |
| + halted_q <= SelectableHarts & halted_d; |
| + resuming_q <= SelectableHarts & resuming_d; |
| end |
| end |
| |
| diff --git a/src/dm_sba.sv b/src/dm_sba.sv |
| index c143ba1..9fb445e 100644 |
| --- a/src/dm_sba.sv |
| +++ b/src/dm_sba.sv |
| @@ -61,7 +61,7 @@ module dm_sba #( |
| logic we; |
| logic [BusWidth/8-1:0] be; |
| |
| - assign sbbusy_o = (state_q != Idle) ? 1'b1 : 1'b0; |
| + assign sbbusy_o = logic'(state_q != Idle); |
| |
| always_comb begin : p_fsm |
| req = 1'b0; |
| diff --git a/src/dm_top.sv b/src/dm_top.sv |
| index dd06a23..e375101 100644 |
| --- a/src/dm_top.sv |
| +++ b/src/dm_top.sv |
| @@ -101,9 +101,9 @@ module dm_top #( |
| .BusWidth(BusWidth), |
| .SelectableHarts(SelectableHarts) |
| ) i_dm_csrs ( |
| - .clk_i ( clk_i ), |
| - .rst_ni ( rst_ni ), |
| - .testmode_i ( testmode_i ), |
| + .clk_i, |
| + .rst_ni, |
| + .testmode_i, |
| .dmi_rst_ni, |
| .dmi_req_valid_i, |
| .dmi_req_ready_o, |
| @@ -111,10 +111,10 @@ module dm_top #( |
| .dmi_resp_valid_o, |
| .dmi_resp_ready_i, |
| .dmi_resp_o, |
| - .ndmreset_o ( ndmreset_o ), |
| - .dmactive_o ( dmactive_o ), |
| + .ndmreset_o, |
| + .dmactive_o, |
| .hartsel_o ( hartsel ), |
| - .hartinfo_i ( hartinfo_i ), |
| + .hartinfo_i, |
| .halted_i ( halted ), |
| .unavailable_i, |
| .resumeack_i ( resumeack ), |
| @@ -150,18 +150,18 @@ module dm_top #( |
| dm_sba #( |
| .BusWidth(BusWidth) |
| ) i_dm_sba ( |
| - .clk_i ( clk_i ), |
| - .rst_ni ( rst_ni ), |
| + .clk_i, |
| + .rst_ni, |
| .dmactive_i ( dmactive_o ), |
| |
| - .master_req_o ( master_req_o ), |
| - .master_add_o ( master_add_o ), |
| - .master_we_o ( master_we_o ), |
| - .master_wdata_o ( master_wdata_o ), |
| - .master_be_o ( master_be_o ), |
| - .master_gnt_i ( master_gnt_i ), |
| - .master_r_valid_i ( master_r_valid_i ), |
| - .master_r_rdata_i ( master_r_rdata_i ), |
| + .master_req_o, |
| + .master_add_o, |
| + .master_we_o, |
| + .master_wdata_o, |
| + .master_be_o, |
| + .master_gnt_i, |
| + .master_r_valid_i, |
| + .master_r_rdata_i, |
| |
| .sbaddress_i ( sbaddress_csrs_sba ), |
| .sbaddress_o ( sbaddress_sba_csrs ), |
| @@ -185,9 +185,9 @@ module dm_top #( |
| .BusWidth(BusWidth), |
| .SelectableHarts(SelectableHarts) |
| ) i_dm_mem ( |
| - .clk_i ( clk_i ), |
| - .rst_ni ( rst_ni ), |
| - .debug_req_o ( debug_req_o ), |
| + .clk_i, |
| + .rst_ni, |
| + .debug_req_o, |
| .hartsel_i ( hartsel ), |
| .haltreq_i ( haltreq ), |
| .resumereq_i ( resumereq ), |
| -- |
| 2.24.0.rc0.303.g954a862665-goog |
| |
