hw/top_englishbreakfast/data/xbar_main.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{ name: "main",
  type: "xbar",
  clock_primary: "clk_main_i", // Main clock, used in sockets
  other_clock_list: [ "clk_fixed_i" ] // Secondary clocks used by specific nodes
  reset_primary: "rst_main_ni", // Main reset, used in sockets
  other_reset_list: [ "rst_fixed_ni" ] // Secondary clocks used by specific nodes

  nodes: [
    { name:  "rv_core_ibex.corei",
      type:  "host",
      clock: "clk_main_i",
      reset: "rst_main_ni",
      pipeline: false

    },
    { name:  "rv_core_ibex.cored",
      type:  "host",
      clock: "clk_main_i",
      reset: "rst_main_ni",
      pipeline: false
    },
    { name:      "rv_dm.regs",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      req_fifo_pass: true,
      rsp_fifo_pass: false,
    },
    { name:      "rv_dm.mem",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      req_fifo_pass: true,
      rsp_fifo_pass: false,
    },
    { name:      "rom_ctrl.rom",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      req_fifo_pass: true,
      rsp_fifo_pass: false,
    },
    { name:      "rom_ctrl.regs",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      req_fifo_pass: true,
      rsp_fifo_pass: false,
    },
    { name:      "peri",
      type:      "device",
      clock:     "clk_fixed_i",
      reset:     "rst_fixed_ni",
      req_fifo_pass: true,
      rsp_fifo_pass: false,
    },
    { name:      "flash_ctrl.core",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      req_fifo_pass: true,
      rsp_fifo_pass: false,
    },
    { name:      "flash_ctrl.prim",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      req_fifo_pass: true,
      rsp_fifo_pass: false,
    },
    { name:      "flash_ctrl.mem",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      req_fifo_pass: true,
      rsp_fifo_pass: false,
    },
    { name:      "hmac",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      req_fifo_pass: true,
      rsp_fifo_pass: false,
    },
    { name:      "aes",
      type:      "device",
      clock:     "clk_main_i"
      reset:     "rst_main_ni"
      req_fifo_pass: true,
      rsp_fifo_pass: false,
    },
    { name:      "rv_plic",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      inst_type: "rv_plic",
      req_fifo_pass: true,
      rsp_fifo_pass: false,
    },
    { name:      "rv_core_ibex.cfg",
      type:      "device",
      clock:     "clk_main_i"
      reset:     "rst_main_ni"
      req_fifo_pass: true,
      rsp_fifo_pass: false,
    },
    { name:      "sram_ctrl_main.regs",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      pipeline: false
    },
    { name:      "sram_ctrl_main.ram",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      pipeline: false
    },
  ],
  connections: {
    rv_core_ibex.corei:  ["rom_ctrl.rom", "rv_dm.mem", "sram_ctrl_main.ram", "flash_ctrl.mem"],
    rv_core_ibex.cored:  [
      "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.mem", "rv_dm.regs",
      "sram_ctrl_main.ram", "flash_ctrl.mem", "peri", "flash_ctrl.core", "flash_ctrl.prim",
      "aes", "hmac",
      "rv_plic", "sram_ctrl_main.ram", "sram_ctrl_main.regs",
      "rv_core_ibex.cfg"
    ],
  },
}