hw/ip/usbdev/rtl/usbdev_reg_top.sv

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `reggen`

`include "prim_assert.sv"

module usbdev_reg_top (
  input clk_i,
  input rst_ni,
  input clk_aon_i,
  input rst_aon_ni,
  input  tlul_pkg::tl_h2d_t tl_i,
  output tlul_pkg::tl_d2h_t tl_o,

  // Output port for window
  output tlul_pkg::tl_h2d_t tl_win_o,
  input  tlul_pkg::tl_d2h_t tl_win_i,

  // To HW
  output usbdev_reg_pkg::usbdev_reg2hw_t reg2hw, // Write
  input  usbdev_reg_pkg::usbdev_hw2reg_t hw2reg, // Read

  // Integrity check errors
  output logic intg_err_o,

  // Config
  input devmode_i // If 1, explicit error return for unmapped register access
);

  import usbdev_reg_pkg::* ;

  localparam int AW = 12;
  localparam int DW = 32;
  localparam int DBW = DW/8;                    // Byte Width

  // register signals
  logic           reg_we;
  logic           reg_re;
  logic [AW-1:0]  reg_addr;
  logic [DW-1:0]  reg_wdata;
  logic [DBW-1:0] reg_be;
  logic [DW-1:0]  reg_rdata;
  logic           reg_error;

  logic          addrmiss, wr_err;

  logic [DW-1:0] reg_rdata_next;
  logic reg_busy;

  tlul_pkg::tl_h2d_t tl_reg_h2d;
  tlul_pkg::tl_d2h_t tl_reg_d2h;


  // incoming payload check
  logic intg_err;
  tlul_cmd_intg_chk u_chk (
    .tl_i(tl_i),
    .err_o(intg_err)
  );

  // also check for spurious write enables
  logic reg_we_err;
  logic [35:0] reg_we_check;
  prim_reg_we_check #(
    .OneHotWidth(36)
  ) u_prim_reg_we_check (
    .clk_i(clk_i),
    .rst_ni(rst_ni),
    .oh_i  (reg_we_check),
    .en_i  (reg_we && !addrmiss),
    .err_o (reg_we_err)
  );

  logic err_q;
  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      err_q <= '0;
    end else if (intg_err || reg_we_err) begin
      err_q <= 1'b1;
    end
  end

  // integrity error output is permanent and should be used for alert generation
  // register errors are transactional
  assign intg_err_o = err_q | intg_err | reg_we_err;

  // outgoing integrity generation
  tlul_pkg::tl_d2h_t tl_o_pre;
  tlul_rsp_intg_gen #(
    .EnableRspIntgGen(1),
    .EnableDataIntgGen(1)
  ) u_rsp_intg_gen (
    .tl_i(tl_o_pre),
    .tl_o(tl_o)
  );

  tlul_pkg::tl_h2d_t tl_socket_h2d [2];
  tlul_pkg::tl_d2h_t tl_socket_d2h [2];

  logic [0:0] reg_steer;

  // socket_1n connection
  assign tl_reg_h2d = tl_socket_h2d[1];
  assign tl_socket_d2h[1] = tl_reg_d2h;

  assign tl_win_o = tl_socket_h2d[0];
  assign tl_socket_d2h[0] = tl_win_i;

  // Create Socket_1n
  tlul_socket_1n #(
    .N            (2),
    .HReqPass     (1'b1),
    .HRspPass     (1'b1),
    .DReqPass     ({2{1'b1}}),
    .DRspPass     ({2{1'b1}}),
    .HReqDepth    (4'h0),
    .HRspDepth    (4'h0),
    .DReqDepth    ({2{4'h0}}),
    .DRspDepth    ({2{4'h0}}),
    .ExplicitErrs (1'b0)
  ) u_socket (
    .clk_i  (clk_i),
    .rst_ni (rst_ni),
    .tl_h_i (tl_i),
    .tl_h_o (tl_o_pre),
    .tl_d_o (tl_socket_h2d),
    .tl_d_i (tl_socket_d2h),
    .dev_select_i (reg_steer)
  );

  // Create steering logic
  always_comb begin
    reg_steer =
        tl_i.a_address[AW-1:0] inside {[2048:4095]} ? 1'd0 :
        // Default set to register
        1'd1;

    // Override this in case of an integrity error
    if (intg_err) begin
      reg_steer = 1'd1;
    end
  end

  tlul_adapter_reg #(
    .RegAw(AW),
    .RegDw(DW),
    .EnableDataIntgGen(0)
  ) u_reg_if (
    .clk_i  (clk_i),
    .rst_ni (rst_ni),

    .tl_i (tl_reg_h2d),
    .tl_o (tl_reg_d2h),

    .en_ifetch_i(prim_mubi_pkg::MuBi4False),
    .intg_error_o(),

    .we_o    (reg_we),
    .re_o    (reg_re),
    .addr_o  (reg_addr),
    .wdata_o (reg_wdata),
    .be_o    (reg_be),
    .busy_i  (reg_busy),
    .rdata_i (reg_rdata),
    .error_i (reg_error)
  );

  // cdc oversampling signals

  assign reg_rdata = reg_rdata_next ;
  assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;

  // Define SW related signals
  // Format: <reg>_<field>_{wd|we|qs}
  //        or <reg>_{wd|we|qs} if field == 1 or 0
  logic intr_state_we;
  logic intr_state_pkt_received_qs;
  logic intr_state_pkt_received_wd;
  logic intr_state_pkt_sent_qs;
  logic intr_state_pkt_sent_wd;
  logic intr_state_disconnected_qs;
  logic intr_state_disconnected_wd;
  logic intr_state_host_lost_qs;
  logic intr_state_host_lost_wd;
  logic intr_state_link_reset_qs;
  logic intr_state_link_reset_wd;
  logic intr_state_link_suspend_qs;
  logic intr_state_link_suspend_wd;
  logic intr_state_link_resume_qs;
  logic intr_state_link_resume_wd;
  logic intr_state_av_empty_qs;
  logic intr_state_av_empty_wd;
  logic intr_state_rx_full_qs;
  logic intr_state_rx_full_wd;
  logic intr_state_av_overflow_qs;
  logic intr_state_av_overflow_wd;
  logic intr_state_link_in_err_qs;
  logic intr_state_link_in_err_wd;
  logic intr_state_rx_crc_err_qs;
  logic intr_state_rx_crc_err_wd;
  logic intr_state_rx_pid_err_qs;
  logic intr_state_rx_pid_err_wd;
  logic intr_state_rx_bitstuff_err_qs;
  logic intr_state_rx_bitstuff_err_wd;
  logic intr_state_frame_qs;
  logic intr_state_frame_wd;
  logic intr_state_powered_qs;
  logic intr_state_powered_wd;
  logic intr_state_link_out_err_qs;
  logic intr_state_link_out_err_wd;
  logic intr_enable_we;
  logic intr_enable_pkt_received_qs;
  logic intr_enable_pkt_received_wd;
  logic intr_enable_pkt_sent_qs;
  logic intr_enable_pkt_sent_wd;
  logic intr_enable_disconnected_qs;
  logic intr_enable_disconnected_wd;
  logic intr_enable_host_lost_qs;
  logic intr_enable_host_lost_wd;
  logic intr_enable_link_reset_qs;
  logic intr_enable_link_reset_wd;
  logic intr_enable_link_suspend_qs;
  logic intr_enable_link_suspend_wd;
  logic intr_enable_link_resume_qs;
  logic intr_enable_link_resume_wd;
  logic intr_enable_av_empty_qs;
  logic intr_enable_av_empty_wd;
  logic intr_enable_rx_full_qs;
  logic intr_enable_rx_full_wd;
  logic intr_enable_av_overflow_qs;
  logic intr_enable_av_overflow_wd;
  logic intr_enable_link_in_err_qs;
  logic intr_enable_link_in_err_wd;
  logic intr_enable_rx_crc_err_qs;
  logic intr_enable_rx_crc_err_wd;
  logic intr_enable_rx_pid_err_qs;
  logic intr_enable_rx_pid_err_wd;
  logic intr_enable_rx_bitstuff_err_qs;
  logic intr_enable_rx_bitstuff_err_wd;
  logic intr_enable_frame_qs;
  logic intr_enable_frame_wd;
  logic intr_enable_powered_qs;
  logic intr_enable_powered_wd;
  logic intr_enable_link_out_err_qs;
  logic intr_enable_link_out_err_wd;
  logic intr_test_we;
  logic intr_test_pkt_received_wd;
  logic intr_test_pkt_sent_wd;
  logic intr_test_disconnected_wd;
  logic intr_test_host_lost_wd;
  logic intr_test_link_reset_wd;
  logic intr_test_link_suspend_wd;
  logic intr_test_link_resume_wd;
  logic intr_test_av_empty_wd;
  logic intr_test_rx_full_wd;
  logic intr_test_av_overflow_wd;
  logic intr_test_link_in_err_wd;
  logic intr_test_rx_crc_err_wd;
  logic intr_test_rx_pid_err_wd;
  logic intr_test_rx_bitstuff_err_wd;
  logic intr_test_frame_wd;
  logic intr_test_powered_wd;
  logic intr_test_link_out_err_wd;
  logic alert_test_we;
  logic alert_test_wd;
  logic usbctrl_we;
  logic usbctrl_enable_qs;
  logic usbctrl_enable_wd;
  logic usbctrl_resume_link_active_wd;
  logic [6:0] usbctrl_device_address_qs;
  logic [6:0] usbctrl_device_address_wd;
  logic ep_out_enable_we;
  logic ep_out_enable_enable_0_qs;
  logic ep_out_enable_enable_0_wd;
  logic ep_out_enable_enable_1_qs;
  logic ep_out_enable_enable_1_wd;
  logic ep_out_enable_enable_2_qs;
  logic ep_out_enable_enable_2_wd;
  logic ep_out_enable_enable_3_qs;
  logic ep_out_enable_enable_3_wd;
  logic ep_out_enable_enable_4_qs;
  logic ep_out_enable_enable_4_wd;
  logic ep_out_enable_enable_5_qs;
  logic ep_out_enable_enable_5_wd;
  logic ep_out_enable_enable_6_qs;
  logic ep_out_enable_enable_6_wd;
  logic ep_out_enable_enable_7_qs;
  logic ep_out_enable_enable_7_wd;
  logic ep_out_enable_enable_8_qs;
  logic ep_out_enable_enable_8_wd;
  logic ep_out_enable_enable_9_qs;
  logic ep_out_enable_enable_9_wd;
  logic ep_out_enable_enable_10_qs;
  logic ep_out_enable_enable_10_wd;
  logic ep_out_enable_enable_11_qs;
  logic ep_out_enable_enable_11_wd;
  logic ep_in_enable_we;
  logic ep_in_enable_enable_0_qs;
  logic ep_in_enable_enable_0_wd;
  logic ep_in_enable_enable_1_qs;
  logic ep_in_enable_enable_1_wd;
  logic ep_in_enable_enable_2_qs;
  logic ep_in_enable_enable_2_wd;
  logic ep_in_enable_enable_3_qs;
  logic ep_in_enable_enable_3_wd;
  logic ep_in_enable_enable_4_qs;
  logic ep_in_enable_enable_4_wd;
  logic ep_in_enable_enable_5_qs;
  logic ep_in_enable_enable_5_wd;
  logic ep_in_enable_enable_6_qs;
  logic ep_in_enable_enable_6_wd;
  logic ep_in_enable_enable_7_qs;
  logic ep_in_enable_enable_7_wd;
  logic ep_in_enable_enable_8_qs;
  logic ep_in_enable_enable_8_wd;
  logic ep_in_enable_enable_9_qs;
  logic ep_in_enable_enable_9_wd;
  logic ep_in_enable_enable_10_qs;
  logic ep_in_enable_enable_10_wd;
  logic ep_in_enable_enable_11_qs;
  logic ep_in_enable_enable_11_wd;
  logic usbstat_re;
  logic [10:0] usbstat_frame_qs;
  logic usbstat_host_lost_qs;
  logic [2:0] usbstat_link_state_qs;
  logic usbstat_sense_qs;
  logic [2:0] usbstat_av_depth_qs;
  logic usbstat_av_full_qs;
  logic [2:0] usbstat_rx_depth_qs;
  logic usbstat_rx_empty_qs;
  logic avbuffer_we;
  logic [4:0] avbuffer_wd;
  logic rxfifo_re;
  logic [4:0] rxfifo_buffer_qs;
  logic [6:0] rxfifo_size_qs;
  logic rxfifo_setup_qs;
  logic [3:0] rxfifo_ep_qs;
  logic rxenable_setup_we;
  logic rxenable_setup_setup_0_qs;
  logic rxenable_setup_setup_0_wd;
  logic rxenable_setup_setup_1_qs;
  logic rxenable_setup_setup_1_wd;
  logic rxenable_setup_setup_2_qs;
  logic rxenable_setup_setup_2_wd;
  logic rxenable_setup_setup_3_qs;
  logic rxenable_setup_setup_3_wd;
  logic rxenable_setup_setup_4_qs;
  logic rxenable_setup_setup_4_wd;
  logic rxenable_setup_setup_5_qs;
  logic rxenable_setup_setup_5_wd;
  logic rxenable_setup_setup_6_qs;
  logic rxenable_setup_setup_6_wd;
  logic rxenable_setup_setup_7_qs;
  logic rxenable_setup_setup_7_wd;
  logic rxenable_setup_setup_8_qs;
  logic rxenable_setup_setup_8_wd;
  logic rxenable_setup_setup_9_qs;
  logic rxenable_setup_setup_9_wd;
  logic rxenable_setup_setup_10_qs;
  logic rxenable_setup_setup_10_wd;
  logic rxenable_setup_setup_11_qs;
  logic rxenable_setup_setup_11_wd;
  logic rxenable_out_we;
  logic rxenable_out_out_0_qs;
  logic rxenable_out_out_0_wd;
  logic rxenable_out_out_1_qs;
  logic rxenable_out_out_1_wd;
  logic rxenable_out_out_2_qs;
  logic rxenable_out_out_2_wd;
  logic rxenable_out_out_3_qs;
  logic rxenable_out_out_3_wd;
  logic rxenable_out_out_4_qs;
  logic rxenable_out_out_4_wd;
  logic rxenable_out_out_5_qs;
  logic rxenable_out_out_5_wd;
  logic rxenable_out_out_6_qs;
  logic rxenable_out_out_6_wd;
  logic rxenable_out_out_7_qs;
  logic rxenable_out_out_7_wd;
  logic rxenable_out_out_8_qs;
  logic rxenable_out_out_8_wd;
  logic rxenable_out_out_9_qs;
  logic rxenable_out_out_9_wd;
  logic rxenable_out_out_10_qs;
  logic rxenable_out_out_10_wd;
  logic rxenable_out_out_11_qs;
  logic rxenable_out_out_11_wd;
  logic set_nak_out_we;
  logic set_nak_out_enable_0_qs;
  logic set_nak_out_enable_0_wd;
  logic set_nak_out_enable_1_qs;
  logic set_nak_out_enable_1_wd;
  logic set_nak_out_enable_2_qs;
  logic set_nak_out_enable_2_wd;
  logic set_nak_out_enable_3_qs;
  logic set_nak_out_enable_3_wd;
  logic set_nak_out_enable_4_qs;
  logic set_nak_out_enable_4_wd;
  logic set_nak_out_enable_5_qs;
  logic set_nak_out_enable_5_wd;
  logic set_nak_out_enable_6_qs;
  logic set_nak_out_enable_6_wd;
  logic set_nak_out_enable_7_qs;
  logic set_nak_out_enable_7_wd;
  logic set_nak_out_enable_8_qs;
  logic set_nak_out_enable_8_wd;
  logic set_nak_out_enable_9_qs;
  logic set_nak_out_enable_9_wd;
  logic set_nak_out_enable_10_qs;
  logic set_nak_out_enable_10_wd;
  logic set_nak_out_enable_11_qs;
  logic set_nak_out_enable_11_wd;
  logic in_sent_we;
  logic in_sent_sent_0_qs;
  logic in_sent_sent_0_wd;
  logic in_sent_sent_1_qs;
  logic in_sent_sent_1_wd;
  logic in_sent_sent_2_qs;
  logic in_sent_sent_2_wd;
  logic in_sent_sent_3_qs;
  logic in_sent_sent_3_wd;
  logic in_sent_sent_4_qs;
  logic in_sent_sent_4_wd;
  logic in_sent_sent_5_qs;
  logic in_sent_sent_5_wd;
  logic in_sent_sent_6_qs;
  logic in_sent_sent_6_wd;
  logic in_sent_sent_7_qs;
  logic in_sent_sent_7_wd;
  logic in_sent_sent_8_qs;
  logic in_sent_sent_8_wd;
  logic in_sent_sent_9_qs;
  logic in_sent_sent_9_wd;
  logic in_sent_sent_10_qs;
  logic in_sent_sent_10_wd;
  logic in_sent_sent_11_qs;
  logic in_sent_sent_11_wd;
  logic out_stall_we;
  logic out_stall_endpoint_0_qs;
  logic out_stall_endpoint_0_wd;
  logic out_stall_endpoint_1_qs;
  logic out_stall_endpoint_1_wd;
  logic out_stall_endpoint_2_qs;
  logic out_stall_endpoint_2_wd;
  logic out_stall_endpoint_3_qs;
  logic out_stall_endpoint_3_wd;
  logic out_stall_endpoint_4_qs;
  logic out_stall_endpoint_4_wd;
  logic out_stall_endpoint_5_qs;
  logic out_stall_endpoint_5_wd;
  logic out_stall_endpoint_6_qs;
  logic out_stall_endpoint_6_wd;
  logic out_stall_endpoint_7_qs;
  logic out_stall_endpoint_7_wd;
  logic out_stall_endpoint_8_qs;
  logic out_stall_endpoint_8_wd;
  logic out_stall_endpoint_9_qs;
  logic out_stall_endpoint_9_wd;
  logic out_stall_endpoint_10_qs;
  logic out_stall_endpoint_10_wd;
  logic out_stall_endpoint_11_qs;
  logic out_stall_endpoint_11_wd;
  logic in_stall_we;
  logic in_stall_endpoint_0_qs;
  logic in_stall_endpoint_0_wd;
  logic in_stall_endpoint_1_qs;
  logic in_stall_endpoint_1_wd;
  logic in_stall_endpoint_2_qs;
  logic in_stall_endpoint_2_wd;
  logic in_stall_endpoint_3_qs;
  logic in_stall_endpoint_3_wd;
  logic in_stall_endpoint_4_qs;
  logic in_stall_endpoint_4_wd;
  logic in_stall_endpoint_5_qs;
  logic in_stall_endpoint_5_wd;
  logic in_stall_endpoint_6_qs;
  logic in_stall_endpoint_6_wd;
  logic in_stall_endpoint_7_qs;
  logic in_stall_endpoint_7_wd;
  logic in_stall_endpoint_8_qs;
  logic in_stall_endpoint_8_wd;
  logic in_stall_endpoint_9_qs;
  logic in_stall_endpoint_9_wd;
  logic in_stall_endpoint_10_qs;
  logic in_stall_endpoint_10_wd;
  logic in_stall_endpoint_11_qs;
  logic in_stall_endpoint_11_wd;
  logic configin_0_we;
  logic [4:0] configin_0_buffer_0_qs;
  logic [4:0] configin_0_buffer_0_wd;
  logic [6:0] configin_0_size_0_qs;
  logic [6:0] configin_0_size_0_wd;
  logic configin_0_pend_0_qs;
  logic configin_0_pend_0_wd;
  logic configin_0_rdy_0_qs;
  logic configin_0_rdy_0_wd;
  logic configin_1_we;
  logic [4:0] configin_1_buffer_1_qs;
  logic [4:0] configin_1_buffer_1_wd;
  logic [6:0] configin_1_size_1_qs;
  logic [6:0] configin_1_size_1_wd;
  logic configin_1_pend_1_qs;
  logic configin_1_pend_1_wd;
  logic configin_1_rdy_1_qs;
  logic configin_1_rdy_1_wd;
  logic configin_2_we;
  logic [4:0] configin_2_buffer_2_qs;
  logic [4:0] configin_2_buffer_2_wd;
  logic [6:0] configin_2_size_2_qs;
  logic [6:0] configin_2_size_2_wd;
  logic configin_2_pend_2_qs;
  logic configin_2_pend_2_wd;
  logic configin_2_rdy_2_qs;
  logic configin_2_rdy_2_wd;
  logic configin_3_we;
  logic [4:0] configin_3_buffer_3_qs;
  logic [4:0] configin_3_buffer_3_wd;
  logic [6:0] configin_3_size_3_qs;
  logic [6:0] configin_3_size_3_wd;
  logic configin_3_pend_3_qs;
  logic configin_3_pend_3_wd;
  logic configin_3_rdy_3_qs;
  logic configin_3_rdy_3_wd;
  logic configin_4_we;
  logic [4:0] configin_4_buffer_4_qs;
  logic [4:0] configin_4_buffer_4_wd;
  logic [6:0] configin_4_size_4_qs;
  logic [6:0] configin_4_size_4_wd;
  logic configin_4_pend_4_qs;
  logic configin_4_pend_4_wd;
  logic configin_4_rdy_4_qs;
  logic configin_4_rdy_4_wd;
  logic configin_5_we;
  logic [4:0] configin_5_buffer_5_qs;
  logic [4:0] configin_5_buffer_5_wd;
  logic [6:0] configin_5_size_5_qs;
  logic [6:0] configin_5_size_5_wd;
  logic configin_5_pend_5_qs;
  logic configin_5_pend_5_wd;
  logic configin_5_rdy_5_qs;
  logic configin_5_rdy_5_wd;
  logic configin_6_we;
  logic [4:0] configin_6_buffer_6_qs;
  logic [4:0] configin_6_buffer_6_wd;
  logic [6:0] configin_6_size_6_qs;
  logic [6:0] configin_6_size_6_wd;
  logic configin_6_pend_6_qs;
  logic configin_6_pend_6_wd;
  logic configin_6_rdy_6_qs;
  logic configin_6_rdy_6_wd;
  logic configin_7_we;
  logic [4:0] configin_7_buffer_7_qs;
  logic [4:0] configin_7_buffer_7_wd;
  logic [6:0] configin_7_size_7_qs;
  logic [6:0] configin_7_size_7_wd;
  logic configin_7_pend_7_qs;
  logic configin_7_pend_7_wd;
  logic configin_7_rdy_7_qs;
  logic configin_7_rdy_7_wd;
  logic configin_8_we;
  logic [4:0] configin_8_buffer_8_qs;
  logic [4:0] configin_8_buffer_8_wd;
  logic [6:0] configin_8_size_8_qs;
  logic [6:0] configin_8_size_8_wd;
  logic configin_8_pend_8_qs;
  logic configin_8_pend_8_wd;
  logic configin_8_rdy_8_qs;
  logic configin_8_rdy_8_wd;
  logic configin_9_we;
  logic [4:0] configin_9_buffer_9_qs;
  logic [4:0] configin_9_buffer_9_wd;
  logic [6:0] configin_9_size_9_qs;
  logic [6:0] configin_9_size_9_wd;
  logic configin_9_pend_9_qs;
  logic configin_9_pend_9_wd;
  logic configin_9_rdy_9_qs;
  logic configin_9_rdy_9_wd;
  logic configin_10_we;
  logic [4:0] configin_10_buffer_10_qs;
  logic [4:0] configin_10_buffer_10_wd;
  logic [6:0] configin_10_size_10_qs;
  logic [6:0] configin_10_size_10_wd;
  logic configin_10_pend_10_qs;
  logic configin_10_pend_10_wd;
  logic configin_10_rdy_10_qs;
  logic configin_10_rdy_10_wd;
  logic configin_11_we;
  logic [4:0] configin_11_buffer_11_qs;
  logic [4:0] configin_11_buffer_11_wd;
  logic [6:0] configin_11_size_11_qs;
  logic [6:0] configin_11_size_11_wd;
  logic configin_11_pend_11_qs;
  logic configin_11_pend_11_wd;
  logic configin_11_rdy_11_qs;
  logic configin_11_rdy_11_wd;
  logic out_iso_we;
  logic out_iso_iso_0_qs;
  logic out_iso_iso_0_wd;
  logic out_iso_iso_1_qs;
  logic out_iso_iso_1_wd;
  logic out_iso_iso_2_qs;
  logic out_iso_iso_2_wd;
  logic out_iso_iso_3_qs;
  logic out_iso_iso_3_wd;
  logic out_iso_iso_4_qs;
  logic out_iso_iso_4_wd;
  logic out_iso_iso_5_qs;
  logic out_iso_iso_5_wd;
  logic out_iso_iso_6_qs;
  logic out_iso_iso_6_wd;
  logic out_iso_iso_7_qs;
  logic out_iso_iso_7_wd;
  logic out_iso_iso_8_qs;
  logic out_iso_iso_8_wd;
  logic out_iso_iso_9_qs;
  logic out_iso_iso_9_wd;
  logic out_iso_iso_10_qs;
  logic out_iso_iso_10_wd;
  logic out_iso_iso_11_qs;
  logic out_iso_iso_11_wd;
  logic in_iso_we;
  logic in_iso_iso_0_qs;
  logic in_iso_iso_0_wd;
  logic in_iso_iso_1_qs;
  logic in_iso_iso_1_wd;
  logic in_iso_iso_2_qs;
  logic in_iso_iso_2_wd;
  logic in_iso_iso_3_qs;
  logic in_iso_iso_3_wd;
  logic in_iso_iso_4_qs;
  logic in_iso_iso_4_wd;
  logic in_iso_iso_5_qs;
  logic in_iso_iso_5_wd;
  logic in_iso_iso_6_qs;
  logic in_iso_iso_6_wd;
  logic in_iso_iso_7_qs;
  logic in_iso_iso_7_wd;
  logic in_iso_iso_8_qs;
  logic in_iso_iso_8_wd;
  logic in_iso_iso_9_qs;
  logic in_iso_iso_9_wd;
  logic in_iso_iso_10_qs;
  logic in_iso_iso_10_wd;
  logic in_iso_iso_11_qs;
  logic in_iso_iso_11_wd;
  logic data_toggle_clear_we;
  logic data_toggle_clear_clear_0_wd;
  logic data_toggle_clear_clear_1_wd;
  logic data_toggle_clear_clear_2_wd;
  logic data_toggle_clear_clear_3_wd;
  logic data_toggle_clear_clear_4_wd;
  logic data_toggle_clear_clear_5_wd;
  logic data_toggle_clear_clear_6_wd;
  logic data_toggle_clear_clear_7_wd;
  logic data_toggle_clear_clear_8_wd;
  logic data_toggle_clear_clear_9_wd;
  logic data_toggle_clear_clear_10_wd;
  logic data_toggle_clear_clear_11_wd;
  logic phy_pins_sense_re;
  logic phy_pins_sense_rx_dp_i_qs;
  logic phy_pins_sense_rx_dn_i_qs;
  logic phy_pins_sense_rx_d_i_qs;
  logic phy_pins_sense_tx_dp_o_qs;
  logic phy_pins_sense_tx_dn_o_qs;
  logic phy_pins_sense_tx_d_o_qs;
  logic phy_pins_sense_tx_se0_o_qs;
  logic phy_pins_sense_tx_oe_o_qs;
  logic phy_pins_sense_pwr_sense_qs;
  logic phy_pins_drive_we;
  logic phy_pins_drive_dp_o_qs;
  logic phy_pins_drive_dp_o_wd;
  logic phy_pins_drive_dn_o_qs;
  logic phy_pins_drive_dn_o_wd;
  logic phy_pins_drive_d_o_qs;
  logic phy_pins_drive_d_o_wd;
  logic phy_pins_drive_se0_o_qs;
  logic phy_pins_drive_se0_o_wd;
  logic phy_pins_drive_oe_o_qs;
  logic phy_pins_drive_oe_o_wd;
  logic phy_pins_drive_rx_enable_o_qs;
  logic phy_pins_drive_rx_enable_o_wd;
  logic phy_pins_drive_dp_pullup_en_o_qs;
  logic phy_pins_drive_dp_pullup_en_o_wd;
  logic phy_pins_drive_dn_pullup_en_o_qs;
  logic phy_pins_drive_dn_pullup_en_o_wd;
  logic phy_pins_drive_en_qs;
  logic phy_pins_drive_en_wd;
  logic phy_config_we;
  logic phy_config_use_diff_rcvr_qs;
  logic phy_config_use_diff_rcvr_wd;
  logic phy_config_tx_use_d_se0_qs;
  logic phy_config_tx_use_d_se0_wd;
  logic phy_config_eop_single_bit_qs;
  logic phy_config_eop_single_bit_wd;
  logic phy_config_pinflip_qs;
  logic phy_config_pinflip_wd;
  logic phy_config_usb_ref_disable_qs;
  logic phy_config_usb_ref_disable_wd;
  logic phy_config_tx_osc_test_mode_qs;
  logic phy_config_tx_osc_test_mode_wd;
  logic wake_control_we;
  logic [1:0] wake_control_qs;
  logic wake_control_busy;
  logic [9:0] wake_events_qs;
  logic wake_events_busy;
  // Define register CDC handling.
  // CDC handling is done on a per-reg instead of per-field boundary.

  logic [1:0] aon_wake_control_qs;
  logic [1:0] aon_wake_control_wdata;
  logic aon_wake_control_we;
  logic unused_aon_wake_control_wdata;

  always_comb begin
    aon_wake_control_qs = 2'h0;
  end

  prim_reg_cdc #(
    .DataWidth(2),
    .ResetVal(2'h0),
    .BitMask(2'h3),
    .DstWrReq(0)
  ) u_wake_control_cdc (
    .clk_src_i    (clk_i),
    .rst_src_ni   (rst_ni),
    .clk_dst_i    (clk_aon_i),
    .rst_dst_ni   (rst_aon_ni),
    .src_regwen_i ('0),
    .src_we_i     (wake_control_we),
    .src_re_i     ('0),
    .src_wd_i     (reg_wdata[1:0]),
    .src_busy_o   (wake_control_busy),
    .src_qs_o     (wake_control_qs), // for software read back
    .dst_update_i ('0),
    .dst_ds_i     ('0),
    .dst_qs_i     (aon_wake_control_qs),
    .dst_we_o     (aon_wake_control_we),
    .dst_re_o     (),
    .dst_regwen_o (),
    .dst_wd_o     (aon_wake_control_wdata)
  );
  assign unused_aon_wake_control_wdata =
      ^aon_wake_control_wdata;

  logic  aon_wake_events_module_active_ds_int;
  logic  aon_wake_events_module_active_qs_int;
  logic  aon_wake_events_disconnected_ds_int;
  logic  aon_wake_events_disconnected_qs_int;
  logic  aon_wake_events_bus_reset_ds_int;
  logic  aon_wake_events_bus_reset_qs_int;
  logic [9:0] aon_wake_events_ds;
  logic aon_wake_events_qe;
  logic [9:0] aon_wake_events_qs;

  always_comb begin
    aon_wake_events_qs = 10'h0;
    aon_wake_events_ds = 10'h0;
    aon_wake_events_ds[0] = aon_wake_events_module_active_ds_int;
    aon_wake_events_qs[0] = aon_wake_events_module_active_qs_int;
    aon_wake_events_ds[8] = aon_wake_events_disconnected_ds_int;
    aon_wake_events_qs[8] = aon_wake_events_disconnected_qs_int;
    aon_wake_events_ds[9] = aon_wake_events_bus_reset_ds_int;
    aon_wake_events_qs[9] = aon_wake_events_bus_reset_qs_int;
  end

  prim_reg_cdc #(
    .DataWidth(10),
    .ResetVal(10'h0),
    .BitMask(10'h301),
    .DstWrReq(1)
  ) u_wake_events_cdc (
    .clk_src_i    (clk_i),
    .rst_src_ni   (rst_ni),
    .clk_dst_i    (clk_aon_i),
    .rst_dst_ni   (rst_aon_ni),
    .src_regwen_i ('0),
    .src_we_i     ('0),
    .src_re_i     ('0),
    .src_wd_i     ('0),
    .src_busy_o   (wake_events_busy),
    .src_qs_o     (wake_events_qs), // for software read back
    .dst_update_i (aon_wake_events_qe),
    .dst_ds_i     (aon_wake_events_ds),
    .dst_qs_i     (aon_wake_events_qs),
    .dst_we_o     (),
    .dst_re_o     (),
    .dst_regwen_o (),
    .dst_wd_o     ()
  );

  // Register instances
  // R[intr_state]: V(False)
  //   F[pkt_received]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_pkt_received (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_pkt_received_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.pkt_received.de),
    .d      (hw2reg.intr_state.pkt_received.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.pkt_received.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_pkt_received_qs)
  );

  //   F[pkt_sent]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_pkt_sent (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_pkt_sent_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.pkt_sent.de),
    .d      (hw2reg.intr_state.pkt_sent.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.pkt_sent.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_pkt_sent_qs)
  );

  //   F[disconnected]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_disconnected (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_disconnected_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.disconnected.de),
    .d      (hw2reg.intr_state.disconnected.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.disconnected.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_disconnected_qs)
  );

  //   F[host_lost]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_host_lost (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_host_lost_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.host_lost.de),
    .d      (hw2reg.intr_state.host_lost.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.host_lost.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_host_lost_qs)
  );

  //   F[link_reset]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_link_reset (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_link_reset_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.link_reset.de),
    .d      (hw2reg.intr_state.link_reset.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.link_reset.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_link_reset_qs)
  );

  //   F[link_suspend]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_link_suspend (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_link_suspend_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.link_suspend.de),
    .d      (hw2reg.intr_state.link_suspend.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.link_suspend.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_link_suspend_qs)
  );

  //   F[link_resume]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_link_resume (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_link_resume_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.link_resume.de),
    .d      (hw2reg.intr_state.link_resume.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.link_resume.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_link_resume_qs)
  );

  //   F[av_empty]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_av_empty (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_av_empty_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.av_empty.de),
    .d      (hw2reg.intr_state.av_empty.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.av_empty.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_av_empty_qs)
  );

  //   F[rx_full]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_rx_full (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_rx_full_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.rx_full.de),
    .d      (hw2reg.intr_state.rx_full.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.rx_full.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_rx_full_qs)
  );

  //   F[av_overflow]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_av_overflow (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_av_overflow_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.av_overflow.de),
    .d      (hw2reg.intr_state.av_overflow.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.av_overflow.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_av_overflow_qs)
  );

  //   F[link_in_err]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_link_in_err (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_link_in_err_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.link_in_err.de),
    .d      (hw2reg.intr_state.link_in_err.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.link_in_err.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_link_in_err_qs)
  );

  //   F[rx_crc_err]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_rx_crc_err (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_rx_crc_err_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.rx_crc_err.de),
    .d      (hw2reg.intr_state.rx_crc_err.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.rx_crc_err.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_rx_crc_err_qs)
  );

  //   F[rx_pid_err]: 12:12
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_rx_pid_err (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_rx_pid_err_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.rx_pid_err.de),
    .d      (hw2reg.intr_state.rx_pid_err.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.rx_pid_err.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_rx_pid_err_qs)
  );

  //   F[rx_bitstuff_err]: 13:13
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_rx_bitstuff_err (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_rx_bitstuff_err_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.rx_bitstuff_err.de),
    .d      (hw2reg.intr_state.rx_bitstuff_err.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.rx_bitstuff_err.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_rx_bitstuff_err_qs)
  );

  //   F[frame]: 14:14
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_frame (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_frame_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.frame.de),
    .d      (hw2reg.intr_state.frame.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.frame.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_frame_qs)
  );

  //   F[powered]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_powered (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_powered_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.powered.de),
    .d      (hw2reg.intr_state.powered.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.powered.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_powered_qs)
  );

  //   F[link_out_err]: 16:16
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_intr_state_link_out_err (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_state_we),
    .wd     (intr_state_link_out_err_wd),

    // from internal hardware
    .de     (hw2reg.intr_state.link_out_err.de),
    .d      (hw2reg.intr_state.link_out_err.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_state.link_out_err.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_state_link_out_err_qs)
  );


  // R[intr_enable]: V(False)
  //   F[pkt_received]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_pkt_received (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_pkt_received_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.pkt_received.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_pkt_received_qs)
  );

  //   F[pkt_sent]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_pkt_sent (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_pkt_sent_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.pkt_sent.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_pkt_sent_qs)
  );

  //   F[disconnected]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_disconnected (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_disconnected_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.disconnected.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_disconnected_qs)
  );

  //   F[host_lost]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_host_lost (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_host_lost_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.host_lost.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_host_lost_qs)
  );

  //   F[link_reset]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_link_reset (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_link_reset_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.link_reset.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_link_reset_qs)
  );

  //   F[link_suspend]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_link_suspend (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_link_suspend_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.link_suspend.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_link_suspend_qs)
  );

  //   F[link_resume]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_link_resume (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_link_resume_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.link_resume.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_link_resume_qs)
  );

  //   F[av_empty]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_av_empty (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_av_empty_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.av_empty.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_av_empty_qs)
  );

  //   F[rx_full]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_rx_full (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_rx_full_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.rx_full.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_rx_full_qs)
  );

  //   F[av_overflow]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_av_overflow (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_av_overflow_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.av_overflow.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_av_overflow_qs)
  );

  //   F[link_in_err]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_link_in_err (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_link_in_err_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.link_in_err.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_link_in_err_qs)
  );

  //   F[rx_crc_err]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_rx_crc_err (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_rx_crc_err_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.rx_crc_err.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_rx_crc_err_qs)
  );

  //   F[rx_pid_err]: 12:12
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_rx_pid_err (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_rx_pid_err_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.rx_pid_err.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_rx_pid_err_qs)
  );

  //   F[rx_bitstuff_err]: 13:13
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_rx_bitstuff_err (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_rx_bitstuff_err_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.rx_bitstuff_err.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_rx_bitstuff_err_qs)
  );

  //   F[frame]: 14:14
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_frame (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_frame_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.frame.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_frame_qs)
  );

  //   F[powered]: 15:15
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_powered (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_powered_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.powered.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_powered_qs)
  );

  //   F[link_out_err]: 16:16
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_intr_enable_link_out_err (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (intr_enable_we),
    .wd     (intr_enable_link_out_err_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intr_enable.link_out_err.q),
    .ds     (),

    // to register interface (read)
    .qs     (intr_enable_link_out_err_qs)
  );


  // R[intr_test]: V(True)
  logic intr_test_qe;
  logic [16:0] intr_test_flds_we;
  assign intr_test_qe = &intr_test_flds_we;
  //   F[pkt_received]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_pkt_received (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_pkt_received_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[0]),
    .q      (reg2hw.intr_test.pkt_received.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.pkt_received.qe = intr_test_qe;

  //   F[pkt_sent]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_pkt_sent (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_pkt_sent_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[1]),
    .q      (reg2hw.intr_test.pkt_sent.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.pkt_sent.qe = intr_test_qe;

  //   F[disconnected]: 2:2
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_disconnected (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_disconnected_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[2]),
    .q      (reg2hw.intr_test.disconnected.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.disconnected.qe = intr_test_qe;

  //   F[host_lost]: 3:3
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_host_lost (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_host_lost_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[3]),
    .q      (reg2hw.intr_test.host_lost.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.host_lost.qe = intr_test_qe;

  //   F[link_reset]: 4:4
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_link_reset (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_link_reset_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[4]),
    .q      (reg2hw.intr_test.link_reset.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.link_reset.qe = intr_test_qe;

  //   F[link_suspend]: 5:5
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_link_suspend (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_link_suspend_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[5]),
    .q      (reg2hw.intr_test.link_suspend.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.link_suspend.qe = intr_test_qe;

  //   F[link_resume]: 6:6
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_link_resume (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_link_resume_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[6]),
    .q      (reg2hw.intr_test.link_resume.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.link_resume.qe = intr_test_qe;

  //   F[av_empty]: 7:7
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_av_empty (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_av_empty_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[7]),
    .q      (reg2hw.intr_test.av_empty.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.av_empty.qe = intr_test_qe;

  //   F[rx_full]: 8:8
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_rx_full (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_rx_full_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[8]),
    .q      (reg2hw.intr_test.rx_full.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.rx_full.qe = intr_test_qe;

  //   F[av_overflow]: 9:9
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_av_overflow (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_av_overflow_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[9]),
    .q      (reg2hw.intr_test.av_overflow.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.av_overflow.qe = intr_test_qe;

  //   F[link_in_err]: 10:10
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_link_in_err (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_link_in_err_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[10]),
    .q      (reg2hw.intr_test.link_in_err.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.link_in_err.qe = intr_test_qe;

  //   F[rx_crc_err]: 11:11
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_rx_crc_err (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_rx_crc_err_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[11]),
    .q      (reg2hw.intr_test.rx_crc_err.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.rx_crc_err.qe = intr_test_qe;

  //   F[rx_pid_err]: 12:12
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_rx_pid_err (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_rx_pid_err_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[12]),
    .q      (reg2hw.intr_test.rx_pid_err.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.rx_pid_err.qe = intr_test_qe;

  //   F[rx_bitstuff_err]: 13:13
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_rx_bitstuff_err (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_rx_bitstuff_err_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[13]),
    .q      (reg2hw.intr_test.rx_bitstuff_err.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.rx_bitstuff_err.qe = intr_test_qe;

  //   F[frame]: 14:14
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_frame (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_frame_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[14]),
    .q      (reg2hw.intr_test.frame.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.frame.qe = intr_test_qe;

  //   F[powered]: 15:15
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_powered (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_powered_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[15]),
    .q      (reg2hw.intr_test.powered.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.powered.qe = intr_test_qe;

  //   F[link_out_err]: 16:16
  prim_subreg_ext #(
    .DW    (1)
  ) u_intr_test_link_out_err (
    .re     (1'b0),
    .we     (intr_test_we),
    .wd     (intr_test_link_out_err_wd),
    .d      ('0),
    .qre    (),
    .qe     (intr_test_flds_we[16]),
    .q      (reg2hw.intr_test.link_out_err.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.intr_test.link_out_err.qe = intr_test_qe;


  // R[alert_test]: V(True)
  logic alert_test_qe;
  logic [0:0] alert_test_flds_we;
  assign alert_test_qe = &alert_test_flds_we;
  prim_subreg_ext #(
    .DW    (1)
  ) u_alert_test (
    .re     (1'b0),
    .we     (alert_test_we),
    .wd     (alert_test_wd),
    .d      ('0),
    .qre    (),
    .qe     (alert_test_flds_we[0]),
    .q      (reg2hw.alert_test.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.alert_test.qe = alert_test_qe;


  // R[usbctrl]: V(False)
  logic usbctrl_qe;
  logic [2:0] usbctrl_flds_we;
  prim_flop #(
    .Width(1),
    .ResetValue(0)
  ) u_usbctrl0_qe (
    .clk_i(clk_i),
    .rst_ni(rst_ni),
    .d_i(&usbctrl_flds_we),
    .q_o(usbctrl_qe)
  );
  //   F[enable]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_usbctrl_enable (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (usbctrl_we),
    .wd     (usbctrl_enable_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (usbctrl_flds_we[0]),
    .q      (reg2hw.usbctrl.enable.q),
    .ds     (),

    // to register interface (read)
    .qs     (usbctrl_enable_qs)
  );

  //   F[resume_link_active]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessWO),
    .RESVAL  (1'h0)
  ) u_usbctrl_resume_link_active (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (usbctrl_we),
    .wd     (usbctrl_resume_link_active_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (usbctrl_flds_we[1]),
    .q      (reg2hw.usbctrl.resume_link_active.q),
    .ds     (),

    // to register interface (read)
    .qs     ()
  );
  assign reg2hw.usbctrl.resume_link_active.qe = usbctrl_qe;

  //   F[device_address]: 22:16
  prim_subreg #(
    .DW      (7),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (7'h0)
  ) u_usbctrl_device_address (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (usbctrl_we),
    .wd     (usbctrl_device_address_wd),

    // from internal hardware
    .de     (hw2reg.usbctrl.device_address.de),
    .d      (hw2reg.usbctrl.device_address.d),

    // to internal hardware
    .qe     (usbctrl_flds_we[2]),
    .q      (reg2hw.usbctrl.device_address.q),
    .ds     (),

    // to register interface (read)
    .qs     (usbctrl_device_address_qs)
  );


  // Subregister 0 of Multireg ep_out_enable
  // R[ep_out_enable]: V(False)
  //   F[enable_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_out_enable_enable_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_out_enable_we),
    .wd     (ep_out_enable_enable_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_out_enable[0].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_out_enable_enable_0_qs)
  );

  //   F[enable_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_out_enable_enable_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_out_enable_we),
    .wd     (ep_out_enable_enable_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_out_enable[1].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_out_enable_enable_1_qs)
  );

  //   F[enable_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_out_enable_enable_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_out_enable_we),
    .wd     (ep_out_enable_enable_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_out_enable[2].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_out_enable_enable_2_qs)
  );

  //   F[enable_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_out_enable_enable_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_out_enable_we),
    .wd     (ep_out_enable_enable_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_out_enable[3].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_out_enable_enable_3_qs)
  );

  //   F[enable_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_out_enable_enable_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_out_enable_we),
    .wd     (ep_out_enable_enable_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_out_enable[4].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_out_enable_enable_4_qs)
  );

  //   F[enable_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_out_enable_enable_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_out_enable_we),
    .wd     (ep_out_enable_enable_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_out_enable[5].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_out_enable_enable_5_qs)
  );

  //   F[enable_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_out_enable_enable_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_out_enable_we),
    .wd     (ep_out_enable_enable_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_out_enable[6].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_out_enable_enable_6_qs)
  );

  //   F[enable_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_out_enable_enable_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_out_enable_we),
    .wd     (ep_out_enable_enable_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_out_enable[7].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_out_enable_enable_7_qs)
  );

  //   F[enable_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_out_enable_enable_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_out_enable_we),
    .wd     (ep_out_enable_enable_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_out_enable[8].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_out_enable_enable_8_qs)
  );

  //   F[enable_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_out_enable_enable_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_out_enable_we),
    .wd     (ep_out_enable_enable_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_out_enable[9].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_out_enable_enable_9_qs)
  );

  //   F[enable_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_out_enable_enable_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_out_enable_we),
    .wd     (ep_out_enable_enable_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_out_enable[10].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_out_enable_enable_10_qs)
  );

  //   F[enable_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_out_enable_enable_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_out_enable_we),
    .wd     (ep_out_enable_enable_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_out_enable[11].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_out_enable_enable_11_qs)
  );


  // Subregister 0 of Multireg ep_in_enable
  // R[ep_in_enable]: V(False)
  //   F[enable_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_in_enable_enable_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_in_enable_we),
    .wd     (ep_in_enable_enable_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_in_enable[0].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_in_enable_enable_0_qs)
  );

  //   F[enable_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_in_enable_enable_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_in_enable_we),
    .wd     (ep_in_enable_enable_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_in_enable[1].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_in_enable_enable_1_qs)
  );

  //   F[enable_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_in_enable_enable_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_in_enable_we),
    .wd     (ep_in_enable_enable_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_in_enable[2].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_in_enable_enable_2_qs)
  );

  //   F[enable_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_in_enable_enable_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_in_enable_we),
    .wd     (ep_in_enable_enable_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_in_enable[3].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_in_enable_enable_3_qs)
  );

  //   F[enable_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_in_enable_enable_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_in_enable_we),
    .wd     (ep_in_enable_enable_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_in_enable[4].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_in_enable_enable_4_qs)
  );

  //   F[enable_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_in_enable_enable_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_in_enable_we),
    .wd     (ep_in_enable_enable_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_in_enable[5].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_in_enable_enable_5_qs)
  );

  //   F[enable_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_in_enable_enable_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_in_enable_we),
    .wd     (ep_in_enable_enable_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_in_enable[6].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_in_enable_enable_6_qs)
  );

  //   F[enable_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_in_enable_enable_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_in_enable_we),
    .wd     (ep_in_enable_enable_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_in_enable[7].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_in_enable_enable_7_qs)
  );

  //   F[enable_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_in_enable_enable_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_in_enable_we),
    .wd     (ep_in_enable_enable_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_in_enable[8].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_in_enable_enable_8_qs)
  );

  //   F[enable_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_in_enable_enable_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_in_enable_we),
    .wd     (ep_in_enable_enable_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_in_enable[9].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_in_enable_enable_9_qs)
  );

  //   F[enable_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_in_enable_enable_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_in_enable_we),
    .wd     (ep_in_enable_enable_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_in_enable[10].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_in_enable_enable_10_qs)
  );

  //   F[enable_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_ep_in_enable_enable_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (ep_in_enable_we),
    .wd     (ep_in_enable_enable_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.ep_in_enable[11].q),
    .ds     (),

    // to register interface (read)
    .qs     (ep_in_enable_enable_11_qs)
  );


  // R[usbstat]: V(True)
  //   F[frame]: 10:0
  prim_subreg_ext #(
    .DW    (11)
  ) u_usbstat_frame (
    .re     (usbstat_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.usbstat.frame.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (usbstat_frame_qs)
  );

  //   F[host_lost]: 11:11
  prim_subreg_ext #(
    .DW    (1)
  ) u_usbstat_host_lost (
    .re     (usbstat_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.usbstat.host_lost.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (usbstat_host_lost_qs)
  );

  //   F[link_state]: 14:12
  prim_subreg_ext #(
    .DW    (3)
  ) u_usbstat_link_state (
    .re     (usbstat_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.usbstat.link_state.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (usbstat_link_state_qs)
  );

  //   F[sense]: 15:15
  prim_subreg_ext #(
    .DW    (1)
  ) u_usbstat_sense (
    .re     (usbstat_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.usbstat.sense.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (usbstat_sense_qs)
  );

  //   F[av_depth]: 18:16
  prim_subreg_ext #(
    .DW    (3)
  ) u_usbstat_av_depth (
    .re     (usbstat_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.usbstat.av_depth.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (usbstat_av_depth_qs)
  );

  //   F[av_full]: 23:23
  prim_subreg_ext #(
    .DW    (1)
  ) u_usbstat_av_full (
    .re     (usbstat_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.usbstat.av_full.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (usbstat_av_full_qs)
  );

  //   F[rx_depth]: 26:24
  prim_subreg_ext #(
    .DW    (3)
  ) u_usbstat_rx_depth (
    .re     (usbstat_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.usbstat.rx_depth.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (usbstat_rx_depth_qs)
  );

  //   F[rx_empty]: 31:31
  prim_subreg_ext #(
    .DW    (1)
  ) u_usbstat_rx_empty (
    .re     (usbstat_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.usbstat.rx_empty.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (usbstat_rx_empty_qs)
  );


  // R[avbuffer]: V(False)
  logic avbuffer_qe;
  logic [0:0] avbuffer_flds_we;
  prim_flop #(
    .Width(1),
    .ResetValue(0)
  ) u_avbuffer0_qe (
    .clk_i(clk_i),
    .rst_ni(rst_ni),
    .d_i(&avbuffer_flds_we),
    .q_o(avbuffer_qe)
  );
  prim_subreg #(
    .DW      (5),
    .SwAccess(prim_subreg_pkg::SwAccessWO),
    .RESVAL  (5'h0)
  ) u_avbuffer (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (avbuffer_we),
    .wd     (avbuffer_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (avbuffer_flds_we[0]),
    .q      (reg2hw.avbuffer.q),
    .ds     (),

    // to register interface (read)
    .qs     ()
  );
  assign reg2hw.avbuffer.qe = avbuffer_qe;


  // R[rxfifo]: V(True)
  //   F[buffer]: 4:0
  prim_subreg_ext #(
    .DW    (5)
  ) u_rxfifo_buffer (
    .re     (rxfifo_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.rxfifo.buffer.d),
    .qre    (reg2hw.rxfifo.buffer.re),
    .qe     (),
    .q      (reg2hw.rxfifo.buffer.q),
    .ds     (),
    .qs     (rxfifo_buffer_qs)
  );

  //   F[size]: 14:8
  prim_subreg_ext #(
    .DW    (7)
  ) u_rxfifo_size (
    .re     (rxfifo_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.rxfifo.size.d),
    .qre    (reg2hw.rxfifo.size.re),
    .qe     (),
    .q      (reg2hw.rxfifo.size.q),
    .ds     (),
    .qs     (rxfifo_size_qs)
  );

  //   F[setup]: 19:19
  prim_subreg_ext #(
    .DW    (1)
  ) u_rxfifo_setup (
    .re     (rxfifo_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.rxfifo.setup.d),
    .qre    (reg2hw.rxfifo.setup.re),
    .qe     (),
    .q      (reg2hw.rxfifo.setup.q),
    .ds     (),
    .qs     (rxfifo_setup_qs)
  );

  //   F[ep]: 23:20
  prim_subreg_ext #(
    .DW    (4)
  ) u_rxfifo_ep (
    .re     (rxfifo_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.rxfifo.ep.d),
    .qre    (reg2hw.rxfifo.ep.re),
    .qe     (),
    .q      (reg2hw.rxfifo.ep.q),
    .ds     (),
    .qs     (rxfifo_ep_qs)
  );


  // Subregister 0 of Multireg rxenable_setup
  // R[rxenable_setup]: V(False)
  //   F[setup_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_setup_setup_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_setup_we),
    .wd     (rxenable_setup_setup_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_setup[0].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_setup_setup_0_qs)
  );

  //   F[setup_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_setup_setup_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_setup_we),
    .wd     (rxenable_setup_setup_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_setup[1].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_setup_setup_1_qs)
  );

  //   F[setup_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_setup_setup_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_setup_we),
    .wd     (rxenable_setup_setup_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_setup[2].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_setup_setup_2_qs)
  );

  //   F[setup_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_setup_setup_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_setup_we),
    .wd     (rxenable_setup_setup_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_setup[3].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_setup_setup_3_qs)
  );

  //   F[setup_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_setup_setup_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_setup_we),
    .wd     (rxenable_setup_setup_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_setup[4].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_setup_setup_4_qs)
  );

  //   F[setup_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_setup_setup_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_setup_we),
    .wd     (rxenable_setup_setup_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_setup[5].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_setup_setup_5_qs)
  );

  //   F[setup_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_setup_setup_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_setup_we),
    .wd     (rxenable_setup_setup_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_setup[6].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_setup_setup_6_qs)
  );

  //   F[setup_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_setup_setup_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_setup_we),
    .wd     (rxenable_setup_setup_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_setup[7].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_setup_setup_7_qs)
  );

  //   F[setup_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_setup_setup_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_setup_we),
    .wd     (rxenable_setup_setup_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_setup[8].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_setup_setup_8_qs)
  );

  //   F[setup_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_setup_setup_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_setup_we),
    .wd     (rxenable_setup_setup_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_setup[9].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_setup_setup_9_qs)
  );

  //   F[setup_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_setup_setup_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_setup_we),
    .wd     (rxenable_setup_setup_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_setup[10].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_setup_setup_10_qs)
  );

  //   F[setup_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_setup_setup_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_setup_we),
    .wd     (rxenable_setup_setup_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_setup[11].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_setup_setup_11_qs)
  );


  // Subregister 0 of Multireg rxenable_out
  // R[rxenable_out]: V(False)
  //   F[out_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_out_out_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_out_we),
    .wd     (rxenable_out_out_0_wd),

    // from internal hardware
    .de     (hw2reg.rxenable_out[0].de),
    .d      (hw2reg.rxenable_out[0].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_out[0].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_out_out_0_qs)
  );

  //   F[out_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_out_out_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_out_we),
    .wd     (rxenable_out_out_1_wd),

    // from internal hardware
    .de     (hw2reg.rxenable_out[1].de),
    .d      (hw2reg.rxenable_out[1].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_out[1].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_out_out_1_qs)
  );

  //   F[out_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_out_out_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_out_we),
    .wd     (rxenable_out_out_2_wd),

    // from internal hardware
    .de     (hw2reg.rxenable_out[2].de),
    .d      (hw2reg.rxenable_out[2].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_out[2].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_out_out_2_qs)
  );

  //   F[out_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_out_out_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_out_we),
    .wd     (rxenable_out_out_3_wd),

    // from internal hardware
    .de     (hw2reg.rxenable_out[3].de),
    .d      (hw2reg.rxenable_out[3].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_out[3].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_out_out_3_qs)
  );

  //   F[out_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_out_out_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_out_we),
    .wd     (rxenable_out_out_4_wd),

    // from internal hardware
    .de     (hw2reg.rxenable_out[4].de),
    .d      (hw2reg.rxenable_out[4].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_out[4].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_out_out_4_qs)
  );

  //   F[out_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_out_out_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_out_we),
    .wd     (rxenable_out_out_5_wd),

    // from internal hardware
    .de     (hw2reg.rxenable_out[5].de),
    .d      (hw2reg.rxenable_out[5].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_out[5].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_out_out_5_qs)
  );

  //   F[out_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_out_out_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_out_we),
    .wd     (rxenable_out_out_6_wd),

    // from internal hardware
    .de     (hw2reg.rxenable_out[6].de),
    .d      (hw2reg.rxenable_out[6].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_out[6].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_out_out_6_qs)
  );

  //   F[out_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_out_out_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_out_we),
    .wd     (rxenable_out_out_7_wd),

    // from internal hardware
    .de     (hw2reg.rxenable_out[7].de),
    .d      (hw2reg.rxenable_out[7].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_out[7].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_out_out_7_qs)
  );

  //   F[out_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_out_out_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_out_we),
    .wd     (rxenable_out_out_8_wd),

    // from internal hardware
    .de     (hw2reg.rxenable_out[8].de),
    .d      (hw2reg.rxenable_out[8].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_out[8].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_out_out_8_qs)
  );

  //   F[out_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_out_out_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_out_we),
    .wd     (rxenable_out_out_9_wd),

    // from internal hardware
    .de     (hw2reg.rxenable_out[9].de),
    .d      (hw2reg.rxenable_out[9].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_out[9].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_out_out_9_qs)
  );

  //   F[out_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_out_out_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_out_we),
    .wd     (rxenable_out_out_10_wd),

    // from internal hardware
    .de     (hw2reg.rxenable_out[10].de),
    .d      (hw2reg.rxenable_out[10].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_out[10].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_out_out_10_qs)
  );

  //   F[out_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_rxenable_out_out_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (rxenable_out_we),
    .wd     (rxenable_out_out_11_wd),

    // from internal hardware
    .de     (hw2reg.rxenable_out[11].de),
    .d      (hw2reg.rxenable_out[11].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.rxenable_out[11].q),
    .ds     (),

    // to register interface (read)
    .qs     (rxenable_out_out_11_qs)
  );


  // Subregister 0 of Multireg set_nak_out
  // R[set_nak_out]: V(False)
  //   F[enable_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_set_nak_out_enable_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (set_nak_out_we),
    .wd     (set_nak_out_enable_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.set_nak_out[0].q),
    .ds     (),

    // to register interface (read)
    .qs     (set_nak_out_enable_0_qs)
  );

  //   F[enable_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_set_nak_out_enable_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (set_nak_out_we),
    .wd     (set_nak_out_enable_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.set_nak_out[1].q),
    .ds     (),

    // to register interface (read)
    .qs     (set_nak_out_enable_1_qs)
  );

  //   F[enable_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_set_nak_out_enable_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (set_nak_out_we),
    .wd     (set_nak_out_enable_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.set_nak_out[2].q),
    .ds     (),

    // to register interface (read)
    .qs     (set_nak_out_enable_2_qs)
  );

  //   F[enable_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_set_nak_out_enable_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (set_nak_out_we),
    .wd     (set_nak_out_enable_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.set_nak_out[3].q),
    .ds     (),

    // to register interface (read)
    .qs     (set_nak_out_enable_3_qs)
  );

  //   F[enable_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_set_nak_out_enable_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (set_nak_out_we),
    .wd     (set_nak_out_enable_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.set_nak_out[4].q),
    .ds     (),

    // to register interface (read)
    .qs     (set_nak_out_enable_4_qs)
  );

  //   F[enable_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_set_nak_out_enable_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (set_nak_out_we),
    .wd     (set_nak_out_enable_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.set_nak_out[5].q),
    .ds     (),

    // to register interface (read)
    .qs     (set_nak_out_enable_5_qs)
  );

  //   F[enable_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_set_nak_out_enable_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (set_nak_out_we),
    .wd     (set_nak_out_enable_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.set_nak_out[6].q),
    .ds     (),

    // to register interface (read)
    .qs     (set_nak_out_enable_6_qs)
  );

  //   F[enable_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_set_nak_out_enable_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (set_nak_out_we),
    .wd     (set_nak_out_enable_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.set_nak_out[7].q),
    .ds     (),

    // to register interface (read)
    .qs     (set_nak_out_enable_7_qs)
  );

  //   F[enable_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_set_nak_out_enable_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (set_nak_out_we),
    .wd     (set_nak_out_enable_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.set_nak_out[8].q),
    .ds     (),

    // to register interface (read)
    .qs     (set_nak_out_enable_8_qs)
  );

  //   F[enable_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_set_nak_out_enable_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (set_nak_out_we),
    .wd     (set_nak_out_enable_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.set_nak_out[9].q),
    .ds     (),

    // to register interface (read)
    .qs     (set_nak_out_enable_9_qs)
  );

  //   F[enable_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_set_nak_out_enable_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (set_nak_out_we),
    .wd     (set_nak_out_enable_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.set_nak_out[10].q),
    .ds     (),

    // to register interface (read)
    .qs     (set_nak_out_enable_10_qs)
  );

  //   F[enable_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_set_nak_out_enable_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (set_nak_out_we),
    .wd     (set_nak_out_enable_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.set_nak_out[11].q),
    .ds     (),

    // to register interface (read)
    .qs     (set_nak_out_enable_11_qs)
  );


  // Subregister 0 of Multireg in_sent
  // R[in_sent]: V(False)
  //   F[sent_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_in_sent_sent_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_sent_we),
    .wd     (in_sent_sent_0_wd),

    // from internal hardware
    .de     (hw2reg.in_sent[0].de),
    .d      (hw2reg.in_sent[0].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_sent[0].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_sent_sent_0_qs)
  );

  //   F[sent_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_in_sent_sent_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_sent_we),
    .wd     (in_sent_sent_1_wd),

    // from internal hardware
    .de     (hw2reg.in_sent[1].de),
    .d      (hw2reg.in_sent[1].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_sent[1].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_sent_sent_1_qs)
  );

  //   F[sent_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_in_sent_sent_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_sent_we),
    .wd     (in_sent_sent_2_wd),

    // from internal hardware
    .de     (hw2reg.in_sent[2].de),
    .d      (hw2reg.in_sent[2].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_sent[2].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_sent_sent_2_qs)
  );

  //   F[sent_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_in_sent_sent_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_sent_we),
    .wd     (in_sent_sent_3_wd),

    // from internal hardware
    .de     (hw2reg.in_sent[3].de),
    .d      (hw2reg.in_sent[3].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_sent[3].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_sent_sent_3_qs)
  );

  //   F[sent_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_in_sent_sent_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_sent_we),
    .wd     (in_sent_sent_4_wd),

    // from internal hardware
    .de     (hw2reg.in_sent[4].de),
    .d      (hw2reg.in_sent[4].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_sent[4].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_sent_sent_4_qs)
  );

  //   F[sent_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_in_sent_sent_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_sent_we),
    .wd     (in_sent_sent_5_wd),

    // from internal hardware
    .de     (hw2reg.in_sent[5].de),
    .d      (hw2reg.in_sent[5].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_sent[5].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_sent_sent_5_qs)
  );

  //   F[sent_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_in_sent_sent_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_sent_we),
    .wd     (in_sent_sent_6_wd),

    // from internal hardware
    .de     (hw2reg.in_sent[6].de),
    .d      (hw2reg.in_sent[6].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_sent[6].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_sent_sent_6_qs)
  );

  //   F[sent_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_in_sent_sent_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_sent_we),
    .wd     (in_sent_sent_7_wd),

    // from internal hardware
    .de     (hw2reg.in_sent[7].de),
    .d      (hw2reg.in_sent[7].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_sent[7].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_sent_sent_7_qs)
  );

  //   F[sent_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_in_sent_sent_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_sent_we),
    .wd     (in_sent_sent_8_wd),

    // from internal hardware
    .de     (hw2reg.in_sent[8].de),
    .d      (hw2reg.in_sent[8].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_sent[8].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_sent_sent_8_qs)
  );

  //   F[sent_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_in_sent_sent_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_sent_we),
    .wd     (in_sent_sent_9_wd),

    // from internal hardware
    .de     (hw2reg.in_sent[9].de),
    .d      (hw2reg.in_sent[9].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_sent[9].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_sent_sent_9_qs)
  );

  //   F[sent_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_in_sent_sent_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_sent_we),
    .wd     (in_sent_sent_10_wd),

    // from internal hardware
    .de     (hw2reg.in_sent[10].de),
    .d      (hw2reg.in_sent[10].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_sent[10].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_sent_sent_10_qs)
  );

  //   F[sent_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_in_sent_sent_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_sent_we),
    .wd     (in_sent_sent_11_wd),

    // from internal hardware
    .de     (hw2reg.in_sent[11].de),
    .d      (hw2reg.in_sent[11].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_sent[11].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_sent_sent_11_qs)
  );


  // Subregister 0 of Multireg out_stall
  // R[out_stall]: V(False)
  //   F[endpoint_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_stall_endpoint_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_stall_we),
    .wd     (out_stall_endpoint_0_wd),

    // from internal hardware
    .de     (hw2reg.out_stall[0].de),
    .d      (hw2reg.out_stall[0].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_stall[0].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_stall_endpoint_0_qs)
  );

  //   F[endpoint_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_stall_endpoint_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_stall_we),
    .wd     (out_stall_endpoint_1_wd),

    // from internal hardware
    .de     (hw2reg.out_stall[1].de),
    .d      (hw2reg.out_stall[1].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_stall[1].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_stall_endpoint_1_qs)
  );

  //   F[endpoint_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_stall_endpoint_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_stall_we),
    .wd     (out_stall_endpoint_2_wd),

    // from internal hardware
    .de     (hw2reg.out_stall[2].de),
    .d      (hw2reg.out_stall[2].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_stall[2].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_stall_endpoint_2_qs)
  );

  //   F[endpoint_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_stall_endpoint_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_stall_we),
    .wd     (out_stall_endpoint_3_wd),

    // from internal hardware
    .de     (hw2reg.out_stall[3].de),
    .d      (hw2reg.out_stall[3].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_stall[3].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_stall_endpoint_3_qs)
  );

  //   F[endpoint_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_stall_endpoint_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_stall_we),
    .wd     (out_stall_endpoint_4_wd),

    // from internal hardware
    .de     (hw2reg.out_stall[4].de),
    .d      (hw2reg.out_stall[4].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_stall[4].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_stall_endpoint_4_qs)
  );

  //   F[endpoint_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_stall_endpoint_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_stall_we),
    .wd     (out_stall_endpoint_5_wd),

    // from internal hardware
    .de     (hw2reg.out_stall[5].de),
    .d      (hw2reg.out_stall[5].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_stall[5].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_stall_endpoint_5_qs)
  );

  //   F[endpoint_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_stall_endpoint_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_stall_we),
    .wd     (out_stall_endpoint_6_wd),

    // from internal hardware
    .de     (hw2reg.out_stall[6].de),
    .d      (hw2reg.out_stall[6].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_stall[6].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_stall_endpoint_6_qs)
  );

  //   F[endpoint_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_stall_endpoint_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_stall_we),
    .wd     (out_stall_endpoint_7_wd),

    // from internal hardware
    .de     (hw2reg.out_stall[7].de),
    .d      (hw2reg.out_stall[7].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_stall[7].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_stall_endpoint_7_qs)
  );

  //   F[endpoint_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_stall_endpoint_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_stall_we),
    .wd     (out_stall_endpoint_8_wd),

    // from internal hardware
    .de     (hw2reg.out_stall[8].de),
    .d      (hw2reg.out_stall[8].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_stall[8].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_stall_endpoint_8_qs)
  );

  //   F[endpoint_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_stall_endpoint_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_stall_we),
    .wd     (out_stall_endpoint_9_wd),

    // from internal hardware
    .de     (hw2reg.out_stall[9].de),
    .d      (hw2reg.out_stall[9].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_stall[9].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_stall_endpoint_9_qs)
  );

  //   F[endpoint_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_stall_endpoint_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_stall_we),
    .wd     (out_stall_endpoint_10_wd),

    // from internal hardware
    .de     (hw2reg.out_stall[10].de),
    .d      (hw2reg.out_stall[10].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_stall[10].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_stall_endpoint_10_qs)
  );

  //   F[endpoint_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_stall_endpoint_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_stall_we),
    .wd     (out_stall_endpoint_11_wd),

    // from internal hardware
    .de     (hw2reg.out_stall[11].de),
    .d      (hw2reg.out_stall[11].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_stall[11].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_stall_endpoint_11_qs)
  );


  // Subregister 0 of Multireg in_stall
  // R[in_stall]: V(False)
  //   F[endpoint_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_stall_endpoint_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_stall_we),
    .wd     (in_stall_endpoint_0_wd),

    // from internal hardware
    .de     (hw2reg.in_stall[0].de),
    .d      (hw2reg.in_stall[0].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_stall[0].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_stall_endpoint_0_qs)
  );

  //   F[endpoint_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_stall_endpoint_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_stall_we),
    .wd     (in_stall_endpoint_1_wd),

    // from internal hardware
    .de     (hw2reg.in_stall[1].de),
    .d      (hw2reg.in_stall[1].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_stall[1].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_stall_endpoint_1_qs)
  );

  //   F[endpoint_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_stall_endpoint_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_stall_we),
    .wd     (in_stall_endpoint_2_wd),

    // from internal hardware
    .de     (hw2reg.in_stall[2].de),
    .d      (hw2reg.in_stall[2].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_stall[2].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_stall_endpoint_2_qs)
  );

  //   F[endpoint_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_stall_endpoint_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_stall_we),
    .wd     (in_stall_endpoint_3_wd),

    // from internal hardware
    .de     (hw2reg.in_stall[3].de),
    .d      (hw2reg.in_stall[3].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_stall[3].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_stall_endpoint_3_qs)
  );

  //   F[endpoint_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_stall_endpoint_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_stall_we),
    .wd     (in_stall_endpoint_4_wd),

    // from internal hardware
    .de     (hw2reg.in_stall[4].de),
    .d      (hw2reg.in_stall[4].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_stall[4].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_stall_endpoint_4_qs)
  );

  //   F[endpoint_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_stall_endpoint_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_stall_we),
    .wd     (in_stall_endpoint_5_wd),

    // from internal hardware
    .de     (hw2reg.in_stall[5].de),
    .d      (hw2reg.in_stall[5].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_stall[5].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_stall_endpoint_5_qs)
  );

  //   F[endpoint_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_stall_endpoint_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_stall_we),
    .wd     (in_stall_endpoint_6_wd),

    // from internal hardware
    .de     (hw2reg.in_stall[6].de),
    .d      (hw2reg.in_stall[6].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_stall[6].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_stall_endpoint_6_qs)
  );

  //   F[endpoint_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_stall_endpoint_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_stall_we),
    .wd     (in_stall_endpoint_7_wd),

    // from internal hardware
    .de     (hw2reg.in_stall[7].de),
    .d      (hw2reg.in_stall[7].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_stall[7].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_stall_endpoint_7_qs)
  );

  //   F[endpoint_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_stall_endpoint_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_stall_we),
    .wd     (in_stall_endpoint_8_wd),

    // from internal hardware
    .de     (hw2reg.in_stall[8].de),
    .d      (hw2reg.in_stall[8].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_stall[8].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_stall_endpoint_8_qs)
  );

  //   F[endpoint_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_stall_endpoint_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_stall_we),
    .wd     (in_stall_endpoint_9_wd),

    // from internal hardware
    .de     (hw2reg.in_stall[9].de),
    .d      (hw2reg.in_stall[9].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_stall[9].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_stall_endpoint_9_qs)
  );

  //   F[endpoint_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_stall_endpoint_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_stall_we),
    .wd     (in_stall_endpoint_10_wd),

    // from internal hardware
    .de     (hw2reg.in_stall[10].de),
    .d      (hw2reg.in_stall[10].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_stall[10].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_stall_endpoint_10_qs)
  );

  //   F[endpoint_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_stall_endpoint_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_stall_we),
    .wd     (in_stall_endpoint_11_wd),

    // from internal hardware
    .de     (hw2reg.in_stall[11].de),
    .d      (hw2reg.in_stall[11].d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_stall[11].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_stall_endpoint_11_qs)
  );


  // Subregister 0 of Multireg configin
  // R[configin_0]: V(False)
  //   F[buffer_0]: 4:0
  prim_subreg #(
    .DW      (5),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (5'h0)
  ) u_configin_0_buffer_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_0_we),
    .wd     (configin_0_buffer_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[0].buffer.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_0_buffer_0_qs)
  );

  //   F[size_0]: 14:8
  prim_subreg #(
    .DW      (7),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (7'h0)
  ) u_configin_0_size_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_0_we),
    .wd     (configin_0_size_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[0].size.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_0_size_0_qs)
  );

  //   F[pend_0]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_configin_0_pend_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_0_we),
    .wd     (configin_0_pend_0_wd),

    // from internal hardware
    .de     (hw2reg.configin[0].pend.de),
    .d      (hw2reg.configin[0].pend.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[0].pend.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_0_pend_0_qs)
  );

  //   F[rdy_0]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_configin_0_rdy_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_0_we),
    .wd     (configin_0_rdy_0_wd),

    // from internal hardware
    .de     (hw2reg.configin[0].rdy.de),
    .d      (hw2reg.configin[0].rdy.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[0].rdy.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_0_rdy_0_qs)
  );


  // Subregister 1 of Multireg configin
  // R[configin_1]: V(False)
  //   F[buffer_1]: 4:0
  prim_subreg #(
    .DW      (5),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (5'h0)
  ) u_configin_1_buffer_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_1_we),
    .wd     (configin_1_buffer_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[1].buffer.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_1_buffer_1_qs)
  );

  //   F[size_1]: 14:8
  prim_subreg #(
    .DW      (7),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (7'h0)
  ) u_configin_1_size_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_1_we),
    .wd     (configin_1_size_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[1].size.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_1_size_1_qs)
  );

  //   F[pend_1]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_configin_1_pend_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_1_we),
    .wd     (configin_1_pend_1_wd),

    // from internal hardware
    .de     (hw2reg.configin[1].pend.de),
    .d      (hw2reg.configin[1].pend.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[1].pend.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_1_pend_1_qs)
  );

  //   F[rdy_1]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_configin_1_rdy_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_1_we),
    .wd     (configin_1_rdy_1_wd),

    // from internal hardware
    .de     (hw2reg.configin[1].rdy.de),
    .d      (hw2reg.configin[1].rdy.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[1].rdy.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_1_rdy_1_qs)
  );


  // Subregister 2 of Multireg configin
  // R[configin_2]: V(False)
  //   F[buffer_2]: 4:0
  prim_subreg #(
    .DW      (5),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (5'h0)
  ) u_configin_2_buffer_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_2_we),
    .wd     (configin_2_buffer_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[2].buffer.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_2_buffer_2_qs)
  );

  //   F[size_2]: 14:8
  prim_subreg #(
    .DW      (7),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (7'h0)
  ) u_configin_2_size_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_2_we),
    .wd     (configin_2_size_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[2].size.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_2_size_2_qs)
  );

  //   F[pend_2]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_configin_2_pend_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_2_we),
    .wd     (configin_2_pend_2_wd),

    // from internal hardware
    .de     (hw2reg.configin[2].pend.de),
    .d      (hw2reg.configin[2].pend.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[2].pend.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_2_pend_2_qs)
  );

  //   F[rdy_2]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_configin_2_rdy_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_2_we),
    .wd     (configin_2_rdy_2_wd),

    // from internal hardware
    .de     (hw2reg.configin[2].rdy.de),
    .d      (hw2reg.configin[2].rdy.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[2].rdy.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_2_rdy_2_qs)
  );


  // Subregister 3 of Multireg configin
  // R[configin_3]: V(False)
  //   F[buffer_3]: 4:0
  prim_subreg #(
    .DW      (5),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (5'h0)
  ) u_configin_3_buffer_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_3_we),
    .wd     (configin_3_buffer_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[3].buffer.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_3_buffer_3_qs)
  );

  //   F[size_3]: 14:8
  prim_subreg #(
    .DW      (7),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (7'h0)
  ) u_configin_3_size_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_3_we),
    .wd     (configin_3_size_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[3].size.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_3_size_3_qs)
  );

  //   F[pend_3]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_configin_3_pend_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_3_we),
    .wd     (configin_3_pend_3_wd),

    // from internal hardware
    .de     (hw2reg.configin[3].pend.de),
    .d      (hw2reg.configin[3].pend.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[3].pend.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_3_pend_3_qs)
  );

  //   F[rdy_3]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_configin_3_rdy_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_3_we),
    .wd     (configin_3_rdy_3_wd),

    // from internal hardware
    .de     (hw2reg.configin[3].rdy.de),
    .d      (hw2reg.configin[3].rdy.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[3].rdy.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_3_rdy_3_qs)
  );


  // Subregister 4 of Multireg configin
  // R[configin_4]: V(False)
  //   F[buffer_4]: 4:0
  prim_subreg #(
    .DW      (5),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (5'h0)
  ) u_configin_4_buffer_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_4_we),
    .wd     (configin_4_buffer_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[4].buffer.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_4_buffer_4_qs)
  );

  //   F[size_4]: 14:8
  prim_subreg #(
    .DW      (7),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (7'h0)
  ) u_configin_4_size_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_4_we),
    .wd     (configin_4_size_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[4].size.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_4_size_4_qs)
  );

  //   F[pend_4]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_configin_4_pend_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_4_we),
    .wd     (configin_4_pend_4_wd),

    // from internal hardware
    .de     (hw2reg.configin[4].pend.de),
    .d      (hw2reg.configin[4].pend.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[4].pend.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_4_pend_4_qs)
  );

  //   F[rdy_4]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_configin_4_rdy_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_4_we),
    .wd     (configin_4_rdy_4_wd),

    // from internal hardware
    .de     (hw2reg.configin[4].rdy.de),
    .d      (hw2reg.configin[4].rdy.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[4].rdy.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_4_rdy_4_qs)
  );


  // Subregister 5 of Multireg configin
  // R[configin_5]: V(False)
  //   F[buffer_5]: 4:0
  prim_subreg #(
    .DW      (5),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (5'h0)
  ) u_configin_5_buffer_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_5_we),
    .wd     (configin_5_buffer_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[5].buffer.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_5_buffer_5_qs)
  );

  //   F[size_5]: 14:8
  prim_subreg #(
    .DW      (7),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (7'h0)
  ) u_configin_5_size_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_5_we),
    .wd     (configin_5_size_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[5].size.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_5_size_5_qs)
  );

  //   F[pend_5]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_configin_5_pend_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_5_we),
    .wd     (configin_5_pend_5_wd),

    // from internal hardware
    .de     (hw2reg.configin[5].pend.de),
    .d      (hw2reg.configin[5].pend.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[5].pend.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_5_pend_5_qs)
  );

  //   F[rdy_5]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_configin_5_rdy_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_5_we),
    .wd     (configin_5_rdy_5_wd),

    // from internal hardware
    .de     (hw2reg.configin[5].rdy.de),
    .d      (hw2reg.configin[5].rdy.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[5].rdy.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_5_rdy_5_qs)
  );


  // Subregister 6 of Multireg configin
  // R[configin_6]: V(False)
  //   F[buffer_6]: 4:0
  prim_subreg #(
    .DW      (5),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (5'h0)
  ) u_configin_6_buffer_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_6_we),
    .wd     (configin_6_buffer_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[6].buffer.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_6_buffer_6_qs)
  );

  //   F[size_6]: 14:8
  prim_subreg #(
    .DW      (7),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (7'h0)
  ) u_configin_6_size_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_6_we),
    .wd     (configin_6_size_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[6].size.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_6_size_6_qs)
  );

  //   F[pend_6]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_configin_6_pend_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_6_we),
    .wd     (configin_6_pend_6_wd),

    // from internal hardware
    .de     (hw2reg.configin[6].pend.de),
    .d      (hw2reg.configin[6].pend.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[6].pend.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_6_pend_6_qs)
  );

  //   F[rdy_6]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_configin_6_rdy_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_6_we),
    .wd     (configin_6_rdy_6_wd),

    // from internal hardware
    .de     (hw2reg.configin[6].rdy.de),
    .d      (hw2reg.configin[6].rdy.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[6].rdy.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_6_rdy_6_qs)
  );


  // Subregister 7 of Multireg configin
  // R[configin_7]: V(False)
  //   F[buffer_7]: 4:0
  prim_subreg #(
    .DW      (5),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (5'h0)
  ) u_configin_7_buffer_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_7_we),
    .wd     (configin_7_buffer_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[7].buffer.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_7_buffer_7_qs)
  );

  //   F[size_7]: 14:8
  prim_subreg #(
    .DW      (7),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (7'h0)
  ) u_configin_7_size_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_7_we),
    .wd     (configin_7_size_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[7].size.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_7_size_7_qs)
  );

  //   F[pend_7]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_configin_7_pend_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_7_we),
    .wd     (configin_7_pend_7_wd),

    // from internal hardware
    .de     (hw2reg.configin[7].pend.de),
    .d      (hw2reg.configin[7].pend.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[7].pend.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_7_pend_7_qs)
  );

  //   F[rdy_7]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_configin_7_rdy_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_7_we),
    .wd     (configin_7_rdy_7_wd),

    // from internal hardware
    .de     (hw2reg.configin[7].rdy.de),
    .d      (hw2reg.configin[7].rdy.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[7].rdy.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_7_rdy_7_qs)
  );


  // Subregister 8 of Multireg configin
  // R[configin_8]: V(False)
  //   F[buffer_8]: 4:0
  prim_subreg #(
    .DW      (5),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (5'h0)
  ) u_configin_8_buffer_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_8_we),
    .wd     (configin_8_buffer_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[8].buffer.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_8_buffer_8_qs)
  );

  //   F[size_8]: 14:8
  prim_subreg #(
    .DW      (7),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (7'h0)
  ) u_configin_8_size_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_8_we),
    .wd     (configin_8_size_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[8].size.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_8_size_8_qs)
  );

  //   F[pend_8]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_configin_8_pend_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_8_we),
    .wd     (configin_8_pend_8_wd),

    // from internal hardware
    .de     (hw2reg.configin[8].pend.de),
    .d      (hw2reg.configin[8].pend.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[8].pend.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_8_pend_8_qs)
  );

  //   F[rdy_8]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_configin_8_rdy_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_8_we),
    .wd     (configin_8_rdy_8_wd),

    // from internal hardware
    .de     (hw2reg.configin[8].rdy.de),
    .d      (hw2reg.configin[8].rdy.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[8].rdy.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_8_rdy_8_qs)
  );


  // Subregister 9 of Multireg configin
  // R[configin_9]: V(False)
  //   F[buffer_9]: 4:0
  prim_subreg #(
    .DW      (5),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (5'h0)
  ) u_configin_9_buffer_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_9_we),
    .wd     (configin_9_buffer_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[9].buffer.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_9_buffer_9_qs)
  );

  //   F[size_9]: 14:8
  prim_subreg #(
    .DW      (7),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (7'h0)
  ) u_configin_9_size_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_9_we),
    .wd     (configin_9_size_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[9].size.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_9_size_9_qs)
  );

  //   F[pend_9]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_configin_9_pend_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_9_we),
    .wd     (configin_9_pend_9_wd),

    // from internal hardware
    .de     (hw2reg.configin[9].pend.de),
    .d      (hw2reg.configin[9].pend.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[9].pend.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_9_pend_9_qs)
  );

  //   F[rdy_9]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_configin_9_rdy_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_9_we),
    .wd     (configin_9_rdy_9_wd),

    // from internal hardware
    .de     (hw2reg.configin[9].rdy.de),
    .d      (hw2reg.configin[9].rdy.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[9].rdy.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_9_rdy_9_qs)
  );


  // Subregister 10 of Multireg configin
  // R[configin_10]: V(False)
  //   F[buffer_10]: 4:0
  prim_subreg #(
    .DW      (5),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (5'h0)
  ) u_configin_10_buffer_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_10_we),
    .wd     (configin_10_buffer_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[10].buffer.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_10_buffer_10_qs)
  );

  //   F[size_10]: 14:8
  prim_subreg #(
    .DW      (7),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (7'h0)
  ) u_configin_10_size_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_10_we),
    .wd     (configin_10_size_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[10].size.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_10_size_10_qs)
  );

  //   F[pend_10]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_configin_10_pend_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_10_we),
    .wd     (configin_10_pend_10_wd),

    // from internal hardware
    .de     (hw2reg.configin[10].pend.de),
    .d      (hw2reg.configin[10].pend.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[10].pend.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_10_pend_10_qs)
  );

  //   F[rdy_10]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_configin_10_rdy_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_10_we),
    .wd     (configin_10_rdy_10_wd),

    // from internal hardware
    .de     (hw2reg.configin[10].rdy.de),
    .d      (hw2reg.configin[10].rdy.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[10].rdy.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_10_rdy_10_qs)
  );


  // Subregister 11 of Multireg configin
  // R[configin_11]: V(False)
  //   F[buffer_11]: 4:0
  prim_subreg #(
    .DW      (5),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (5'h0)
  ) u_configin_11_buffer_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_11_we),
    .wd     (configin_11_buffer_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[11].buffer.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_11_buffer_11_qs)
  );

  //   F[size_11]: 14:8
  prim_subreg #(
    .DW      (7),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (7'h0)
  ) u_configin_11_size_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_11_we),
    .wd     (configin_11_size_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[11].size.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_11_size_11_qs)
  );

  //   F[pend_11]: 30:30
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessW1C),
    .RESVAL  (1'h0)
  ) u_configin_11_pend_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_11_we),
    .wd     (configin_11_pend_11_wd),

    // from internal hardware
    .de     (hw2reg.configin[11].pend.de),
    .d      (hw2reg.configin[11].pend.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[11].pend.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_11_pend_11_qs)
  );

  //   F[rdy_11]: 31:31
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_configin_11_rdy_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (configin_11_we),
    .wd     (configin_11_rdy_11_wd),

    // from internal hardware
    .de     (hw2reg.configin[11].rdy.de),
    .d      (hw2reg.configin[11].rdy.d),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.configin[11].rdy.q),
    .ds     (),

    // to register interface (read)
    .qs     (configin_11_rdy_11_qs)
  );


  // Subregister 0 of Multireg out_iso
  // R[out_iso]: V(False)
  //   F[iso_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_iso_iso_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_iso_we),
    .wd     (out_iso_iso_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_iso[0].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_iso_iso_0_qs)
  );

  //   F[iso_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_iso_iso_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_iso_we),
    .wd     (out_iso_iso_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_iso[1].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_iso_iso_1_qs)
  );

  //   F[iso_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_iso_iso_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_iso_we),
    .wd     (out_iso_iso_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_iso[2].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_iso_iso_2_qs)
  );

  //   F[iso_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_iso_iso_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_iso_we),
    .wd     (out_iso_iso_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_iso[3].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_iso_iso_3_qs)
  );

  //   F[iso_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_iso_iso_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_iso_we),
    .wd     (out_iso_iso_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_iso[4].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_iso_iso_4_qs)
  );

  //   F[iso_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_iso_iso_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_iso_we),
    .wd     (out_iso_iso_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_iso[5].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_iso_iso_5_qs)
  );

  //   F[iso_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_iso_iso_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_iso_we),
    .wd     (out_iso_iso_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_iso[6].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_iso_iso_6_qs)
  );

  //   F[iso_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_iso_iso_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_iso_we),
    .wd     (out_iso_iso_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_iso[7].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_iso_iso_7_qs)
  );

  //   F[iso_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_iso_iso_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_iso_we),
    .wd     (out_iso_iso_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_iso[8].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_iso_iso_8_qs)
  );

  //   F[iso_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_iso_iso_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_iso_we),
    .wd     (out_iso_iso_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_iso[9].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_iso_iso_9_qs)
  );

  //   F[iso_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_iso_iso_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_iso_we),
    .wd     (out_iso_iso_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_iso[10].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_iso_iso_10_qs)
  );

  //   F[iso_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_out_iso_iso_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (out_iso_we),
    .wd     (out_iso_iso_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.out_iso[11].q),
    .ds     (),

    // to register interface (read)
    .qs     (out_iso_iso_11_qs)
  );


  // Subregister 0 of Multireg in_iso
  // R[in_iso]: V(False)
  //   F[iso_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_iso_iso_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_iso_we),
    .wd     (in_iso_iso_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_iso[0].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_iso_iso_0_qs)
  );

  //   F[iso_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_iso_iso_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_iso_we),
    .wd     (in_iso_iso_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_iso[1].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_iso_iso_1_qs)
  );

  //   F[iso_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_iso_iso_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_iso_we),
    .wd     (in_iso_iso_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_iso[2].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_iso_iso_2_qs)
  );

  //   F[iso_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_iso_iso_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_iso_we),
    .wd     (in_iso_iso_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_iso[3].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_iso_iso_3_qs)
  );

  //   F[iso_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_iso_iso_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_iso_we),
    .wd     (in_iso_iso_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_iso[4].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_iso_iso_4_qs)
  );

  //   F[iso_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_iso_iso_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_iso_we),
    .wd     (in_iso_iso_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_iso[5].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_iso_iso_5_qs)
  );

  //   F[iso_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_iso_iso_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_iso_we),
    .wd     (in_iso_iso_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_iso[6].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_iso_iso_6_qs)
  );

  //   F[iso_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_iso_iso_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_iso_we),
    .wd     (in_iso_iso_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_iso[7].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_iso_iso_7_qs)
  );

  //   F[iso_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_iso_iso_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_iso_we),
    .wd     (in_iso_iso_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_iso[8].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_iso_iso_8_qs)
  );

  //   F[iso_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_iso_iso_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_iso_we),
    .wd     (in_iso_iso_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_iso[9].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_iso_iso_9_qs)
  );

  //   F[iso_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_iso_iso_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_iso_we),
    .wd     (in_iso_iso_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_iso[10].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_iso_iso_10_qs)
  );

  //   F[iso_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_in_iso_iso_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (in_iso_we),
    .wd     (in_iso_iso_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.in_iso[11].q),
    .ds     (),

    // to register interface (read)
    .qs     (in_iso_iso_11_qs)
  );


  // Subregister 0 of Multireg data_toggle_clear
  // R[data_toggle_clear]: V(False)
  logic data_toggle_clear_qe;
  logic [11:0] data_toggle_clear_flds_we;
  prim_flop #(
    .Width(1),
    .ResetValue(0)
  ) u_data_toggle_clear0_qe (
    .clk_i(clk_i),
    .rst_ni(rst_ni),
    .d_i(&data_toggle_clear_flds_we),
    .q_o(data_toggle_clear_qe)
  );
  //   F[clear_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessWO),
    .RESVAL  (1'h0)
  ) u_data_toggle_clear_clear_0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (data_toggle_clear_we),
    .wd     (data_toggle_clear_clear_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (data_toggle_clear_flds_we[0]),
    .q      (reg2hw.data_toggle_clear[0].q),
    .ds     (),

    // to register interface (read)
    .qs     ()
  );
  assign reg2hw.data_toggle_clear[0].qe = data_toggle_clear_qe;

  //   F[clear_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessWO),
    .RESVAL  (1'h0)
  ) u_data_toggle_clear_clear_1 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (data_toggle_clear_we),
    .wd     (data_toggle_clear_clear_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (data_toggle_clear_flds_we[1]),
    .q      (reg2hw.data_toggle_clear[1].q),
    .ds     (),

    // to register interface (read)
    .qs     ()
  );
  assign reg2hw.data_toggle_clear[1].qe = data_toggle_clear_qe;

  //   F[clear_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessWO),
    .RESVAL  (1'h0)
  ) u_data_toggle_clear_clear_2 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (data_toggle_clear_we),
    .wd     (data_toggle_clear_clear_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (data_toggle_clear_flds_we[2]),
    .q      (reg2hw.data_toggle_clear[2].q),
    .ds     (),

    // to register interface (read)
    .qs     ()
  );
  assign reg2hw.data_toggle_clear[2].qe = data_toggle_clear_qe;

  //   F[clear_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessWO),
    .RESVAL  (1'h0)
  ) u_data_toggle_clear_clear_3 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (data_toggle_clear_we),
    .wd     (data_toggle_clear_clear_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (data_toggle_clear_flds_we[3]),
    .q      (reg2hw.data_toggle_clear[3].q),
    .ds     (),

    // to register interface (read)
    .qs     ()
  );
  assign reg2hw.data_toggle_clear[3].qe = data_toggle_clear_qe;

  //   F[clear_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessWO),
    .RESVAL  (1'h0)
  ) u_data_toggle_clear_clear_4 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (data_toggle_clear_we),
    .wd     (data_toggle_clear_clear_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (data_toggle_clear_flds_we[4]),
    .q      (reg2hw.data_toggle_clear[4].q),
    .ds     (),

    // to register interface (read)
    .qs     ()
  );
  assign reg2hw.data_toggle_clear[4].qe = data_toggle_clear_qe;

  //   F[clear_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessWO),
    .RESVAL  (1'h0)
  ) u_data_toggle_clear_clear_5 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (data_toggle_clear_we),
    .wd     (data_toggle_clear_clear_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (data_toggle_clear_flds_we[5]),
    .q      (reg2hw.data_toggle_clear[5].q),
    .ds     (),

    // to register interface (read)
    .qs     ()
  );
  assign reg2hw.data_toggle_clear[5].qe = data_toggle_clear_qe;

  //   F[clear_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessWO),
    .RESVAL  (1'h0)
  ) u_data_toggle_clear_clear_6 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (data_toggle_clear_we),
    .wd     (data_toggle_clear_clear_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (data_toggle_clear_flds_we[6]),
    .q      (reg2hw.data_toggle_clear[6].q),
    .ds     (),

    // to register interface (read)
    .qs     ()
  );
  assign reg2hw.data_toggle_clear[6].qe = data_toggle_clear_qe;

  //   F[clear_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessWO),
    .RESVAL  (1'h0)
  ) u_data_toggle_clear_clear_7 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (data_toggle_clear_we),
    .wd     (data_toggle_clear_clear_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (data_toggle_clear_flds_we[7]),
    .q      (reg2hw.data_toggle_clear[7].q),
    .ds     (),

    // to register interface (read)
    .qs     ()
  );
  assign reg2hw.data_toggle_clear[7].qe = data_toggle_clear_qe;

  //   F[clear_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessWO),
    .RESVAL  (1'h0)
  ) u_data_toggle_clear_clear_8 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (data_toggle_clear_we),
    .wd     (data_toggle_clear_clear_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (data_toggle_clear_flds_we[8]),
    .q      (reg2hw.data_toggle_clear[8].q),
    .ds     (),

    // to register interface (read)
    .qs     ()
  );
  assign reg2hw.data_toggle_clear[8].qe = data_toggle_clear_qe;

  //   F[clear_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessWO),
    .RESVAL  (1'h0)
  ) u_data_toggle_clear_clear_9 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (data_toggle_clear_we),
    .wd     (data_toggle_clear_clear_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (data_toggle_clear_flds_we[9]),
    .q      (reg2hw.data_toggle_clear[9].q),
    .ds     (),

    // to register interface (read)
    .qs     ()
  );
  assign reg2hw.data_toggle_clear[9].qe = data_toggle_clear_qe;

  //   F[clear_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessWO),
    .RESVAL  (1'h0)
  ) u_data_toggle_clear_clear_10 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (data_toggle_clear_we),
    .wd     (data_toggle_clear_clear_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (data_toggle_clear_flds_we[10]),
    .q      (reg2hw.data_toggle_clear[10].q),
    .ds     (),

    // to register interface (read)
    .qs     ()
  );
  assign reg2hw.data_toggle_clear[10].qe = data_toggle_clear_qe;

  //   F[clear_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessWO),
    .RESVAL  (1'h0)
  ) u_data_toggle_clear_clear_11 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (data_toggle_clear_we),
    .wd     (data_toggle_clear_clear_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (data_toggle_clear_flds_we[11]),
    .q      (reg2hw.data_toggle_clear[11].q),
    .ds     (),

    // to register interface (read)
    .qs     ()
  );
  assign reg2hw.data_toggle_clear[11].qe = data_toggle_clear_qe;


  // R[phy_pins_sense]: V(True)
  //   F[rx_dp_i]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_phy_pins_sense_rx_dp_i (
    .re     (phy_pins_sense_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.phy_pins_sense.rx_dp_i.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (phy_pins_sense_rx_dp_i_qs)
  );

  //   F[rx_dn_i]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_phy_pins_sense_rx_dn_i (
    .re     (phy_pins_sense_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.phy_pins_sense.rx_dn_i.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (phy_pins_sense_rx_dn_i_qs)
  );

  //   F[rx_d_i]: 2:2
  prim_subreg_ext #(
    .DW    (1)
  ) u_phy_pins_sense_rx_d_i (
    .re     (phy_pins_sense_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.phy_pins_sense.rx_d_i.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (phy_pins_sense_rx_d_i_qs)
  );

  //   F[tx_dp_o]: 8:8
  prim_subreg_ext #(
    .DW    (1)
  ) u_phy_pins_sense_tx_dp_o (
    .re     (phy_pins_sense_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.phy_pins_sense.tx_dp_o.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (phy_pins_sense_tx_dp_o_qs)
  );

  //   F[tx_dn_o]: 9:9
  prim_subreg_ext #(
    .DW    (1)
  ) u_phy_pins_sense_tx_dn_o (
    .re     (phy_pins_sense_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.phy_pins_sense.tx_dn_o.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (phy_pins_sense_tx_dn_o_qs)
  );

  //   F[tx_d_o]: 10:10
  prim_subreg_ext #(
    .DW    (1)
  ) u_phy_pins_sense_tx_d_o (
    .re     (phy_pins_sense_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.phy_pins_sense.tx_d_o.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (phy_pins_sense_tx_d_o_qs)
  );

  //   F[tx_se0_o]: 11:11
  prim_subreg_ext #(
    .DW    (1)
  ) u_phy_pins_sense_tx_se0_o (
    .re     (phy_pins_sense_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.phy_pins_sense.tx_se0_o.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (phy_pins_sense_tx_se0_o_qs)
  );

  //   F[tx_oe_o]: 12:12
  prim_subreg_ext #(
    .DW    (1)
  ) u_phy_pins_sense_tx_oe_o (
    .re     (phy_pins_sense_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.phy_pins_sense.tx_oe_o.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (phy_pins_sense_tx_oe_o_qs)
  );

  //   F[pwr_sense]: 16:16
  prim_subreg_ext #(
    .DW    (1)
  ) u_phy_pins_sense_pwr_sense (
    .re     (phy_pins_sense_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.phy_pins_sense.pwr_sense.d),
    .qre    (),
    .qe     (),
    .q      (),
    .ds     (),
    .qs     (phy_pins_sense_pwr_sense_qs)
  );


  // R[phy_pins_drive]: V(False)
  //   F[dp_o]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_phy_pins_drive_dp_o (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (phy_pins_drive_we),
    .wd     (phy_pins_drive_dp_o_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.phy_pins_drive.dp_o.q),
    .ds     (),

    // to register interface (read)
    .qs     (phy_pins_drive_dp_o_qs)
  );

  //   F[dn_o]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_phy_pins_drive_dn_o (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (phy_pins_drive_we),
    .wd     (phy_pins_drive_dn_o_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.phy_pins_drive.dn_o.q),
    .ds     (),

    // to register interface (read)
    .qs     (phy_pins_drive_dn_o_qs)
  );

  //   F[d_o]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_phy_pins_drive_d_o (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (phy_pins_drive_we),
    .wd     (phy_pins_drive_d_o_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.phy_pins_drive.d_o.q),
    .ds     (),

    // to register interface (read)
    .qs     (phy_pins_drive_d_o_qs)
  );

  //   F[se0_o]: 3:3
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_phy_pins_drive_se0_o (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (phy_pins_drive_we),
    .wd     (phy_pins_drive_se0_o_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.phy_pins_drive.se0_o.q),
    .ds     (),

    // to register interface (read)
    .qs     (phy_pins_drive_se0_o_qs)
  );

  //   F[oe_o]: 4:4
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_phy_pins_drive_oe_o (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (phy_pins_drive_we),
    .wd     (phy_pins_drive_oe_o_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.phy_pins_drive.oe_o.q),
    .ds     (),

    // to register interface (read)
    .qs     (phy_pins_drive_oe_o_qs)
  );

  //   F[rx_enable_o]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_phy_pins_drive_rx_enable_o (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (phy_pins_drive_we),
    .wd     (phy_pins_drive_rx_enable_o_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.phy_pins_drive.rx_enable_o.q),
    .ds     (),

    // to register interface (read)
    .qs     (phy_pins_drive_rx_enable_o_qs)
  );

  //   F[dp_pullup_en_o]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_phy_pins_drive_dp_pullup_en_o (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (phy_pins_drive_we),
    .wd     (phy_pins_drive_dp_pullup_en_o_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.phy_pins_drive.dp_pullup_en_o.q),
    .ds     (),

    // to register interface (read)
    .qs     (phy_pins_drive_dp_pullup_en_o_qs)
  );

  //   F[dn_pullup_en_o]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_phy_pins_drive_dn_pullup_en_o (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (phy_pins_drive_we),
    .wd     (phy_pins_drive_dn_pullup_en_o_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.phy_pins_drive.dn_pullup_en_o.q),
    .ds     (),

    // to register interface (read)
    .qs     (phy_pins_drive_dn_pullup_en_o_qs)
  );

  //   F[en]: 16:16
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_phy_pins_drive_en (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (phy_pins_drive_we),
    .wd     (phy_pins_drive_en_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.phy_pins_drive.en.q),
    .ds     (),

    // to register interface (read)
    .qs     (phy_pins_drive_en_qs)
  );


  // R[phy_config]: V(False)
  //   F[use_diff_rcvr]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_phy_config_use_diff_rcvr (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (phy_config_we),
    .wd     (phy_config_use_diff_rcvr_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.phy_config.use_diff_rcvr.q),
    .ds     (),

    // to register interface (read)
    .qs     (phy_config_use_diff_rcvr_qs)
  );

  //   F[tx_use_d_se0]: 1:1
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_phy_config_tx_use_d_se0 (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (phy_config_we),
    .wd     (phy_config_tx_use_d_se0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.phy_config.tx_use_d_se0.q),
    .ds     (),

    // to register interface (read)
    .qs     (phy_config_tx_use_d_se0_qs)
  );

  //   F[eop_single_bit]: 2:2
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h1)
  ) u_phy_config_eop_single_bit (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (phy_config_we),
    .wd     (phy_config_eop_single_bit_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.phy_config.eop_single_bit.q),
    .ds     (),

    // to register interface (read)
    .qs     (phy_config_eop_single_bit_qs)
  );

  //   F[pinflip]: 5:5
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_phy_config_pinflip (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (phy_config_we),
    .wd     (phy_config_pinflip_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.phy_config.pinflip.q),
    .ds     (),

    // to register interface (read)
    .qs     (phy_config_pinflip_qs)
  );

  //   F[usb_ref_disable]: 6:6
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_phy_config_usb_ref_disable (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (phy_config_we),
    .wd     (phy_config_usb_ref_disable_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.phy_config.usb_ref_disable.q),
    .ds     (),

    // to register interface (read)
    .qs     (phy_config_usb_ref_disable_qs)
  );

  //   F[tx_osc_test_mode]: 7:7
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRW),
    .RESVAL  (1'h0)
  ) u_phy_config_tx_osc_test_mode (
    .clk_i   (clk_i),
    .rst_ni  (rst_ni),

    // from register interface
    .we     (phy_config_we),
    .wd     (phy_config_tx_osc_test_mode_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.phy_config.tx_osc_test_mode.q),
    .ds     (),

    // to register interface (read)
    .qs     (phy_config_tx_osc_test_mode_qs)
  );


  // R[wake_control]: V(True)
  logic wake_control_qe;
  logic [1:0] wake_control_flds_we;
  assign wake_control_qe = &wake_control_flds_we;
  //   F[suspend_req]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_wake_control_suspend_req (
    .re     (1'b0),
    .we     (aon_wake_control_we),
    .wd     (aon_wake_control_wdata[0]),
    .d      ('0),
    .qre    (),
    .qe     (wake_control_flds_we[0]),
    .q      (reg2hw.wake_control.suspend_req.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.wake_control.suspend_req.qe = wake_control_qe;

  //   F[wake_ack]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_wake_control_wake_ack (
    .re     (1'b0),
    .we     (aon_wake_control_we),
    .wd     (aon_wake_control_wdata[1]),
    .d      ('0),
    .qre    (),
    .qe     (wake_control_flds_we[1]),
    .q      (reg2hw.wake_control.wake_ack.q),
    .ds     (),
    .qs     ()
  );
  assign reg2hw.wake_control.wake_ack.qe = wake_control_qe;


  // R[wake_events]: V(False)
  logic [2:0] wake_events_flds_we;
  assign aon_wake_events_qe = |wake_events_flds_we;
  //   F[module_active]: 0:0
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (1'h0)
  ) u_wake_events_module_active (
    .clk_i   (clk_aon_i),
    .rst_ni  (rst_aon_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.wake_events.module_active.de),
    .d      (hw2reg.wake_events.module_active.d),

    // to internal hardware
    .qe     (wake_events_flds_we[0]),
    .q      (),
    .ds     (aon_wake_events_module_active_ds_int),

    // to register interface (read)
    .qs     (aon_wake_events_module_active_qs_int)
  );

  //   F[disconnected]: 8:8
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (1'h0)
  ) u_wake_events_disconnected (
    .clk_i   (clk_aon_i),
    .rst_ni  (rst_aon_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.wake_events.disconnected.de),
    .d      (hw2reg.wake_events.disconnected.d),

    // to internal hardware
    .qe     (wake_events_flds_we[1]),
    .q      (),
    .ds     (aon_wake_events_disconnected_ds_int),

    // to register interface (read)
    .qs     (aon_wake_events_disconnected_qs_int)
  );

  //   F[bus_reset]: 9:9
  prim_subreg #(
    .DW      (1),
    .SwAccess(prim_subreg_pkg::SwAccessRO),
    .RESVAL  (1'h0)
  ) u_wake_events_bus_reset (
    .clk_i   (clk_aon_i),
    .rst_ni  (rst_aon_ni),

    // from register interface
    .we     (1'b0),
    .wd     ('0),

    // from internal hardware
    .de     (hw2reg.wake_events.bus_reset.de),
    .d      (hw2reg.wake_events.bus_reset.d),

    // to internal hardware
    .qe     (wake_events_flds_we[2]),
    .q      (),
    .ds     (aon_wake_events_bus_reset_ds_int),

    // to register interface (read)
    .qs     (aon_wake_events_bus_reset_qs_int)
  );



  logic [35:0] addr_hit;
  always_comb begin
    addr_hit = '0;
    addr_hit[ 0] = (reg_addr == USBDEV_INTR_STATE_OFFSET);
    addr_hit[ 1] = (reg_addr == USBDEV_INTR_ENABLE_OFFSET);
    addr_hit[ 2] = (reg_addr == USBDEV_INTR_TEST_OFFSET);
    addr_hit[ 3] = (reg_addr == USBDEV_ALERT_TEST_OFFSET);
    addr_hit[ 4] = (reg_addr == USBDEV_USBCTRL_OFFSET);
    addr_hit[ 5] = (reg_addr == USBDEV_EP_OUT_ENABLE_OFFSET);
    addr_hit[ 6] = (reg_addr == USBDEV_EP_IN_ENABLE_OFFSET);
    addr_hit[ 7] = (reg_addr == USBDEV_USBSTAT_OFFSET);
    addr_hit[ 8] = (reg_addr == USBDEV_AVBUFFER_OFFSET);
    addr_hit[ 9] = (reg_addr == USBDEV_RXFIFO_OFFSET);
    addr_hit[10] = (reg_addr == USBDEV_RXENABLE_SETUP_OFFSET);
    addr_hit[11] = (reg_addr == USBDEV_RXENABLE_OUT_OFFSET);
    addr_hit[12] = (reg_addr == USBDEV_SET_NAK_OUT_OFFSET);
    addr_hit[13] = (reg_addr == USBDEV_IN_SENT_OFFSET);
    addr_hit[14] = (reg_addr == USBDEV_OUT_STALL_OFFSET);
    addr_hit[15] = (reg_addr == USBDEV_IN_STALL_OFFSET);
    addr_hit[16] = (reg_addr == USBDEV_CONFIGIN_0_OFFSET);
    addr_hit[17] = (reg_addr == USBDEV_CONFIGIN_1_OFFSET);
    addr_hit[18] = (reg_addr == USBDEV_CONFIGIN_2_OFFSET);
    addr_hit[19] = (reg_addr == USBDEV_CONFIGIN_3_OFFSET);
    addr_hit[20] = (reg_addr == USBDEV_CONFIGIN_4_OFFSET);
    addr_hit[21] = (reg_addr == USBDEV_CONFIGIN_5_OFFSET);
    addr_hit[22] = (reg_addr == USBDEV_CONFIGIN_6_OFFSET);
    addr_hit[23] = (reg_addr == USBDEV_CONFIGIN_7_OFFSET);
    addr_hit[24] = (reg_addr == USBDEV_CONFIGIN_8_OFFSET);
    addr_hit[25] = (reg_addr == USBDEV_CONFIGIN_9_OFFSET);
    addr_hit[26] = (reg_addr == USBDEV_CONFIGIN_10_OFFSET);
    addr_hit[27] = (reg_addr == USBDEV_CONFIGIN_11_OFFSET);
    addr_hit[28] = (reg_addr == USBDEV_OUT_ISO_OFFSET);
    addr_hit[29] = (reg_addr == USBDEV_IN_ISO_OFFSET);
    addr_hit[30] = (reg_addr == USBDEV_DATA_TOGGLE_CLEAR_OFFSET);
    addr_hit[31] = (reg_addr == USBDEV_PHY_PINS_SENSE_OFFSET);
    addr_hit[32] = (reg_addr == USBDEV_PHY_PINS_DRIVE_OFFSET);
    addr_hit[33] = (reg_addr == USBDEV_PHY_CONFIG_OFFSET);
    addr_hit[34] = (reg_addr == USBDEV_WAKE_CONTROL_OFFSET);
    addr_hit[35] = (reg_addr == USBDEV_WAKE_EVENTS_OFFSET);
  end

  assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;

  // Check sub-word write is permitted
  always_comb begin
    wr_err = (reg_we &
              ((addr_hit[ 0] & (|(USBDEV_PERMIT[ 0] & ~reg_be))) |
               (addr_hit[ 1] & (|(USBDEV_PERMIT[ 1] & ~reg_be))) |
               (addr_hit[ 2] & (|(USBDEV_PERMIT[ 2] & ~reg_be))) |
               (addr_hit[ 3] & (|(USBDEV_PERMIT[ 3] & ~reg_be))) |
               (addr_hit[ 4] & (|(USBDEV_PERMIT[ 4] & ~reg_be))) |
               (addr_hit[ 5] & (|(USBDEV_PERMIT[ 5] & ~reg_be))) |
               (addr_hit[ 6] & (|(USBDEV_PERMIT[ 6] & ~reg_be))) |
               (addr_hit[ 7] & (|(USBDEV_PERMIT[ 7] & ~reg_be))) |
               (addr_hit[ 8] & (|(USBDEV_PERMIT[ 8] & ~reg_be))) |
               (addr_hit[ 9] & (|(USBDEV_PERMIT[ 9] & ~reg_be))) |
               (addr_hit[10] & (|(USBDEV_PERMIT[10] & ~reg_be))) |
               (addr_hit[11] & (|(USBDEV_PERMIT[11] & ~reg_be))) |
               (addr_hit[12] & (|(USBDEV_PERMIT[12] & ~reg_be))) |
               (addr_hit[13] & (|(USBDEV_PERMIT[13] & ~reg_be))) |
               (addr_hit[14] & (|(USBDEV_PERMIT[14] & ~reg_be))) |
               (addr_hit[15] & (|(USBDEV_PERMIT[15] & ~reg_be))) |
               (addr_hit[16] & (|(USBDEV_PERMIT[16] & ~reg_be))) |
               (addr_hit[17] & (|(USBDEV_PERMIT[17] & ~reg_be))) |
               (addr_hit[18] & (|(USBDEV_PERMIT[18] & ~reg_be))) |
               (addr_hit[19] & (|(USBDEV_PERMIT[19] & ~reg_be))) |
               (addr_hit[20] & (|(USBDEV_PERMIT[20] & ~reg_be))) |
               (addr_hit[21] & (|(USBDEV_PERMIT[21] & ~reg_be))) |
               (addr_hit[22] & (|(USBDEV_PERMIT[22] & ~reg_be))) |
               (addr_hit[23] & (|(USBDEV_PERMIT[23] & ~reg_be))) |
               (addr_hit[24] & (|(USBDEV_PERMIT[24] & ~reg_be))) |
               (addr_hit[25] & (|(USBDEV_PERMIT[25] & ~reg_be))) |
               (addr_hit[26] & (|(USBDEV_PERMIT[26] & ~reg_be))) |
               (addr_hit[27] & (|(USBDEV_PERMIT[27] & ~reg_be))) |
               (addr_hit[28] & (|(USBDEV_PERMIT[28] & ~reg_be))) |
               (addr_hit[29] & (|(USBDEV_PERMIT[29] & ~reg_be))) |
               (addr_hit[30] & (|(USBDEV_PERMIT[30] & ~reg_be))) |
               (addr_hit[31] & (|(USBDEV_PERMIT[31] & ~reg_be))) |
               (addr_hit[32] & (|(USBDEV_PERMIT[32] & ~reg_be))) |
               (addr_hit[33] & (|(USBDEV_PERMIT[33] & ~reg_be))) |
               (addr_hit[34] & (|(USBDEV_PERMIT[34] & ~reg_be))) |
               (addr_hit[35] & (|(USBDEV_PERMIT[35] & ~reg_be)))));
  end

  // Generate write-enables
  assign intr_state_we = addr_hit[0] & reg_we & !reg_error;

  assign intr_state_pkt_received_wd = reg_wdata[0];

  assign intr_state_pkt_sent_wd = reg_wdata[1];

  assign intr_state_disconnected_wd = reg_wdata[2];

  assign intr_state_host_lost_wd = reg_wdata[3];

  assign intr_state_link_reset_wd = reg_wdata[4];

  assign intr_state_link_suspend_wd = reg_wdata[5];

  assign intr_state_link_resume_wd = reg_wdata[6];

  assign intr_state_av_empty_wd = reg_wdata[7];

  assign intr_state_rx_full_wd = reg_wdata[8];

  assign intr_state_av_overflow_wd = reg_wdata[9];

  assign intr_state_link_in_err_wd = reg_wdata[10];

  assign intr_state_rx_crc_err_wd = reg_wdata[11];

  assign intr_state_rx_pid_err_wd = reg_wdata[12];

  assign intr_state_rx_bitstuff_err_wd = reg_wdata[13];

  assign intr_state_frame_wd = reg_wdata[14];

  assign intr_state_powered_wd = reg_wdata[15];

  assign intr_state_link_out_err_wd = reg_wdata[16];
  assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;

  assign intr_enable_pkt_received_wd = reg_wdata[0];

  assign intr_enable_pkt_sent_wd = reg_wdata[1];

  assign intr_enable_disconnected_wd = reg_wdata[2];

  assign intr_enable_host_lost_wd = reg_wdata[3];

  assign intr_enable_link_reset_wd = reg_wdata[4];

  assign intr_enable_link_suspend_wd = reg_wdata[5];

  assign intr_enable_link_resume_wd = reg_wdata[6];

  assign intr_enable_av_empty_wd = reg_wdata[7];

  assign intr_enable_rx_full_wd = reg_wdata[8];

  assign intr_enable_av_overflow_wd = reg_wdata[9];

  assign intr_enable_link_in_err_wd = reg_wdata[10];

  assign intr_enable_rx_crc_err_wd = reg_wdata[11];

  assign intr_enable_rx_pid_err_wd = reg_wdata[12];

  assign intr_enable_rx_bitstuff_err_wd = reg_wdata[13];

  assign intr_enable_frame_wd = reg_wdata[14];

  assign intr_enable_powered_wd = reg_wdata[15];

  assign intr_enable_link_out_err_wd = reg_wdata[16];
  assign intr_test_we = addr_hit[2] & reg_we & !reg_error;

  assign intr_test_pkt_received_wd = reg_wdata[0];

  assign intr_test_pkt_sent_wd = reg_wdata[1];

  assign intr_test_disconnected_wd = reg_wdata[2];

  assign intr_test_host_lost_wd = reg_wdata[3];

  assign intr_test_link_reset_wd = reg_wdata[4];

  assign intr_test_link_suspend_wd = reg_wdata[5];

  assign intr_test_link_resume_wd = reg_wdata[6];

  assign intr_test_av_empty_wd = reg_wdata[7];

  assign intr_test_rx_full_wd = reg_wdata[8];

  assign intr_test_av_overflow_wd = reg_wdata[9];

  assign intr_test_link_in_err_wd = reg_wdata[10];

  assign intr_test_rx_crc_err_wd = reg_wdata[11];

  assign intr_test_rx_pid_err_wd = reg_wdata[12];

  assign intr_test_rx_bitstuff_err_wd = reg_wdata[13];

  assign intr_test_frame_wd = reg_wdata[14];

  assign intr_test_powered_wd = reg_wdata[15];

  assign intr_test_link_out_err_wd = reg_wdata[16];
  assign alert_test_we = addr_hit[3] & reg_we & !reg_error;

  assign alert_test_wd = reg_wdata[0];
  assign usbctrl_we = addr_hit[4] & reg_we & !reg_error;

  assign usbctrl_enable_wd = reg_wdata[0];

  assign usbctrl_resume_link_active_wd = reg_wdata[1];

  assign usbctrl_device_address_wd = reg_wdata[22:16];
  assign ep_out_enable_we = addr_hit[5] & reg_we & !reg_error;

  assign ep_out_enable_enable_0_wd = reg_wdata[0];

  assign ep_out_enable_enable_1_wd = reg_wdata[1];

  assign ep_out_enable_enable_2_wd = reg_wdata[2];

  assign ep_out_enable_enable_3_wd = reg_wdata[3];

  assign ep_out_enable_enable_4_wd = reg_wdata[4];

  assign ep_out_enable_enable_5_wd = reg_wdata[5];

  assign ep_out_enable_enable_6_wd = reg_wdata[6];

  assign ep_out_enable_enable_7_wd = reg_wdata[7];

  assign ep_out_enable_enable_8_wd = reg_wdata[8];

  assign ep_out_enable_enable_9_wd = reg_wdata[9];

  assign ep_out_enable_enable_10_wd = reg_wdata[10];

  assign ep_out_enable_enable_11_wd = reg_wdata[11];
  assign ep_in_enable_we = addr_hit[6] & reg_we & !reg_error;

  assign ep_in_enable_enable_0_wd = reg_wdata[0];

  assign ep_in_enable_enable_1_wd = reg_wdata[1];

  assign ep_in_enable_enable_2_wd = reg_wdata[2];

  assign ep_in_enable_enable_3_wd = reg_wdata[3];

  assign ep_in_enable_enable_4_wd = reg_wdata[4];

  assign ep_in_enable_enable_5_wd = reg_wdata[5];

  assign ep_in_enable_enable_6_wd = reg_wdata[6];

  assign ep_in_enable_enable_7_wd = reg_wdata[7];

  assign ep_in_enable_enable_8_wd = reg_wdata[8];

  assign ep_in_enable_enable_9_wd = reg_wdata[9];

  assign ep_in_enable_enable_10_wd = reg_wdata[10];

  assign ep_in_enable_enable_11_wd = reg_wdata[11];
  assign usbstat_re = addr_hit[7] & reg_re & !reg_error;
  assign avbuffer_we = addr_hit[8] & reg_we & !reg_error;

  assign avbuffer_wd = reg_wdata[4:0];
  assign rxfifo_re = addr_hit[9] & reg_re & !reg_error;
  assign rxenable_setup_we = addr_hit[10] & reg_we & !reg_error;

  assign rxenable_setup_setup_0_wd = reg_wdata[0];

  assign rxenable_setup_setup_1_wd = reg_wdata[1];

  assign rxenable_setup_setup_2_wd = reg_wdata[2];

  assign rxenable_setup_setup_3_wd = reg_wdata[3];

  assign rxenable_setup_setup_4_wd = reg_wdata[4];

  assign rxenable_setup_setup_5_wd = reg_wdata[5];

  assign rxenable_setup_setup_6_wd = reg_wdata[6];

  assign rxenable_setup_setup_7_wd = reg_wdata[7];

  assign rxenable_setup_setup_8_wd = reg_wdata[8];

  assign rxenable_setup_setup_9_wd = reg_wdata[9];

  assign rxenable_setup_setup_10_wd = reg_wdata[10];

  assign rxenable_setup_setup_11_wd = reg_wdata[11];
  assign rxenable_out_we = addr_hit[11] & reg_we & !reg_error;

  assign rxenable_out_out_0_wd = reg_wdata[0];

  assign rxenable_out_out_1_wd = reg_wdata[1];

  assign rxenable_out_out_2_wd = reg_wdata[2];

  assign rxenable_out_out_3_wd = reg_wdata[3];

  assign rxenable_out_out_4_wd = reg_wdata[4];

  assign rxenable_out_out_5_wd = reg_wdata[5];

  assign rxenable_out_out_6_wd = reg_wdata[6];

  assign rxenable_out_out_7_wd = reg_wdata[7];

  assign rxenable_out_out_8_wd = reg_wdata[8];

  assign rxenable_out_out_9_wd = reg_wdata[9];

  assign rxenable_out_out_10_wd = reg_wdata[10];

  assign rxenable_out_out_11_wd = reg_wdata[11];
  assign set_nak_out_we = addr_hit[12] & reg_we & !reg_error;

  assign set_nak_out_enable_0_wd = reg_wdata[0];

  assign set_nak_out_enable_1_wd = reg_wdata[1];

  assign set_nak_out_enable_2_wd = reg_wdata[2];

  assign set_nak_out_enable_3_wd = reg_wdata[3];

  assign set_nak_out_enable_4_wd = reg_wdata[4];

  assign set_nak_out_enable_5_wd = reg_wdata[5];

  assign set_nak_out_enable_6_wd = reg_wdata[6];

  assign set_nak_out_enable_7_wd = reg_wdata[7];

  assign set_nak_out_enable_8_wd = reg_wdata[8];

  assign set_nak_out_enable_9_wd = reg_wdata[9];

  assign set_nak_out_enable_10_wd = reg_wdata[10];

  assign set_nak_out_enable_11_wd = reg_wdata[11];
  assign in_sent_we = addr_hit[13] & reg_we & !reg_error;

  assign in_sent_sent_0_wd = reg_wdata[0];

  assign in_sent_sent_1_wd = reg_wdata[1];

  assign in_sent_sent_2_wd = reg_wdata[2];

  assign in_sent_sent_3_wd = reg_wdata[3];

  assign in_sent_sent_4_wd = reg_wdata[4];

  assign in_sent_sent_5_wd = reg_wdata[5];

  assign in_sent_sent_6_wd = reg_wdata[6];

  assign in_sent_sent_7_wd = reg_wdata[7];

  assign in_sent_sent_8_wd = reg_wdata[8];

  assign in_sent_sent_9_wd = reg_wdata[9];

  assign in_sent_sent_10_wd = reg_wdata[10];

  assign in_sent_sent_11_wd = reg_wdata[11];
  assign out_stall_we = addr_hit[14] & reg_we & !reg_error;

  assign out_stall_endpoint_0_wd = reg_wdata[0];

  assign out_stall_endpoint_1_wd = reg_wdata[1];

  assign out_stall_endpoint_2_wd = reg_wdata[2];

  assign out_stall_endpoint_3_wd = reg_wdata[3];

  assign out_stall_endpoint_4_wd = reg_wdata[4];

  assign out_stall_endpoint_5_wd = reg_wdata[5];

  assign out_stall_endpoint_6_wd = reg_wdata[6];

  assign out_stall_endpoint_7_wd = reg_wdata[7];

  assign out_stall_endpoint_8_wd = reg_wdata[8];

  assign out_stall_endpoint_9_wd = reg_wdata[9];

  assign out_stall_endpoint_10_wd = reg_wdata[10];

  assign out_stall_endpoint_11_wd = reg_wdata[11];
  assign in_stall_we = addr_hit[15] & reg_we & !reg_error;

  assign in_stall_endpoint_0_wd = reg_wdata[0];

  assign in_stall_endpoint_1_wd = reg_wdata[1];

  assign in_stall_endpoint_2_wd = reg_wdata[2];

  assign in_stall_endpoint_3_wd = reg_wdata[3];

  assign in_stall_endpoint_4_wd = reg_wdata[4];

  assign in_stall_endpoint_5_wd = reg_wdata[5];

  assign in_stall_endpoint_6_wd = reg_wdata[6];

  assign in_stall_endpoint_7_wd = reg_wdata[7];

  assign in_stall_endpoint_8_wd = reg_wdata[8];

  assign in_stall_endpoint_9_wd = reg_wdata[9];

  assign in_stall_endpoint_10_wd = reg_wdata[10];

  assign in_stall_endpoint_11_wd = reg_wdata[11];
  assign configin_0_we = addr_hit[16] & reg_we & !reg_error;

  assign configin_0_buffer_0_wd = reg_wdata[4:0];

  assign configin_0_size_0_wd = reg_wdata[14:8];

  assign configin_0_pend_0_wd = reg_wdata[30];

  assign configin_0_rdy_0_wd = reg_wdata[31];
  assign configin_1_we = addr_hit[17] & reg_we & !reg_error;

  assign configin_1_buffer_1_wd = reg_wdata[4:0];

  assign configin_1_size_1_wd = reg_wdata[14:8];

  assign configin_1_pend_1_wd = reg_wdata[30];

  assign configin_1_rdy_1_wd = reg_wdata[31];
  assign configin_2_we = addr_hit[18] & reg_we & !reg_error;

  assign configin_2_buffer_2_wd = reg_wdata[4:0];

  assign configin_2_size_2_wd = reg_wdata[14:8];

  assign configin_2_pend_2_wd = reg_wdata[30];

  assign configin_2_rdy_2_wd = reg_wdata[31];
  assign configin_3_we = addr_hit[19] & reg_we & !reg_error;

  assign configin_3_buffer_3_wd = reg_wdata[4:0];

  assign configin_3_size_3_wd = reg_wdata[14:8];

  assign configin_3_pend_3_wd = reg_wdata[30];

  assign configin_3_rdy_3_wd = reg_wdata[31];
  assign configin_4_we = addr_hit[20] & reg_we & !reg_error;

  assign configin_4_buffer_4_wd = reg_wdata[4:0];

  assign configin_4_size_4_wd = reg_wdata[14:8];

  assign configin_4_pend_4_wd = reg_wdata[30];

  assign configin_4_rdy_4_wd = reg_wdata[31];
  assign configin_5_we = addr_hit[21] & reg_we & !reg_error;

  assign configin_5_buffer_5_wd = reg_wdata[4:0];

  assign configin_5_size_5_wd = reg_wdata[14:8];

  assign configin_5_pend_5_wd = reg_wdata[30];

  assign configin_5_rdy_5_wd = reg_wdata[31];
  assign configin_6_we = addr_hit[22] & reg_we & !reg_error;

  assign configin_6_buffer_6_wd = reg_wdata[4:0];

  assign configin_6_size_6_wd = reg_wdata[14:8];

  assign configin_6_pend_6_wd = reg_wdata[30];

  assign configin_6_rdy_6_wd = reg_wdata[31];
  assign configin_7_we = addr_hit[23] & reg_we & !reg_error;

  assign configin_7_buffer_7_wd = reg_wdata[4:0];

  assign configin_7_size_7_wd = reg_wdata[14:8];

  assign configin_7_pend_7_wd = reg_wdata[30];

  assign configin_7_rdy_7_wd = reg_wdata[31];
  assign configin_8_we = addr_hit[24] & reg_we & !reg_error;

  assign configin_8_buffer_8_wd = reg_wdata[4:0];

  assign configin_8_size_8_wd = reg_wdata[14:8];

  assign configin_8_pend_8_wd = reg_wdata[30];

  assign configin_8_rdy_8_wd = reg_wdata[31];
  assign configin_9_we = addr_hit[25] & reg_we & !reg_error;

  assign configin_9_buffer_9_wd = reg_wdata[4:0];

  assign configin_9_size_9_wd = reg_wdata[14:8];

  assign configin_9_pend_9_wd = reg_wdata[30];

  assign configin_9_rdy_9_wd = reg_wdata[31];
  assign configin_10_we = addr_hit[26] & reg_we & !reg_error;

  assign configin_10_buffer_10_wd = reg_wdata[4:0];

  assign configin_10_size_10_wd = reg_wdata[14:8];

  assign configin_10_pend_10_wd = reg_wdata[30];

  assign configin_10_rdy_10_wd = reg_wdata[31];
  assign configin_11_we = addr_hit[27] & reg_we & !reg_error;

  assign configin_11_buffer_11_wd = reg_wdata[4:0];

  assign configin_11_size_11_wd = reg_wdata[14:8];

  assign configin_11_pend_11_wd = reg_wdata[30];

  assign configin_11_rdy_11_wd = reg_wdata[31];
  assign out_iso_we = addr_hit[28] & reg_we & !reg_error;

  assign out_iso_iso_0_wd = reg_wdata[0];

  assign out_iso_iso_1_wd = reg_wdata[1];

  assign out_iso_iso_2_wd = reg_wdata[2];

  assign out_iso_iso_3_wd = reg_wdata[3];

  assign out_iso_iso_4_wd = reg_wdata[4];

  assign out_iso_iso_5_wd = reg_wdata[5];

  assign out_iso_iso_6_wd = reg_wdata[6];

  assign out_iso_iso_7_wd = reg_wdata[7];

  assign out_iso_iso_8_wd = reg_wdata[8];

  assign out_iso_iso_9_wd = reg_wdata[9];

  assign out_iso_iso_10_wd = reg_wdata[10];

  assign out_iso_iso_11_wd = reg_wdata[11];
  assign in_iso_we = addr_hit[29] & reg_we & !reg_error;

  assign in_iso_iso_0_wd = reg_wdata[0];

  assign in_iso_iso_1_wd = reg_wdata[1];

  assign in_iso_iso_2_wd = reg_wdata[2];

  assign in_iso_iso_3_wd = reg_wdata[3];

  assign in_iso_iso_4_wd = reg_wdata[4];

  assign in_iso_iso_5_wd = reg_wdata[5];

  assign in_iso_iso_6_wd = reg_wdata[6];

  assign in_iso_iso_7_wd = reg_wdata[7];

  assign in_iso_iso_8_wd = reg_wdata[8];

  assign in_iso_iso_9_wd = reg_wdata[9];

  assign in_iso_iso_10_wd = reg_wdata[10];

  assign in_iso_iso_11_wd = reg_wdata[11];
  assign data_toggle_clear_we = addr_hit[30] & reg_we & !reg_error;

  assign data_toggle_clear_clear_0_wd = reg_wdata[0];

  assign data_toggle_clear_clear_1_wd = reg_wdata[1];

  assign data_toggle_clear_clear_2_wd = reg_wdata[2];

  assign data_toggle_clear_clear_3_wd = reg_wdata[3];

  assign data_toggle_clear_clear_4_wd = reg_wdata[4];

  assign data_toggle_clear_clear_5_wd = reg_wdata[5];

  assign data_toggle_clear_clear_6_wd = reg_wdata[6];

  assign data_toggle_clear_clear_7_wd = reg_wdata[7];

  assign data_toggle_clear_clear_8_wd = reg_wdata[8];

  assign data_toggle_clear_clear_9_wd = reg_wdata[9];

  assign data_toggle_clear_clear_10_wd = reg_wdata[10];

  assign data_toggle_clear_clear_11_wd = reg_wdata[11];
  assign phy_pins_sense_re = addr_hit[31] & reg_re & !reg_error;
  assign phy_pins_drive_we = addr_hit[32] & reg_we & !reg_error;

  assign phy_pins_drive_dp_o_wd = reg_wdata[0];

  assign phy_pins_drive_dn_o_wd = reg_wdata[1];

  assign phy_pins_drive_d_o_wd = reg_wdata[2];

  assign phy_pins_drive_se0_o_wd = reg_wdata[3];

  assign phy_pins_drive_oe_o_wd = reg_wdata[4];

  assign phy_pins_drive_rx_enable_o_wd = reg_wdata[5];

  assign phy_pins_drive_dp_pullup_en_o_wd = reg_wdata[6];

  assign phy_pins_drive_dn_pullup_en_o_wd = reg_wdata[7];

  assign phy_pins_drive_en_wd = reg_wdata[16];
  assign phy_config_we = addr_hit[33] & reg_we & !reg_error;

  assign phy_config_use_diff_rcvr_wd = reg_wdata[0];

  assign phy_config_tx_use_d_se0_wd = reg_wdata[1];

  assign phy_config_eop_single_bit_wd = reg_wdata[2];

  assign phy_config_pinflip_wd = reg_wdata[5];

  assign phy_config_usb_ref_disable_wd = reg_wdata[6];

  assign phy_config_tx_osc_test_mode_wd = reg_wdata[7];
  assign wake_control_we = addr_hit[34] & reg_we & !reg_error;



  // Assign write-enables to checker logic vector.
  always_comb begin
    reg_we_check = '0;
    reg_we_check[0] = intr_state_we;
    reg_we_check[1] = intr_enable_we;
    reg_we_check[2] = intr_test_we;
    reg_we_check[3] = alert_test_we;
    reg_we_check[4] = usbctrl_we;
    reg_we_check[5] = ep_out_enable_we;
    reg_we_check[6] = ep_in_enable_we;
    reg_we_check[7] = 1'b0;
    reg_we_check[8] = avbuffer_we;
    reg_we_check[9] = 1'b0;
    reg_we_check[10] = rxenable_setup_we;
    reg_we_check[11] = rxenable_out_we;
    reg_we_check[12] = set_nak_out_we;
    reg_we_check[13] = in_sent_we;
    reg_we_check[14] = out_stall_we;
    reg_we_check[15] = in_stall_we;
    reg_we_check[16] = configin_0_we;
    reg_we_check[17] = configin_1_we;
    reg_we_check[18] = configin_2_we;
    reg_we_check[19] = configin_3_we;
    reg_we_check[20] = configin_4_we;
    reg_we_check[21] = configin_5_we;
    reg_we_check[22] = configin_6_we;
    reg_we_check[23] = configin_7_we;
    reg_we_check[24] = configin_8_we;
    reg_we_check[25] = configin_9_we;
    reg_we_check[26] = configin_10_we;
    reg_we_check[27] = configin_11_we;
    reg_we_check[28] = out_iso_we;
    reg_we_check[29] = in_iso_we;
    reg_we_check[30] = data_toggle_clear_we;
    reg_we_check[31] = 1'b0;
    reg_we_check[32] = phy_pins_drive_we;
    reg_we_check[33] = phy_config_we;
    reg_we_check[34] = wake_control_we;
    reg_we_check[35] = 1'b0;
  end

  // Read data return
  always_comb begin
    reg_rdata_next = '0;
    unique case (1'b1)
      addr_hit[0]: begin
        reg_rdata_next[0] = intr_state_pkt_received_qs;
        reg_rdata_next[1] = intr_state_pkt_sent_qs;
        reg_rdata_next[2] = intr_state_disconnected_qs;
        reg_rdata_next[3] = intr_state_host_lost_qs;
        reg_rdata_next[4] = intr_state_link_reset_qs;
        reg_rdata_next[5] = intr_state_link_suspend_qs;
        reg_rdata_next[6] = intr_state_link_resume_qs;
        reg_rdata_next[7] = intr_state_av_empty_qs;
        reg_rdata_next[8] = intr_state_rx_full_qs;
        reg_rdata_next[9] = intr_state_av_overflow_qs;
        reg_rdata_next[10] = intr_state_link_in_err_qs;
        reg_rdata_next[11] = intr_state_rx_crc_err_qs;
        reg_rdata_next[12] = intr_state_rx_pid_err_qs;
        reg_rdata_next[13] = intr_state_rx_bitstuff_err_qs;
        reg_rdata_next[14] = intr_state_frame_qs;
        reg_rdata_next[15] = intr_state_powered_qs;
        reg_rdata_next[16] = intr_state_link_out_err_qs;
      end

      addr_hit[1]: begin
        reg_rdata_next[0] = intr_enable_pkt_received_qs;
        reg_rdata_next[1] = intr_enable_pkt_sent_qs;
        reg_rdata_next[2] = intr_enable_disconnected_qs;
        reg_rdata_next[3] = intr_enable_host_lost_qs;
        reg_rdata_next[4] = intr_enable_link_reset_qs;
        reg_rdata_next[5] = intr_enable_link_suspend_qs;
        reg_rdata_next[6] = intr_enable_link_resume_qs;
        reg_rdata_next[7] = intr_enable_av_empty_qs;
        reg_rdata_next[8] = intr_enable_rx_full_qs;
        reg_rdata_next[9] = intr_enable_av_overflow_qs;
        reg_rdata_next[10] = intr_enable_link_in_err_qs;
        reg_rdata_next[11] = intr_enable_rx_crc_err_qs;
        reg_rdata_next[12] = intr_enable_rx_pid_err_qs;
        reg_rdata_next[13] = intr_enable_rx_bitstuff_err_qs;
        reg_rdata_next[14] = intr_enable_frame_qs;
        reg_rdata_next[15] = intr_enable_powered_qs;
        reg_rdata_next[16] = intr_enable_link_out_err_qs;
      end

      addr_hit[2]: begin
        reg_rdata_next[0] = '0;
        reg_rdata_next[1] = '0;
        reg_rdata_next[2] = '0;
        reg_rdata_next[3] = '0;
        reg_rdata_next[4] = '0;
        reg_rdata_next[5] = '0;
        reg_rdata_next[6] = '0;
        reg_rdata_next[7] = '0;
        reg_rdata_next[8] = '0;
        reg_rdata_next[9] = '0;
        reg_rdata_next[10] = '0;
        reg_rdata_next[11] = '0;
        reg_rdata_next[12] = '0;
        reg_rdata_next[13] = '0;
        reg_rdata_next[14] = '0;
        reg_rdata_next[15] = '0;
        reg_rdata_next[16] = '0;
      end

      addr_hit[3]: begin
        reg_rdata_next[0] = '0;
      end

      addr_hit[4]: begin
        reg_rdata_next[0] = usbctrl_enable_qs;
        reg_rdata_next[1] = '0;
        reg_rdata_next[22:16] = usbctrl_device_address_qs;
      end

      addr_hit[5]: begin
        reg_rdata_next[0] = ep_out_enable_enable_0_qs;
        reg_rdata_next[1] = ep_out_enable_enable_1_qs;
        reg_rdata_next[2] = ep_out_enable_enable_2_qs;
        reg_rdata_next[3] = ep_out_enable_enable_3_qs;
        reg_rdata_next[4] = ep_out_enable_enable_4_qs;
        reg_rdata_next[5] = ep_out_enable_enable_5_qs;
        reg_rdata_next[6] = ep_out_enable_enable_6_qs;
        reg_rdata_next[7] = ep_out_enable_enable_7_qs;
        reg_rdata_next[8] = ep_out_enable_enable_8_qs;
        reg_rdata_next[9] = ep_out_enable_enable_9_qs;
        reg_rdata_next[10] = ep_out_enable_enable_10_qs;
        reg_rdata_next[11] = ep_out_enable_enable_11_qs;
      end

      addr_hit[6]: begin
        reg_rdata_next[0] = ep_in_enable_enable_0_qs;
        reg_rdata_next[1] = ep_in_enable_enable_1_qs;
        reg_rdata_next[2] = ep_in_enable_enable_2_qs;
        reg_rdata_next[3] = ep_in_enable_enable_3_qs;
        reg_rdata_next[4] = ep_in_enable_enable_4_qs;
        reg_rdata_next[5] = ep_in_enable_enable_5_qs;
        reg_rdata_next[6] = ep_in_enable_enable_6_qs;
        reg_rdata_next[7] = ep_in_enable_enable_7_qs;
        reg_rdata_next[8] = ep_in_enable_enable_8_qs;
        reg_rdata_next[9] = ep_in_enable_enable_9_qs;
        reg_rdata_next[10] = ep_in_enable_enable_10_qs;
        reg_rdata_next[11] = ep_in_enable_enable_11_qs;
      end

      addr_hit[7]: begin
        reg_rdata_next[10:0] = usbstat_frame_qs;
        reg_rdata_next[11] = usbstat_host_lost_qs;
        reg_rdata_next[14:12] = usbstat_link_state_qs;
        reg_rdata_next[15] = usbstat_sense_qs;
        reg_rdata_next[18:16] = usbstat_av_depth_qs;
        reg_rdata_next[23] = usbstat_av_full_qs;
        reg_rdata_next[26:24] = usbstat_rx_depth_qs;
        reg_rdata_next[31] = usbstat_rx_empty_qs;
      end

      addr_hit[8]: begin
        reg_rdata_next[4:0] = '0;
      end

      addr_hit[9]: begin
        reg_rdata_next[4:0] = rxfifo_buffer_qs;
        reg_rdata_next[14:8] = rxfifo_size_qs;
        reg_rdata_next[19] = rxfifo_setup_qs;
        reg_rdata_next[23:20] = rxfifo_ep_qs;
      end

      addr_hit[10]: begin
        reg_rdata_next[0] = rxenable_setup_setup_0_qs;
        reg_rdata_next[1] = rxenable_setup_setup_1_qs;
        reg_rdata_next[2] = rxenable_setup_setup_2_qs;
        reg_rdata_next[3] = rxenable_setup_setup_3_qs;
        reg_rdata_next[4] = rxenable_setup_setup_4_qs;
        reg_rdata_next[5] = rxenable_setup_setup_5_qs;
        reg_rdata_next[6] = rxenable_setup_setup_6_qs;
        reg_rdata_next[7] = rxenable_setup_setup_7_qs;
        reg_rdata_next[8] = rxenable_setup_setup_8_qs;
        reg_rdata_next[9] = rxenable_setup_setup_9_qs;
        reg_rdata_next[10] = rxenable_setup_setup_10_qs;
        reg_rdata_next[11] = rxenable_setup_setup_11_qs;
      end

      addr_hit[11]: begin
        reg_rdata_next[0] = rxenable_out_out_0_qs;
        reg_rdata_next[1] = rxenable_out_out_1_qs;
        reg_rdata_next[2] = rxenable_out_out_2_qs;
        reg_rdata_next[3] = rxenable_out_out_3_qs;
        reg_rdata_next[4] = rxenable_out_out_4_qs;
        reg_rdata_next[5] = rxenable_out_out_5_qs;
        reg_rdata_next[6] = rxenable_out_out_6_qs;
        reg_rdata_next[7] = rxenable_out_out_7_qs;
        reg_rdata_next[8] = rxenable_out_out_8_qs;
        reg_rdata_next[9] = rxenable_out_out_9_qs;
        reg_rdata_next[10] = rxenable_out_out_10_qs;
        reg_rdata_next[11] = rxenable_out_out_11_qs;
      end

      addr_hit[12]: begin
        reg_rdata_next[0] = set_nak_out_enable_0_qs;
        reg_rdata_next[1] = set_nak_out_enable_1_qs;
        reg_rdata_next[2] = set_nak_out_enable_2_qs;
        reg_rdata_next[3] = set_nak_out_enable_3_qs;
        reg_rdata_next[4] = set_nak_out_enable_4_qs;
        reg_rdata_next[5] = set_nak_out_enable_5_qs;
        reg_rdata_next[6] = set_nak_out_enable_6_qs;
        reg_rdata_next[7] = set_nak_out_enable_7_qs;
        reg_rdata_next[8] = set_nak_out_enable_8_qs;
        reg_rdata_next[9] = set_nak_out_enable_9_qs;
        reg_rdata_next[10] = set_nak_out_enable_10_qs;
        reg_rdata_next[11] = set_nak_out_enable_11_qs;
      end

      addr_hit[13]: begin
        reg_rdata_next[0] = in_sent_sent_0_qs;
        reg_rdata_next[1] = in_sent_sent_1_qs;
        reg_rdata_next[2] = in_sent_sent_2_qs;
        reg_rdata_next[3] = in_sent_sent_3_qs;
        reg_rdata_next[4] = in_sent_sent_4_qs;
        reg_rdata_next[5] = in_sent_sent_5_qs;
        reg_rdata_next[6] = in_sent_sent_6_qs;
        reg_rdata_next[7] = in_sent_sent_7_qs;
        reg_rdata_next[8] = in_sent_sent_8_qs;
        reg_rdata_next[9] = in_sent_sent_9_qs;
        reg_rdata_next[10] = in_sent_sent_10_qs;
        reg_rdata_next[11] = in_sent_sent_11_qs;
      end

      addr_hit[14]: begin
        reg_rdata_next[0] = out_stall_endpoint_0_qs;
        reg_rdata_next[1] = out_stall_endpoint_1_qs;
        reg_rdata_next[2] = out_stall_endpoint_2_qs;
        reg_rdata_next[3] = out_stall_endpoint_3_qs;
        reg_rdata_next[4] = out_stall_endpoint_4_qs;
        reg_rdata_next[5] = out_stall_endpoint_5_qs;
        reg_rdata_next[6] = out_stall_endpoint_6_qs;
        reg_rdata_next[7] = out_stall_endpoint_7_qs;
        reg_rdata_next[8] = out_stall_endpoint_8_qs;
        reg_rdata_next[9] = out_stall_endpoint_9_qs;
        reg_rdata_next[10] = out_stall_endpoint_10_qs;
        reg_rdata_next[11] = out_stall_endpoint_11_qs;
      end

      addr_hit[15]: begin
        reg_rdata_next[0] = in_stall_endpoint_0_qs;
        reg_rdata_next[1] = in_stall_endpoint_1_qs;
        reg_rdata_next[2] = in_stall_endpoint_2_qs;
        reg_rdata_next[3] = in_stall_endpoint_3_qs;
        reg_rdata_next[4] = in_stall_endpoint_4_qs;
        reg_rdata_next[5] = in_stall_endpoint_5_qs;
        reg_rdata_next[6] = in_stall_endpoint_6_qs;
        reg_rdata_next[7] = in_stall_endpoint_7_qs;
        reg_rdata_next[8] = in_stall_endpoint_8_qs;
        reg_rdata_next[9] = in_stall_endpoint_9_qs;
        reg_rdata_next[10] = in_stall_endpoint_10_qs;
        reg_rdata_next[11] = in_stall_endpoint_11_qs;
      end

      addr_hit[16]: begin
        reg_rdata_next[4:0] = configin_0_buffer_0_qs;
        reg_rdata_next[14:8] = configin_0_size_0_qs;
        reg_rdata_next[30] = configin_0_pend_0_qs;
        reg_rdata_next[31] = configin_0_rdy_0_qs;
      end

      addr_hit[17]: begin
        reg_rdata_next[4:0] = configin_1_buffer_1_qs;
        reg_rdata_next[14:8] = configin_1_size_1_qs;
        reg_rdata_next[30] = configin_1_pend_1_qs;
        reg_rdata_next[31] = configin_1_rdy_1_qs;
      end

      addr_hit[18]: begin
        reg_rdata_next[4:0] = configin_2_buffer_2_qs;
        reg_rdata_next[14:8] = configin_2_size_2_qs;
        reg_rdata_next[30] = configin_2_pend_2_qs;
        reg_rdata_next[31] = configin_2_rdy_2_qs;
      end

      addr_hit[19]: begin
        reg_rdata_next[4:0] = configin_3_buffer_3_qs;
        reg_rdata_next[14:8] = configin_3_size_3_qs;
        reg_rdata_next[30] = configin_3_pend_3_qs;
        reg_rdata_next[31] = configin_3_rdy_3_qs;
      end

      addr_hit[20]: begin
        reg_rdata_next[4:0] = configin_4_buffer_4_qs;
        reg_rdata_next[14:8] = configin_4_size_4_qs;
        reg_rdata_next[30] = configin_4_pend_4_qs;
        reg_rdata_next[31] = configin_4_rdy_4_qs;
      end

      addr_hit[21]: begin
        reg_rdata_next[4:0] = configin_5_buffer_5_qs;
        reg_rdata_next[14:8] = configin_5_size_5_qs;
        reg_rdata_next[30] = configin_5_pend_5_qs;
        reg_rdata_next[31] = configin_5_rdy_5_qs;
      end

      addr_hit[22]: begin
        reg_rdata_next[4:0] = configin_6_buffer_6_qs;
        reg_rdata_next[14:8] = configin_6_size_6_qs;
        reg_rdata_next[30] = configin_6_pend_6_qs;
        reg_rdata_next[31] = configin_6_rdy_6_qs;
      end

      addr_hit[23]: begin
        reg_rdata_next[4:0] = configin_7_buffer_7_qs;
        reg_rdata_next[14:8] = configin_7_size_7_qs;
        reg_rdata_next[30] = configin_7_pend_7_qs;
        reg_rdata_next[31] = configin_7_rdy_7_qs;
      end

      addr_hit[24]: begin
        reg_rdata_next[4:0] = configin_8_buffer_8_qs;
        reg_rdata_next[14:8] = configin_8_size_8_qs;
        reg_rdata_next[30] = configin_8_pend_8_qs;
        reg_rdata_next[31] = configin_8_rdy_8_qs;
      end

      addr_hit[25]: begin
        reg_rdata_next[4:0] = configin_9_buffer_9_qs;
        reg_rdata_next[14:8] = configin_9_size_9_qs;
        reg_rdata_next[30] = configin_9_pend_9_qs;
        reg_rdata_next[31] = configin_9_rdy_9_qs;
      end

      addr_hit[26]: begin
        reg_rdata_next[4:0] = configin_10_buffer_10_qs;
        reg_rdata_next[14:8] = configin_10_size_10_qs;
        reg_rdata_next[30] = configin_10_pend_10_qs;
        reg_rdata_next[31] = configin_10_rdy_10_qs;
      end

      addr_hit[27]: begin
        reg_rdata_next[4:0] = configin_11_buffer_11_qs;
        reg_rdata_next[14:8] = configin_11_size_11_qs;
        reg_rdata_next[30] = configin_11_pend_11_qs;
        reg_rdata_next[31] = configin_11_rdy_11_qs;
      end

      addr_hit[28]: begin
        reg_rdata_next[0] = out_iso_iso_0_qs;
        reg_rdata_next[1] = out_iso_iso_1_qs;
        reg_rdata_next[2] = out_iso_iso_2_qs;
        reg_rdata_next[3] = out_iso_iso_3_qs;
        reg_rdata_next[4] = out_iso_iso_4_qs;
        reg_rdata_next[5] = out_iso_iso_5_qs;
        reg_rdata_next[6] = out_iso_iso_6_qs;
        reg_rdata_next[7] = out_iso_iso_7_qs;
        reg_rdata_next[8] = out_iso_iso_8_qs;
        reg_rdata_next[9] = out_iso_iso_9_qs;
        reg_rdata_next[10] = out_iso_iso_10_qs;
        reg_rdata_next[11] = out_iso_iso_11_qs;
      end

      addr_hit[29]: begin
        reg_rdata_next[0] = in_iso_iso_0_qs;
        reg_rdata_next[1] = in_iso_iso_1_qs;
        reg_rdata_next[2] = in_iso_iso_2_qs;
        reg_rdata_next[3] = in_iso_iso_3_qs;
        reg_rdata_next[4] = in_iso_iso_4_qs;
        reg_rdata_next[5] = in_iso_iso_5_qs;
        reg_rdata_next[6] = in_iso_iso_6_qs;
        reg_rdata_next[7] = in_iso_iso_7_qs;
        reg_rdata_next[8] = in_iso_iso_8_qs;
        reg_rdata_next[9] = in_iso_iso_9_qs;
        reg_rdata_next[10] = in_iso_iso_10_qs;
        reg_rdata_next[11] = in_iso_iso_11_qs;
      end

      addr_hit[30]: begin
        reg_rdata_next[0] = '0;
        reg_rdata_next[1] = '0;
        reg_rdata_next[2] = '0;
        reg_rdata_next[3] = '0;
        reg_rdata_next[4] = '0;
        reg_rdata_next[5] = '0;
        reg_rdata_next[6] = '0;
        reg_rdata_next[7] = '0;
        reg_rdata_next[8] = '0;
        reg_rdata_next[9] = '0;
        reg_rdata_next[10] = '0;
        reg_rdata_next[11] = '0;
      end

      addr_hit[31]: begin
        reg_rdata_next[0] = phy_pins_sense_rx_dp_i_qs;
        reg_rdata_next[1] = phy_pins_sense_rx_dn_i_qs;
        reg_rdata_next[2] = phy_pins_sense_rx_d_i_qs;
        reg_rdata_next[8] = phy_pins_sense_tx_dp_o_qs;
        reg_rdata_next[9] = phy_pins_sense_tx_dn_o_qs;
        reg_rdata_next[10] = phy_pins_sense_tx_d_o_qs;
        reg_rdata_next[11] = phy_pins_sense_tx_se0_o_qs;
        reg_rdata_next[12] = phy_pins_sense_tx_oe_o_qs;
        reg_rdata_next[16] = phy_pins_sense_pwr_sense_qs;
      end

      addr_hit[32]: begin
        reg_rdata_next[0] = phy_pins_drive_dp_o_qs;
        reg_rdata_next[1] = phy_pins_drive_dn_o_qs;
        reg_rdata_next[2] = phy_pins_drive_d_o_qs;
        reg_rdata_next[3] = phy_pins_drive_se0_o_qs;
        reg_rdata_next[4] = phy_pins_drive_oe_o_qs;
        reg_rdata_next[5] = phy_pins_drive_rx_enable_o_qs;
        reg_rdata_next[6] = phy_pins_drive_dp_pullup_en_o_qs;
        reg_rdata_next[7] = phy_pins_drive_dn_pullup_en_o_qs;
        reg_rdata_next[16] = phy_pins_drive_en_qs;
      end

      addr_hit[33]: begin
        reg_rdata_next[0] = phy_config_use_diff_rcvr_qs;
        reg_rdata_next[1] = phy_config_tx_use_d_se0_qs;
        reg_rdata_next[2] = phy_config_eop_single_bit_qs;
        reg_rdata_next[5] = phy_config_pinflip_qs;
        reg_rdata_next[6] = phy_config_usb_ref_disable_qs;
        reg_rdata_next[7] = phy_config_tx_osc_test_mode_qs;
      end

      addr_hit[34]: begin
        reg_rdata_next = DW'(wake_control_qs);
      end
      addr_hit[35]: begin
        reg_rdata_next = DW'(wake_events_qs);
      end
      default: begin
        reg_rdata_next = '1;
      end
    endcase
  end

  // shadow busy
  logic shadow_busy;
  assign shadow_busy = 1'b0;

  // register busy
  logic reg_busy_sel;
  assign reg_busy = reg_busy_sel | shadow_busy;
  always_comb begin
    reg_busy_sel = '0;
    unique case (1'b1)
      addr_hit[34]: begin
        reg_busy_sel = wake_control_busy;
      end
      addr_hit[35]: begin
        reg_busy_sel = wake_events_busy;
      end
      default: begin
        reg_busy_sel  = '0;
      end
    endcase
  end


  // Unused signal tieoff

  // wdata / byte enable are not always fully used
  // add a blanket unused statement to handle lint waivers
  logic unused_wdata;
  logic unused_be;
  assign unused_wdata = ^reg_wdata;
  assign unused_be = ^reg_be;

  // Assertions for Register Interface
  `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
  `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)

  `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)

  `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)

  // this is formulated as an assumption such that the FPV testbenches do disprove this
  // property by mistake
  //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)

endmodule