[csrng/rtl] added fatal alert Also changed all sync fifos to use the full_o. Force fatal error register added. Re-ran the top level interconnection script. Connect new alert to alert handler at the top level. Fixed some of the error reporting logic. Updated the fifo intr to be a fatal interrupt. Updated the csrng tb to stub intial io values. Changed the fatal interrupt name to be more consistant with others. Changed register name to err_code_test, and read-only. Re-ran top level make. Signed-off-by: Mark Branstad <mark.branstad@wdc.com>
diff --git a/hw/ip/csrng/data/csrng.hjson b/hw/ip/csrng/data/csrng.hjson index 10d540d..ff9abb7 100644 --- a/hw/ip/csrng/data/csrng.hjson +++ b/hw/ip/csrng/data/csrng.hjson
@@ -8,7 +8,7 @@ param_list: [ { name: "SBoxImpl", type: "aes_pkg::sbox_impl_e", - default: "aes_pkg::SBoxImplCanright", + default: "aes_pkg::SBoxImplLut", desc: "Selection of the S-Box implementation. See aes_pkg.sv.", local: "false", expose: "true" @@ -27,8 +27,13 @@ desc: "Asserted when a request for entropy has been made."} { name: "cs_hw_inst_exc" desc: "Asserted when a hardware-attached CSRNG instance encounters a command exception"} - { name: "cs_fifo_err" - desc: "Asserted when a FIFO error occurs."} + { name: "cs_fatal_err" + desc: "Asserted when a FIFO error or a fatal alert occurs. Check the !!ERR_CODE register to get more information."} + ], + alert_list: [ + { name: "fatal_alert", + desc: "This alert triggers if an illegal state machine state is reached, or if an AES fatal alert condition occurs.", + } ], inter_signal_list: [ { struct: "csrng" @@ -274,7 +279,7 @@ { name: "ERR_CODE", desc: "Hardware detection of error conditions status register", - swaccess: "rw", + swaccess: "ro", hwaccess: "hwo", fields: [ { bits: "0", @@ -421,6 +426,60 @@ This bit will stay set until firmware clears it. ''' } + { bits: "20", + name: "CMD_STAGE_SM_ERR", + desc: ''' + This bit will be set to one when an illegal state has been detected for the + command stage state machine. This error will signal a fatal alert, and also + an interrupt if enabled. + This bit will stay set until firmware clears it. + ''' + } + { bits: "21", + name: "MAIN_SM_ERR", + desc: ''' + This bit will be set to one when an illegal state has been detected for the + main state machine. This error will signal a fatal alert, and also + an interrupt if enabled. + This bit will stay set until firmware clears it. + ''' + } + { bits: "22", + name: "DRBG_GEN_SM_ERR", + desc: ''' + This bit will be set to one when an illegal state has been detected for the + ctr_dbrg gen state machine. This error will signal a fatal alert, and also + an interrupt if enabled. + This bit will stay set until firmware clears it. + ''' + } + { bits: "23", + name: "DRBG_UPDBE_SM_ERR", + desc: ''' + This bit will be set to one when an illegal state has been detected for the + ctr_dbrg update block encode state machine. This error will signal a fatal alert, and also + an interrupt if enabled. + This bit will stay set until firmware clears it. + ''' + } + { bits: "24", + name: "DRBG_UPDOB_SM_ERR", + desc: ''' + This bit will be set to one when an illegal state has been detected for the + ctr_dbrg update out block state machine. This error will signal a fatal alert, and also + an interrupt if enabled. + This bit will stay set until firmware clears it. + ''' + } + { bits: "25", + name: "AES_CIPHER_SM_ERR", + desc: ''' + This bit will be set to one when an AES fatal error has been detected. + This error will signal a fatal alert, and also + an interrupt if enabled. + This bit will stay set until firmware clears it. + ''' + } { bits: "28", name: "FIFO_WRITE_ERR", desc: ''' @@ -450,5 +509,26 @@ } ] }, + { name: "ERR_CODE_TEST", + desc: "Test error conditions register", + swaccess: "rw", + hwaccess: "hro", + hwqe: "true", + regwen: "REGWEN", + fields: [ + { + bits: "4:0", + name: "ERR_CODE_TEST", + desc: ''' + Setting this field will set the bit number for which an error + will be forced in the hardware. This bit number is that same one + found in the !!ERR_CODE register. The action of writing this + register will force an error pulse. The sole purpose of this + register is to test that any error properly propagates to either + an interrupt or an alert. + ''' + }, + ] + }, ] }
diff --git a/hw/ip/csrng/dv/tb.sv b/hw/ip/csrng/dv/tb.sv old mode 100644 new mode 100755 index a34024a..f2ebc9c --- a/hw/ip/csrng/dv/tb.sv +++ b/hw/ip/csrng/dv/tb.sv
@@ -19,7 +19,7 @@ wire intr_cmd_req_done; wire intr_entropy_req; wire intr_hw_inst_exc; - wire intr_fifo_err; + wire intr_cs_fatal_err; // interfaces clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n)); @@ -51,16 +51,19 @@ .csrng_cmd_i (csrng_if.cmd_req), .csrng_cmd_o (csrng_if.cmd_rsp), + .alert_rx_i ('0), // (alert_rx), // TODO: connect to model + .alert_tx_o (), // (alert_tx), // TODO: connect to model + .intr_cs_cmd_req_done_o (intr_cmd_req_done), .intr_cs_entropy_req_o (intr_entropy_req), .intr_cs_hw_inst_exc_o (intr_hw_inst_exc), - .intr_cs_fifo_err_o (intr_fifo_err) + .intr_cs_fatal_err_o (intr_cs_fatal_err) ); assign interrupts[CmdReqDone] = intr_cmd_req_done; assign interrupts[EntropyReq] = intr_entropy_req; assign interrupts[HwInstExc] = intr_hw_inst_exc; - assign interrupts[FifoErr] = intr_fifo_err; + assign interrupts[FifoErr] = intr_cs_fatal_err; initial begin // drive clk and rst_n from clk_if
diff --git a/hw/ip/csrng/rtl/csrng.sv b/hw/ip/csrng/rtl/csrng.sv index 92498c6..ffee8c6 100644 --- a/hw/ip/csrng/rtl/csrng.sv +++ b/hw/ip/csrng/rtl/csrng.sv
@@ -6,8 +6,12 @@ `include "prim_assert.sv" -module csrng import csrng_pkg::*; #( +module csrng + import csrng_pkg::*; + import csrng_reg_pkg::*; +#( parameter aes_pkg::sbox_impl_e SBoxImpl = aes_pkg::SBoxImplLut, + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, parameter int NHwApps = 2 ) ( input logic clk_i, @@ -31,11 +35,15 @@ input csrng_req_t [NHwApps-1:0] csrng_cmd_i, output csrng_rsp_t [NHwApps-1:0] csrng_cmd_o, + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + // Interrupts output logic intr_cs_cmd_req_done_o, output logic intr_cs_entropy_req_o, output logic intr_cs_hw_inst_exc_o, - output logic intr_cs_fifo_err_o + output logic intr_cs_fatal_err_o ); @@ -44,6 +52,9 @@ csrng_reg2hw_t reg2hw; csrng_hw2reg_t hw2reg; + logic alert; + logic alert_test; + csrng_reg_top u_reg ( .clk_i, .rst_ni, @@ -51,7 +62,6 @@ .tl_o, .reg2hw, .hw2reg, - .devmode_i(1'b1) ); @@ -76,12 +86,32 @@ .csrng_cmd_i, .csrng_cmd_o, + // Alerts + .alert_test_o(alert_test), + .fatal_alert_o(alert), + .intr_cs_cmd_req_done_o, .intr_cs_entropy_req_o, .intr_cs_hw_inst_exc_o, - .intr_cs_fifo_err_o + .intr_cs_fatal_err_o ); + + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[0]), + .IsFatal(1) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test ), + .alert_req_i ( alert ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[0] ), + .alert_tx_o ( alert_tx_o[0] ) + ); + + // Assertions `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid) @@ -98,10 +128,13 @@ `ASSERT_KNOWN(CsrngGenbitsBusKnownO_A, csrng_cmd_o[i].genbits_bus) end : gen_app_if_asserts + // Alerts + `ASSERT_KNOWN(AlertTxKnownO_A, alert_tx_o) + `ASSERT_KNOWN(IntrCsCmdReqDoneKnownO_A, intr_cs_cmd_req_done_o) `ASSERT_KNOWN(IntrCsEntropyReqKnownO_A, intr_cs_entropy_req_o) `ASSERT_KNOWN(IntrCsHwInstExcKnownO_A, intr_cs_hw_inst_exc_o) - `ASSERT_KNOWN(IntrCsFifoErrKnownO_A, intr_cs_fifo_err_o) + `ASSERT_KNOWN(IntrCsFatalErrKnownO_A, intr_cs_fatal_err_o)
diff --git a/hw/ip/csrng/rtl/csrng_block_encrypt.sv b/hw/ip/csrng/rtl/csrng_block_encrypt.sv index d07cd17..4be9ad2 100644 --- a/hw/ip/csrng/rtl/csrng_block_encrypt.sv +++ b/hw/ip/csrng/rtl/csrng_block_encrypt.sv
@@ -30,6 +30,7 @@ output logic [Cmd-1:0] block_encrypt_cmd_o, output logic [StateId-1:0] block_encrypt_id_o, output logic [BlkLen-1:0] block_encrypt_v_o, + output logic block_encrypt_aes_cipher_sm_err_o, output logic [2:0] block_encrypt_sfifo_blkenc_err_o ); @@ -43,7 +44,7 @@ logic sfifo_blkenc_push; logic [BlkEncFifoWidth-1:0] sfifo_blkenc_wdata; logic sfifo_blkenc_pop; - logic sfifo_blkenc_not_full; + logic sfifo_blkenc_full; logic sfifo_blkenc_not_empty; // breakout logic [Cmd-1:0] sfifo_blkenc_cmd; @@ -99,7 +100,7 @@ .key_len_i ( aes_pkg::AES_256 ), .crypt_i ( aes_cipher_core_enable ), .crypt_o ( ), - .alert_o ( ), // TODO: Prop to top + .alert_o ( block_encrypt_aes_cipher_sm_err_o), .dec_key_gen_i ( 1'b0 ), // Disable .dec_key_gen_o ( ), .key_clear_i ( 1'b0 ), // Disable @@ -132,19 +133,19 @@ .rst_ni (rst_ni), .clr_i (!block_encrypt_enable_i), .wvalid_i (sfifo_blkenc_push), - .wready_o (sfifo_blkenc_not_full), + .wready_o (), .wdata_i (sfifo_blkenc_wdata), .rvalid_o (sfifo_blkenc_not_empty), .rready_i (sfifo_blkenc_pop), .rdata_o (sfifo_blkenc_rdata), - .full_o (), + .full_o (sfifo_blkenc_full), .depth_o () ); - assign sfifo_blkenc_push = block_encrypt_req_i && sfifo_blkenc_not_full; + assign sfifo_blkenc_push = block_encrypt_req_i && !sfifo_blkenc_full; assign sfifo_blkenc_wdata = {block_encrypt_v_i,block_encrypt_id_i,block_encrypt_cmd_i}; - assign block_encrypt_rdy_o = !aes_cipher_core_enable ? sfifo_blkenc_not_full : cipher_in_ready; + assign block_encrypt_rdy_o = !aes_cipher_core_enable ? !sfifo_blkenc_full : cipher_in_ready; assign sfifo_blkenc_pop = block_encrypt_ack_o; assign {sfifo_blkenc_v,sfifo_blkenc_id,sfifo_blkenc_cmd} = sfifo_blkenc_rdata; @@ -158,8 +159,8 @@ assign cipher_out_ready = block_encrypt_rdy_i; assign block_encrypt_sfifo_blkenc_err_o = - {(sfifo_blkenc_push && !sfifo_blkenc_not_full), + {(sfifo_blkenc_push && sfifo_blkenc_full), (sfifo_blkenc_pop && !sfifo_blkenc_not_empty), - (!sfifo_blkenc_not_full && !sfifo_blkenc_not_empty)}; + (sfifo_blkenc_full && !sfifo_blkenc_not_empty)}; endmodule
diff --git a/hw/ip/csrng/rtl/csrng_cmd_stage.sv b/hw/ip/csrng/rtl/csrng_cmd_stage.sv index 2f84d9b..85940da 100644 --- a/hw/ip/csrng/rtl/csrng_cmd_stage.sv +++ b/hw/ip/csrng/rtl/csrng_cmd_stage.sv
@@ -42,7 +42,8 @@ output logic genbits_fips_o, // error indication output logic [2:0] cmd_stage_sfifo_cmd_err_o, - output logic [2:0] cmd_stage_sfifo_genbits_err_o + output logic [2:0] cmd_stage_sfifo_genbits_err_o, + output logic cmd_stage_sm_err_o ); localparam int GenBitsFifoWidth = 1+128; @@ -56,7 +57,7 @@ logic [CmdFifoWidth-1:0] sfifo_cmd_wdata; logic sfifo_cmd_pop; logic [2:0] sfifo_cmd_err; - logic sfifo_cmd_not_full; + logic sfifo_cmd_full; logic sfifo_cmd_not_empty; // genbits fifo @@ -65,7 +66,7 @@ logic [GenBitsFifoWidth-1:0] sfifo_genbits_wdata; logic sfifo_genbits_pop; logic [2:0] sfifo_genbits_err; - logic sfifo_genbits_not_full; + logic sfifo_genbits_full; logic sfifo_genbits_not_empty; logic [3:0] cmd_len; @@ -119,12 +120,12 @@ .rst_ni (rst_ni), .clr_i (!cs_enable_i), .wvalid_i (sfifo_cmd_push), - .wready_o (sfifo_cmd_not_full), + .wready_o (), .wdata_i (sfifo_cmd_wdata), .rvalid_o (sfifo_cmd_not_empty), .rready_i (sfifo_cmd_pop), .rdata_o (sfifo_cmd_rdata), - .full_o (), + .full_o (sfifo_cmd_full), .depth_o (sfifo_cmd_depth) ); @@ -139,12 +140,12 @@ cmd_gen_1st_req ? {16'b0,cmd_stage_shid_i,sfifo_cmd_rdata[11:0]} : // pad,id,f,clen,cmd sfifo_cmd_rdata; - assign cmd_stage_rdy_o = sfifo_cmd_not_full; + assign cmd_stage_rdy_o = !sfifo_cmd_full; assign sfifo_cmd_err = - {(sfifo_cmd_push && !sfifo_cmd_not_full), + {(sfifo_cmd_push && sfifo_cmd_full), (sfifo_cmd_pop && !sfifo_cmd_not_empty), - (!sfifo_cmd_not_full && !sfifo_cmd_not_empty)}; + (sfifo_cmd_full && !sfifo_cmd_not_empty)}; // state machine controls @@ -173,28 +174,35 @@ // state machine to process command //--------------------------------------------------------- - // Encoding generated with ./sparse-fsm-encode.py -d 3 -m 6 -n 6 -s 1112859863 - // Hamming distance histogram: - // - // 0: -- - // 1: -- - // 2: -- - // 3: |||||||||||||||||||| (53.33%) - // 4: ||||||||||||||| (40.00%) - // 5: || (6.67%) - // 6: -- - // - // Minimum Hamming distance: 3 - // Maximum Hamming distance: 5 - // +// Encoding generated with: +// $ ./util/design/sparse-fsm-encode.py -d 3 -m 7 -n 6 \ +// -s 2519129599 --language=sv +// +// Hamming distance histogram: +// +// 0: -- +// 1: -- +// 2: -- +// 3: |||||||||||||||||||| (57.14%) +// 4: ||||||||||||||| (42.86%) +// 5: -- +// 6: -- +// +// Minimum Hamming distance: 3 +// Maximum Hamming distance: 4 +// Minimum Hamming weight: 1 +// Maximum Hamming weight: 5 +// + localparam int StateWidth = 6; typedef enum logic [StateWidth-1:0] { - Idle = 6'b000100, // idle - SendSOP = 6'b110011, // send sop (start of packet) - SendMOP = 6'b011110, // send mop (middle of packet) - GenCmdChk = 6'b001011, // gen cmd check - CmdAck = 6'b101101, // wait for command ack - GenReq = 6'b111000 // process gen requests + Idle = 6'b001010, // idle + SendSOP = 6'b000111, // send sop (start of packet) + SendMOP = 6'b010000, // send mop (middle of packet) + GenCmdChk = 6'b011101, // gen cmd check + CmdAck = 6'b111011, // wait for command ack + GenReq = 6'b110110, // process gen requests + Error = 6'b101100 // illegal state reached and hang } state_e; state_e state_d, state_q; @@ -227,6 +235,7 @@ cmd_arb_sop_o = 1'b0; cmd_arb_mop_o = 1'b0; cmd_arb_eop_o = 1'b0; + cmd_stage_sm_err_o = 1'b0; unique case (state_q) Idle: begin if (!cmd_fifo_zero) begin @@ -276,7 +285,7 @@ // flag set if a gen request if (cmd_gen_flag_q) begin // must stall if genbits fifo is not clear - if (sfifo_genbits_not_full) begin + if (!sfifo_genbits_full) begin if (cmd_gen_cnt_q == '0) begin cmd_final_ack = 1'b1; state_d = Idle; @@ -297,7 +306,10 @@ state_d = Idle; end end - default: state_d = Idle; + Error: begin + cmd_stage_sm_err_o = 1'b1; + end + default: state_d = Error; endcase end @@ -314,12 +326,12 @@ .rst_ni (rst_ni), .clr_i (!cs_enable_i), .wvalid_i (sfifo_genbits_push), - .wready_o (sfifo_genbits_not_full), + .wready_o (), .wdata_i (sfifo_genbits_wdata), .rvalid_o (sfifo_genbits_not_empty), .rready_i (sfifo_genbits_pop), .rdata_o (sfifo_genbits_rdata), - .full_o (), + .full_o (sfifo_genbits_full), .depth_o () // sfifo_genbits_depth) ); @@ -334,9 +346,9 @@ assign sfifo_genbits_err = - {(sfifo_genbits_push && !sfifo_genbits_not_full), + {(sfifo_genbits_push && sfifo_genbits_full), (sfifo_genbits_pop && !sfifo_genbits_not_empty), - (!sfifo_genbits_not_full && !sfifo_genbits_not_empty)}; + (sfifo_genbits_full && !sfifo_genbits_not_empty)}; //--------------------------------------------------------- // ack logic
diff --git a/hw/ip/csrng/rtl/csrng_core.sv b/hw/ip/csrng/rtl/csrng_core.sv index 232b1c7..f70960d 100644 --- a/hw/ip/csrng/rtl/csrng_core.sv +++ b/hw/ip/csrng/rtl/csrng_core.sv
@@ -27,14 +27,17 @@ input entropy_src_pkg::entropy_src_hw_if_rsp_t entropy_src_hw_if_i, // Application Interfaces - // instantiation interface input csrng_req_t [NHwApps-1:0] csrng_cmd_i, output csrng_rsp_t [NHwApps-1:0] csrng_cmd_o, + // Alerts + output logic alert_test_o, + output logic fatal_alert_o, + output logic intr_cs_cmd_req_done_o, output logic intr_cs_entropy_req_o, output logic intr_cs_hw_inst_exc_o, - output logic intr_cs_fifo_err_o + output logic intr_cs_fatal_err_o ); import csrng_reg_pkg::*; @@ -59,7 +62,7 @@ logic event_cs_cmd_req_done; logic event_cs_entropy_req; logic event_cs_hw_inst_exc; - logic event_cs_fifo_err; + logic event_cs_fatal_err; logic cs_enable; logic aes_cipher_enable; logic acmd_avail; @@ -127,20 +130,49 @@ logic ctr_drbg_gen_req; logic ctr_drbg_gen_req_rdy; logic ctr_drbg_cmd_req_rdy; + logic ctr_drbg_cmd_sfifo_cmdreq_err_sum; logic [2:0] ctr_drbg_cmd_sfifo_cmdreq_err; + logic ctr_drbg_cmd_sfifo_rcstage_err_sum; logic [2:0] ctr_drbg_cmd_sfifo_rcstage_err; + logic ctr_drbg_cmd_sfifo_keyvrc_err_sum; logic [2:0] ctr_drbg_cmd_sfifo_keyvrc_err; + logic ctr_drbg_upd_sfifo_updreq_err_sum; logic [2:0] ctr_drbg_upd_sfifo_updreq_err; + logic ctr_drbg_upd_sfifo_bencreq_err_sum; logic [2:0] ctr_drbg_upd_sfifo_bencreq_err; + logic ctr_drbg_upd_sfifo_bencack_err_sum; logic [2:0] ctr_drbg_upd_sfifo_bencack_err; + logic ctr_drbg_upd_sfifo_pdata_err_sum; logic [2:0] ctr_drbg_upd_sfifo_pdata_err; + logic ctr_drbg_upd_sfifo_final_err_sum; logic [2:0] ctr_drbg_upd_sfifo_final_err; + logic ctr_drbg_gen_sfifo_gbencack_err_sum; logic [2:0] ctr_drbg_gen_sfifo_gbencack_err; + logic ctr_drbg_gen_sfifo_grcstage_err_sum; logic [2:0] ctr_drbg_gen_sfifo_grcstage_err; + logic ctr_drbg_gen_sfifo_ggenreq_err_sum; logic [2:0] ctr_drbg_gen_sfifo_ggenreq_err; + logic ctr_drbg_gen_sfifo_gadstage_err_sum; logic [2:0] ctr_drbg_gen_sfifo_gadstage_err; + logic ctr_drbg_gen_sfifo_ggenbits_err_sum; logic [2:0] ctr_drbg_gen_sfifo_ggenbits_err; + logic block_encrypt_sfifo_blkenc_err_sum; logic [2:0] block_encrypt_sfifo_blkenc_err; + logic cmd_stage_sm_err_sum; + logic main_sm_err_sum; + logic main_sm_err; + logic drbg_gen_sm_err_sum; + logic drbg_gen_sm_err; + logic drbg_updbe_sm_err_sum; + logic drbg_updbe_sm_err; + logic drbg_updob_sm_err_sum; + logic drbg_updob_sm_err; + logic aes_cipher_sm_err_sum; + logic aes_cipher_sm_err; + logic fifo_write_err_sum; + logic fifo_read_err_sum; + logic fifo_status_err_sum; + logic [KeyLen-1:0] state_db_rd_key; logic [BlkLen-1:0] state_db_rd_v; logic [CtrLen-1:0] state_db_rd_rc; @@ -229,6 +261,7 @@ logic [NApps-1:0] cmd_stage_sfifo_genbits_err_wr; logic [NApps-1:0] cmd_stage_sfifo_genbits_err_rd; logic [NApps-1:0] cmd_stage_sfifo_genbits_err_st; + logic [NApps-1:0] cmd_stage_sm_err; logic [NApps-1:0] cmd_stage_vld; logic [StateId-1:0] cmd_stage_shid[NApps]; @@ -255,6 +288,7 @@ logic genbits_stage_bus_rd_sw; logic [31:0] genbits_stage_bus_sw; logic genbits_stage_fips_sw; + logic [2:0] pfifo_sw_genbits_depth; logic [14:0] hw_exception_sts; logic lc_hw_debug_not_on; @@ -264,6 +298,8 @@ logic [StateId-1:0] state_db_reg_rd_id; logic [31:0] state_db_reg_rd_val; + logic [30:0] err_code_test_bit; + // flops logic [2:0] acmd_q, acmd_d; logic [3:0] shid_q, shid_d; @@ -340,91 +376,89 @@ prim_intr_hw #( .Width(1) - ) u_intr_hw_cs_fifo_err ( + ) u_intr_hw_cs_fatal_err ( .clk_i (clk_i), .rst_ni (rst_ni), - .event_intr_i (event_cs_fifo_err), - .reg2hw_intr_enable_q_i (reg2hw.intr_enable.cs_fifo_err.q), - .reg2hw_intr_test_q_i (reg2hw.intr_test.cs_fifo_err.q), - .reg2hw_intr_test_qe_i (reg2hw.intr_test.cs_fifo_err.qe), - .reg2hw_intr_state_q_i (reg2hw.intr_state.cs_fifo_err.q), - .hw2reg_intr_state_de_o (hw2reg.intr_state.cs_fifo_err.de), - .hw2reg_intr_state_d_o (hw2reg.intr_state.cs_fifo_err.d), - .intr_o (intr_cs_fifo_err_o) + .event_intr_i (event_cs_fatal_err), + .reg2hw_intr_enable_q_i (reg2hw.intr_enable.cs_fatal_err.q), + .reg2hw_intr_test_q_i (reg2hw.intr_test.cs_fatal_err.q), + .reg2hw_intr_test_qe_i (reg2hw.intr_test.cs_fatal_err.qe), + .reg2hw_intr_state_q_i (reg2hw.intr_state.cs_fatal_err.q), + .hw2reg_intr_state_de_o (hw2reg.intr_state.cs_fatal_err.de), + .hw2reg_intr_state_d_o (hw2reg.intr_state.cs_fatal_err.d), + .intr_o (intr_cs_fatal_err_o) ); // set the interrupt sources - assign event_cs_fifo_err = cs_enable && ( + assign event_cs_fatal_err = cs_enable && ( (|cmd_stage_sfifo_cmd_err_sum) || (|cmd_stage_sfifo_genbits_err_sum) || - (|ctr_drbg_cmd_sfifo_cmdreq_err) || - (|ctr_drbg_cmd_sfifo_rcstage_err) || - (|ctr_drbg_cmd_sfifo_keyvrc_err) || - (|ctr_drbg_upd_sfifo_updreq_err) || - (|ctr_drbg_upd_sfifo_bencreq_err) || - (|ctr_drbg_upd_sfifo_bencack_err) || - (|ctr_drbg_upd_sfifo_pdata_err) || - (|ctr_drbg_upd_sfifo_final_err) || - (|ctr_drbg_gen_sfifo_gbencack_err) || - (|ctr_drbg_gen_sfifo_grcstage_err) || - (|ctr_drbg_gen_sfifo_ggenreq_err) || - (|ctr_drbg_gen_sfifo_gadstage_err) || - (|ctr_drbg_gen_sfifo_ggenbits_err) || - (|block_encrypt_sfifo_blkenc_err)); + ctr_drbg_cmd_sfifo_cmdreq_err_sum || + ctr_drbg_cmd_sfifo_rcstage_err_sum || + ctr_drbg_cmd_sfifo_keyvrc_err_sum || + ctr_drbg_upd_sfifo_updreq_err_sum || + ctr_drbg_upd_sfifo_bencreq_err_sum || + ctr_drbg_upd_sfifo_bencack_err_sum || + ctr_drbg_upd_sfifo_pdata_err_sum || + ctr_drbg_upd_sfifo_final_err_sum || + ctr_drbg_gen_sfifo_gbencack_err_sum || + ctr_drbg_gen_sfifo_grcstage_err_sum || + ctr_drbg_gen_sfifo_ggenreq_err_sum || + ctr_drbg_gen_sfifo_gadstage_err_sum || + ctr_drbg_gen_sfifo_ggenbits_err_sum || + block_encrypt_sfifo_blkenc_err_sum || + cmd_stage_sm_err_sum || + main_sm_err_sum || + drbg_gen_sm_err_sum || + drbg_updbe_sm_err_sum || + drbg_updob_sm_err_sum || + aes_cipher_sm_err_sum || + fifo_write_err_sum || + fifo_read_err_sum || + fifo_status_err_sum); - // set the err code source bits - assign hw2reg.err_code.sfifo_cmd_err.d = 1'b1; - assign hw2reg.err_code.sfifo_cmd_err.de = cs_enable && (|cmd_stage_sfifo_cmd_err_sum); - - assign hw2reg.err_code.sfifo_genbits_err.d = 1'b1; - assign hw2reg.err_code.sfifo_genbits_err.de = cs_enable && (|cmd_stage_sfifo_genbits_err_sum); - - assign hw2reg.err_code.sfifo_cmdreq_err.d = 1'b1; - assign hw2reg.err_code.sfifo_cmdreq_err.de = cs_enable && (|ctr_drbg_cmd_sfifo_cmdreq_err); - - assign hw2reg.err_code.sfifo_rcstage_err.d = 1'b1; - assign hw2reg.err_code.sfifo_rcstage_err.de = cs_enable && (|ctr_drbg_cmd_sfifo_rcstage_err); - - assign hw2reg.err_code.sfifo_keyvrc_err.d = 1'b1; - assign hw2reg.err_code.sfifo_keyvrc_err.de = cs_enable && (|ctr_drbg_cmd_sfifo_keyvrc_err); - - assign hw2reg.err_code.sfifo_updreq_err.d = 1'b1; - assign hw2reg.err_code.sfifo_updreq_err.de = cs_enable && (|ctr_drbg_upd_sfifo_updreq_err); - - assign hw2reg.err_code.sfifo_bencreq_err.d = 1'b1; - assign hw2reg.err_code.sfifo_bencreq_err.de = cs_enable && (|ctr_drbg_upd_sfifo_bencreq_err); - - assign hw2reg.err_code.sfifo_bencack_err.d = 1'b1; - assign hw2reg.err_code.sfifo_bencack_err.de = cs_enable && (|ctr_drbg_upd_sfifo_bencack_err); - - assign hw2reg.err_code.sfifo_pdata_err.d = 1'b1; - assign hw2reg.err_code.sfifo_pdata_err.de = cs_enable && (|ctr_drbg_upd_sfifo_pdata_err); - - assign hw2reg.err_code.sfifo_final_err.d = 1'b1; - assign hw2reg.err_code.sfifo_final_err.de = cs_enable && (|ctr_drbg_upd_sfifo_final_err); - - assign hw2reg.err_code.sfifo_gbencack_err.d = 1'b1; - assign hw2reg.err_code.sfifo_gbencack_err.de = cs_enable && (|ctr_drbg_gen_sfifo_gbencack_err); - - assign hw2reg.err_code.sfifo_grcstage_err.d = 1'b1; - assign hw2reg.err_code.sfifo_grcstage_err.de = cs_enable && (|ctr_drbg_gen_sfifo_grcstage_err); - - assign hw2reg.err_code.sfifo_ggenreq_err.d = 1'b1; - assign hw2reg.err_code.sfifo_ggenreq_err.de = cs_enable && (|ctr_drbg_gen_sfifo_ggenreq_err); - - assign hw2reg.err_code.sfifo_gadstage_err.d = 1'b1; - assign hw2reg.err_code.sfifo_gadstage_err.de = cs_enable && (|ctr_drbg_gen_sfifo_gadstage_err); - - assign hw2reg.err_code.sfifo_ggenbits_err.d = 1'b1; - assign hw2reg.err_code.sfifo_ggenbits_err.de = cs_enable && (|ctr_drbg_gen_sfifo_ggenbits_err); - - assign hw2reg.err_code.sfifo_blkenc_err.d = 1'b1; - assign hw2reg.err_code.sfifo_blkenc_err.de = cs_enable && (|block_encrypt_sfifo_blkenc_err); - - - // set the err code type bits - assign hw2reg.err_code.fifo_write_err.d = 1'b1; - assign hw2reg.err_code.fifo_write_err.de =cs_enable && ( + // set fifo errors that are single instances of source + assign ctr_drbg_cmd_sfifo_cmdreq_err_sum = (|ctr_drbg_cmd_sfifo_cmdreq_err) || + err_code_test_bit[2]; + assign ctr_drbg_cmd_sfifo_rcstage_err_sum = (|ctr_drbg_cmd_sfifo_rcstage_err) || + err_code_test_bit[3]; + assign ctr_drbg_cmd_sfifo_keyvrc_err_sum = (|ctr_drbg_cmd_sfifo_keyvrc_err) || + err_code_test_bit[4]; + assign ctr_drbg_upd_sfifo_updreq_err_sum = (|ctr_drbg_upd_sfifo_updreq_err) || + err_code_test_bit[5]; + assign ctr_drbg_upd_sfifo_bencreq_err_sum = (|ctr_drbg_upd_sfifo_bencreq_err) || + err_code_test_bit[6]; + assign ctr_drbg_upd_sfifo_bencack_err_sum = (|ctr_drbg_upd_sfifo_bencack_err) || + err_code_test_bit[7]; + assign ctr_drbg_upd_sfifo_pdata_err_sum = (|ctr_drbg_upd_sfifo_pdata_err) || + err_code_test_bit[8]; + assign ctr_drbg_upd_sfifo_final_err_sum = (|ctr_drbg_upd_sfifo_final_err) || + err_code_test_bit[9]; + assign ctr_drbg_gen_sfifo_gbencack_err_sum = (|ctr_drbg_gen_sfifo_gbencack_err) || + err_code_test_bit[10]; + assign ctr_drbg_gen_sfifo_grcstage_err_sum = (|ctr_drbg_gen_sfifo_grcstage_err) || + err_code_test_bit[11]; + assign ctr_drbg_gen_sfifo_ggenreq_err_sum = (|ctr_drbg_gen_sfifo_ggenreq_err) || + err_code_test_bit[12]; + assign ctr_drbg_gen_sfifo_gadstage_err_sum = (|ctr_drbg_gen_sfifo_gadstage_err) || + err_code_test_bit[13]; + assign ctr_drbg_gen_sfifo_ggenbits_err_sum = (|ctr_drbg_gen_sfifo_ggenbits_err) || + err_code_test_bit[14]; + assign block_encrypt_sfifo_blkenc_err_sum = (|block_encrypt_sfifo_blkenc_err) || + err_code_test_bit[15]; + assign cmd_stage_sm_err_sum = (|cmd_stage_sm_err) || + err_code_test_bit[20]; + assign main_sm_err_sum = main_sm_err || + err_code_test_bit[21]; + assign drbg_gen_sm_err_sum = drbg_gen_sm_err || + err_code_test_bit[22]; + assign drbg_updbe_sm_err_sum = drbg_updbe_sm_err || + err_code_test_bit[23]; + assign drbg_updob_sm_err_sum = drbg_updob_sm_err || + err_code_test_bit[24]; + assign aes_cipher_sm_err_sum = aes_cipher_sm_err || + err_code_test_bit[25]; + assign fifo_write_err_sum = block_encrypt_sfifo_blkenc_err[2] || ctr_drbg_gen_sfifo_ggenbits_err[2] || ctr_drbg_gen_sfifo_gadstage_err[2] || @@ -440,10 +474,9 @@ ctr_drbg_cmd_sfifo_rcstage_err[2] || ctr_drbg_cmd_sfifo_cmdreq_err[2] || (|cmd_stage_sfifo_genbits_err_wr) || - (|cmd_stage_sfifo_cmd_err_wr)); - - assign hw2reg.err_code.fifo_read_err.d = 1'b1; - assign hw2reg.err_code.fifo_read_err.de =cs_enable && ( + (|cmd_stage_sfifo_cmd_err_wr) || + err_code_test_bit[28]; + assign fifo_read_err_sum = block_encrypt_sfifo_blkenc_err[1] || ctr_drbg_gen_sfifo_ggenbits_err[1] || ctr_drbg_gen_sfifo_gadstage_err[1] || @@ -459,10 +492,9 @@ ctr_drbg_cmd_sfifo_rcstage_err[1] || ctr_drbg_cmd_sfifo_cmdreq_err[1] || (|cmd_stage_sfifo_genbits_err_rd) || - (|cmd_stage_sfifo_cmd_err_rd)); - - assign hw2reg.err_code.fifo_state_err.d = 1'b1; - assign hw2reg.err_code.fifo_state_err.de =cs_enable && ( + (|cmd_stage_sfifo_cmd_err_rd) || + err_code_test_bit[29]; + assign fifo_status_err_sum = block_encrypt_sfifo_blkenc_err[0] || ctr_drbg_gen_sfifo_ggenbits_err[0] || ctr_drbg_gen_sfifo_gadstage_err[0] || @@ -478,9 +510,100 @@ ctr_drbg_cmd_sfifo_rcstage_err[0] || ctr_drbg_cmd_sfifo_cmdreq_err[0] || (|cmd_stage_sfifo_genbits_err_st) || - (|cmd_stage_sfifo_cmd_err_st)); + (|cmd_stage_sfifo_cmd_err_st) || + err_code_test_bit[30]; + + // set the err code source bits + assign hw2reg.err_code.sfifo_cmd_err.d = 1'b1; + assign hw2reg.err_code.sfifo_cmd_err.de = cs_enable && (|cmd_stage_sfifo_cmd_err_sum); + + assign hw2reg.err_code.sfifo_genbits_err.d = 1'b1; + assign hw2reg.err_code.sfifo_genbits_err.de = cs_enable && (|cmd_stage_sfifo_genbits_err_sum); + + assign hw2reg.err_code.sfifo_cmdreq_err.d = 1'b1; + assign hw2reg.err_code.sfifo_cmdreq_err.de = cs_enable && ctr_drbg_cmd_sfifo_cmdreq_err_sum; + + assign hw2reg.err_code.sfifo_rcstage_err.d = 1'b1; + assign hw2reg.err_code.sfifo_rcstage_err.de = cs_enable && ctr_drbg_cmd_sfifo_rcstage_err_sum; + + assign hw2reg.err_code.sfifo_keyvrc_err.d = 1'b1; + assign hw2reg.err_code.sfifo_keyvrc_err.de = cs_enable && ctr_drbg_cmd_sfifo_keyvrc_err_sum; + + assign hw2reg.err_code.sfifo_updreq_err.d = 1'b1; + assign hw2reg.err_code.sfifo_updreq_err.de = cs_enable && ctr_drbg_upd_sfifo_updreq_err_sum; + + assign hw2reg.err_code.sfifo_bencreq_err.d = 1'b1; + assign hw2reg.err_code.sfifo_bencreq_err.de = cs_enable && ctr_drbg_upd_sfifo_bencreq_err_sum; + + assign hw2reg.err_code.sfifo_bencack_err.d = 1'b1; + assign hw2reg.err_code.sfifo_bencack_err.de = cs_enable && ctr_drbg_upd_sfifo_bencack_err_sum; + + assign hw2reg.err_code.sfifo_pdata_err.d = 1'b1; + assign hw2reg.err_code.sfifo_pdata_err.de = cs_enable && ctr_drbg_upd_sfifo_pdata_err_sum; + + assign hw2reg.err_code.sfifo_final_err.d = 1'b1; + assign hw2reg.err_code.sfifo_final_err.de = cs_enable && ctr_drbg_upd_sfifo_final_err_sum; + + assign hw2reg.err_code.sfifo_gbencack_err.d = 1'b1; + assign hw2reg.err_code.sfifo_gbencack_err.de = cs_enable && ctr_drbg_gen_sfifo_gbencack_err_sum; + + assign hw2reg.err_code.sfifo_grcstage_err.d = 1'b1; + assign hw2reg.err_code.sfifo_grcstage_err.de = cs_enable && ctr_drbg_gen_sfifo_grcstage_err_sum; + + assign hw2reg.err_code.sfifo_ggenreq_err.d = 1'b1; + assign hw2reg.err_code.sfifo_ggenreq_err.de = cs_enable && ctr_drbg_gen_sfifo_ggenreq_err_sum; + + assign hw2reg.err_code.sfifo_gadstage_err.d = 1'b1; + assign hw2reg.err_code.sfifo_gadstage_err.de = cs_enable && ctr_drbg_gen_sfifo_gadstage_err_sum; + + assign hw2reg.err_code.sfifo_ggenbits_err.d = 1'b1; + assign hw2reg.err_code.sfifo_ggenbits_err.de = cs_enable && ctr_drbg_gen_sfifo_ggenbits_err_sum; + + assign hw2reg.err_code.sfifo_blkenc_err.d = 1'b1; + assign hw2reg.err_code.sfifo_blkenc_err.de = cs_enable && block_encrypt_sfifo_blkenc_err_sum; + + assign hw2reg.err_code.cmd_stage_sm_err.d = 1'b1; + assign hw2reg.err_code.cmd_stage_sm_err.de = cs_enable && cmd_stage_sm_err_sum; + + assign hw2reg.err_code.main_sm_err.d = 1'b1; + assign hw2reg.err_code.main_sm_err.de = cs_enable && main_sm_err_sum; + + assign hw2reg.err_code.drbg_gen_sm_err.d = 1'b1; + assign hw2reg.err_code.drbg_gen_sm_err.de = cs_enable && drbg_gen_sm_err_sum; + + assign hw2reg.err_code.drbg_updbe_sm_err.d = 1'b1; + assign hw2reg.err_code.drbg_updbe_sm_err.de = cs_enable && drbg_updbe_sm_err_sum; + + assign hw2reg.err_code.drbg_updob_sm_err.d = 1'b1; + assign hw2reg.err_code.drbg_updob_sm_err.de = cs_enable && drbg_updob_sm_err_sum; + + assign hw2reg.err_code.aes_cipher_sm_err.d = 1'b1; + assign hw2reg.err_code.aes_cipher_sm_err.de = cs_enable && aes_cipher_sm_err_sum; + // set the err code type bits + assign hw2reg.err_code.fifo_write_err.d = 1'b1; + assign hw2reg.err_code.fifo_write_err.de = cs_enable && fifo_write_err_sum; + + assign hw2reg.err_code.fifo_read_err.d = 1'b1; + assign hw2reg.err_code.fifo_read_err.de = cs_enable && fifo_read_err_sum; + + assign hw2reg.err_code.fifo_state_err.d = 1'b1; + assign hw2reg.err_code.fifo_state_err.de = cs_enable && fifo_status_err_sum; + + // Error forcing + for (genvar i = 0; i < 31; i = i+1) begin : gen_err_code_test_bit + assign err_code_test_bit[i] = (reg2hw.err_code_test.q == i) && reg2hw.err_code_test.qe; + end : gen_err_code_test_bit + + // alert - send all interrupt sources to the alert for the fatal case + assign fatal_alert_o = event_cs_fatal_err; + + // alert test + assign alert_test_o = { + reg2hw.alert_test.q & + reg2hw.alert_test.qe + }; // master module enable assign cs_enable = reg2hw.ctrl.enable.q; @@ -529,7 +652,8 @@ .genbits_bus_o (genbits_stage_bus[ai]), .genbits_fips_o (genbits_stage_fips[ai]), .cmd_stage_sfifo_cmd_err_o (cmd_stage_sfifo_cmd_err[ai]), - .cmd_stage_sfifo_genbits_err_o (cmd_stage_sfifo_genbits_err[ai]) + .cmd_stage_sfifo_genbits_err_o (cmd_stage_sfifo_genbits_err[ai]), + .cmd_stage_sm_err_o (cmd_stage_sm_err[ai]) ); end : gen_cmd_stage @@ -566,7 +690,7 @@ .rvalid_o (genbits_stage_vldo_sw), .rdata_o (genbits_stage_bus_sw), .rready_i (genbits_stage_bus_rd_sw), - .depth_o () + .depth_o (pfifo_sw_genbits_depth) ); // flops for SW fips status @@ -605,11 +729,13 @@ // set fifo err status bits for (genvar i = 0; i < NApps; i = i+1) begin : gen_fifo_sts - assign cmd_stage_sfifo_cmd_err_sum[i] = |cmd_stage_sfifo_cmd_err[i]; + assign cmd_stage_sfifo_cmd_err_sum[i] = (|cmd_stage_sfifo_cmd_err[i] || + err_code_test_bit[0]); assign cmd_stage_sfifo_cmd_err_wr[i] = cmd_stage_sfifo_cmd_err[i][0]; assign cmd_stage_sfifo_cmd_err_rd[i] = cmd_stage_sfifo_cmd_err[i][1]; assign cmd_stage_sfifo_cmd_err_st[i] = cmd_stage_sfifo_cmd_err[i][2]; - assign cmd_stage_sfifo_genbits_err_sum[i] = |cmd_stage_sfifo_genbits_err[i]; + assign cmd_stage_sfifo_genbits_err_sum[i] = (|cmd_stage_sfifo_genbits_err[i] || + err_code_test_bit[1]); assign cmd_stage_sfifo_genbits_err_wr[i] = cmd_stage_sfifo_genbits_err[i][0]; assign cmd_stage_sfifo_genbits_err_rd[i] = cmd_stage_sfifo_genbits_err[i][1]; assign cmd_stage_sfifo_genbits_err_st[i] = cmd_stage_sfifo_genbits_err[i][2]; @@ -669,7 +795,8 @@ .reseed_req_o(reseed_req), .generate_req_o(generate_req), .update_req_o(update_req), - .uninstant_req_o(uninstant_req) + .uninstant_req_o(uninstant_req), + .main_sm_err_o(main_sm_err) ); @@ -944,7 +1071,9 @@ .ctr_drbg_upd_sfifo_bencreq_err_o(ctr_drbg_upd_sfifo_bencreq_err), .ctr_drbg_upd_sfifo_bencack_err_o(ctr_drbg_upd_sfifo_bencack_err), .ctr_drbg_upd_sfifo_pdata_err_o(ctr_drbg_upd_sfifo_pdata_err), - .ctr_drbg_upd_sfifo_final_err_o(ctr_drbg_upd_sfifo_final_err) + .ctr_drbg_upd_sfifo_final_err_o(ctr_drbg_upd_sfifo_final_err), + .ctr_drbg_updbe_sm_err_o(drbg_updbe_sm_err), + .ctr_drbg_updob_sm_err_o(drbg_updob_sm_err) ); // update block arbiter @@ -1036,6 +1165,7 @@ .block_encrypt_cmd_o(benblk_cmd), .block_encrypt_id_o(benblk_inst_id), .block_encrypt_v_o(benblk_v), + .block_encrypt_aes_cipher_sm_err_o(aes_cipher_sm_err), .block_encrypt_sfifo_blkenc_err_o(block_encrypt_sfifo_blkenc_err) ); @@ -1143,7 +1273,8 @@ .ctr_drbg_gen_sfifo_grcstage_err_o(ctr_drbg_gen_sfifo_grcstage_err), .ctr_drbg_gen_sfifo_ggenreq_err_o(ctr_drbg_gen_sfifo_ggenreq_err), .ctr_drbg_gen_sfifo_gadstage_err_o(ctr_drbg_gen_sfifo_gadstage_err), - .ctr_drbg_gen_sfifo_ggenbits_err_o(ctr_drbg_gen_sfifo_ggenbits_err) + .ctr_drbg_gen_sfifo_ggenbits_err_o(ctr_drbg_gen_sfifo_ggenbits_err), + .ctr_drbg_gen_sm_err_o(drbg_gen_sm_err) ); @@ -1156,16 +1287,17 @@ assign hw2reg.hw_exc_sts.de = cs_enable; assign hw2reg.hw_exc_sts.d = hw_exception_sts; - // TODO: add depths or remove assign hw2reg.sum_sts.fifo_depth_sts.de = cs_enable; assign hw2reg.sum_sts.fifo_depth_sts.d = - (fifo_sel == 4'h0) ? 24'b0 : + (fifo_sel == 4'h0) ? {21'b0,pfifo_sw_genbits_depth} : 24'b0; assign hw2reg.sum_sts.diag.de = !cs_enable; assign hw2reg.sum_sts.diag.d = - (reg2hw.regwen.q) && // not used - (|reg2hw.genbits.q) && // not used + (|err_code_test_bit[19:16]) && // not used + (|err_code_test_bit[27:26]) && // not used + (reg2hw.regwen.q) && // not used + (|reg2hw.genbits.q) && // not used (|reg2hw.int_state_val.q); // not used
diff --git a/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv b/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv index 069c157..37eab59 100644 --- a/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv +++ b/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv
@@ -96,7 +96,7 @@ logic sfifo_cmdreq_push; logic [CmdreqFifoWidth-1:0] sfifo_cmdreq_wdata; logic sfifo_cmdreq_pop; - logic sfifo_cmdreq_not_full; + logic sfifo_cmdreq_full; logic sfifo_cmdreq_not_empty; // rcstage fifo @@ -104,7 +104,7 @@ logic sfifo_rcstage_push; logic [RCStageFifoWidth-1:0] sfifo_rcstage_wdata; logic sfifo_rcstage_pop; - logic sfifo_rcstage_not_full; + logic sfifo_rcstage_full; logic sfifo_rcstage_not_empty; // keyvrc fifo @@ -112,7 +112,7 @@ logic sfifo_keyvrc_push; logic [KeyVRCFifoWidth-1:0] sfifo_keyvrc_wdata; logic sfifo_keyvrc_pop; - logic sfifo_keyvrc_not_full; + logic sfifo_keyvrc_full; logic sfifo_keyvrc_not_empty; @@ -129,12 +129,12 @@ .rst_ni (rst_ni), .clr_i (!ctr_drbg_cmd_enable_i), .wvalid_i (sfifo_cmdreq_push), - .wready_o (sfifo_cmdreq_not_full), + .wready_o (), .wdata_i (sfifo_cmdreq_wdata), .rvalid_o (sfifo_cmdreq_not_empty), .rready_i (sfifo_cmdreq_pop), .rdata_o (sfifo_cmdreq_rdata), - .full_o (), + .full_o (sfifo_cmdreq_full), .depth_o () ); @@ -154,12 +154,12 @@ cmdreq_entropy_fips,cmdreq_entropy,cmdreq_adata, cmdreq_id,cmdreq_ccmd} = sfifo_cmdreq_rdata; - assign ctr_drbg_cmd_rdy_o = sfifo_cmdreq_not_full; + assign ctr_drbg_cmd_rdy_o = !sfifo_cmdreq_full; assign ctr_drbg_cmd_sfifo_cmdreq_err_o = - {(sfifo_cmdreq_push && !sfifo_cmdreq_not_full), + {(sfifo_cmdreq_push && sfifo_cmdreq_full), (sfifo_cmdreq_pop && !sfifo_cmdreq_not_empty), - (!sfifo_cmdreq_not_full && !sfifo_cmdreq_not_empty)}; + (sfifo_cmdreq_full && !sfifo_cmdreq_not_empty)}; //-------------------------------------------- @@ -217,12 +217,12 @@ .rst_ni (rst_ni), .clr_i (!ctr_drbg_cmd_enable_i), .wvalid_i (sfifo_rcstage_push), - .wready_o (sfifo_rcstage_not_full), + .wready_o (), .wdata_i (sfifo_rcstage_wdata), .rvalid_o (sfifo_rcstage_not_empty), .rready_i (sfifo_rcstage_pop), .rdata_o (sfifo_rcstage_rdata), - .full_o (), + .full_o (sfifo_rcstage_full), .depth_o () ); @@ -233,11 +233,11 @@ assign ctr_drbg_cmd_sfifo_rcstage_err_o = - {(sfifo_rcstage_push && !sfifo_rcstage_not_full), + {(sfifo_rcstage_push && sfifo_rcstage_full), (sfifo_rcstage_pop && !sfifo_rcstage_not_empty), - (!sfifo_rcstage_not_full && !sfifo_rcstage_not_empty)}; + (sfifo_rcstage_full && !sfifo_rcstage_not_empty)}; - assign cmd_upd_rdy_o = sfifo_rcstage_not_empty && sfifo_keyvrc_not_full; + assign cmd_upd_rdy_o = sfifo_rcstage_not_empty && !sfifo_keyvrc_full; //-------------------------------------------- // final cmd block processing @@ -252,12 +252,12 @@ .rst_ni (rst_ni), .clr_i (!ctr_drbg_cmd_enable_i), .wvalid_i (sfifo_keyvrc_push), - .wready_o (sfifo_keyvrc_not_full), + .wready_o (), .wdata_i (sfifo_keyvrc_wdata), .rvalid_o (sfifo_keyvrc_not_empty), .rready_i (sfifo_keyvrc_pop), .rdata_o (sfifo_keyvrc_rdata), - .full_o (), + .full_o (sfifo_keyvrc_full), .depth_o () ); @@ -275,9 +275,9 @@ ctr_drbg_cmd_inst_id_o,ctr_drbg_cmd_ccmd_o} = sfifo_keyvrc_rdata; assign ctr_drbg_cmd_sfifo_keyvrc_err_o = - {(sfifo_keyvrc_push && !sfifo_keyvrc_not_full), + {(sfifo_keyvrc_push && sfifo_keyvrc_full), (sfifo_keyvrc_pop && !sfifo_keyvrc_not_empty), - (!sfifo_keyvrc_not_full && !sfifo_keyvrc_not_empty)}; + (sfifo_keyvrc_full && !sfifo_keyvrc_not_empty)}; // block ack assign ctr_drbg_cmd_ack_o = sfifo_keyvrc_pop;
diff --git a/hw/ip/csrng/rtl/csrng_ctr_drbg_gen.sv b/hw/ip/csrng/rtl/csrng_ctr_drbg_gen.sv index a918563..87fba90 100644 --- a/hw/ip/csrng/rtl/csrng_ctr_drbg_gen.sv +++ b/hw/ip/csrng/rtl/csrng_ctr_drbg_gen.sv
@@ -73,7 +73,8 @@ output logic [2:0] ctr_drbg_gen_sfifo_grcstage_err_o, output logic [2:0] ctr_drbg_gen_sfifo_ggenreq_err_o, output logic [2:0] ctr_drbg_gen_sfifo_gadstage_err_o, - output logic [2:0] ctr_drbg_gen_sfifo_ggenbits_err_o + output logic [2:0] ctr_drbg_gen_sfifo_ggenbits_err_o, + output logic ctr_drbg_gen_sm_err_o ); localparam int GenreqFifoDepth = 1; @@ -116,7 +117,7 @@ logic sfifo_genreq_push; logic [GenreqFifoWidth-1:0] sfifo_genreq_wdata; logic sfifo_genreq_pop; - logic sfifo_genreq_not_full; + logic sfifo_genreq_full; logic sfifo_genreq_not_empty; // adstage fifo @@ -124,14 +125,14 @@ logic sfifo_adstage_push; logic [AdstageFifoWidth-1:0] sfifo_adstage_wdata; logic sfifo_adstage_pop; - logic sfifo_adstage_not_full; + logic sfifo_adstage_full; logic sfifo_adstage_not_empty; // blk_encrypt_ack fifo logic [BlkEncAckFifoWidth-1:0] sfifo_bencack_rdata; logic sfifo_bencack_push; logic [BlkEncAckFifoWidth-1:0] sfifo_bencack_wdata; logic sfifo_bencack_pop; - logic sfifo_bencack_not_full; + logic sfifo_bencack_full; logic sfifo_bencack_not_empty; // breakout logic [Cmd-1:0] sfifo_bencack_ccmd; @@ -143,7 +144,7 @@ logic sfifo_rcstage_push; logic [RCStageFifoWidth-1:0] sfifo_rcstage_wdata; logic sfifo_rcstage_pop; - logic sfifo_rcstage_not_full; + logic sfifo_rcstage_full; logic sfifo_rcstage_not_empty; // genbits fifo @@ -151,7 +152,7 @@ logic sfifo_genbits_push; logic [GenbitsFifoWidth-1:0] sfifo_genbits_wdata; logic sfifo_genbits_pop; - logic sfifo_genbits_not_full; + logic sfifo_genbits_full; logic sfifo_genbits_not_empty; logic [CtrLen-1:0] v_inc; @@ -166,22 +167,30 @@ logic [CtrLen-1:0] v_ctr_q, v_ctr_d; logic [1:0] interate_ctr_q, interate_ctr_d; - // Encoding generated with ./sparse-fsm-encode.py -d 3 -m 2 -n 4 -s 352244715 - // Hamming distance histogram: - // - // 0: -- - // 1: -- - // 2: -- - // 3: -- - // 4: |||||||||||||||||||| (100.00%) - // - // Minimum Hamming distance: 4 - // Maximum Hamming distance: 4 - // - localparam int StateWidth = 4; +// Encoding generated with: +// $ ./util/design/sparse-fsm-encode.py -d 3 -m 3 -n 5 \ +// -s 214010139 --language=sv +// +// Hamming distance histogram: +// +// 0: -- +// 1: -- +// 2: -- +// 3: |||||||||||||||||||| (66.67%) +// 4: |||||||||| (33.33%) +// 5: -- +// +// Minimum Hamming distance: 3 +// Maximum Hamming distance: 4 +// Minimum Hamming weight: 2 +// Maximum Hamming weight: 3 +// + + localparam int StateWidth = 5; typedef enum logic [StateWidth-1:0] { - ReqIdle = 4'b1010, - ReqSend = 4'b0101 + ReqIdle = 5'b01011, + ReqSend = 5'b10001, + ReqError = 5'b10110 } state_e; state_e state_d, state_q; @@ -226,12 +235,12 @@ .rst_ni (rst_ni), .clr_i (!ctr_drbg_gen_enable_i), .wvalid_i (sfifo_genreq_push), - .wready_o (sfifo_genreq_not_full), + .wready_o (), .wdata_i (sfifo_genreq_wdata), .rvalid_o (sfifo_genreq_not_empty), .rready_i (sfifo_genreq_pop), .rdata_o (sfifo_genreq_rdata), - .full_o (), + .full_o (sfifo_genreq_full), .depth_o () ); @@ -247,12 +256,12 @@ genreq_fips,genreq_adata, genreq_id,genreq_ccmd} = sfifo_genreq_rdata; - assign ctr_drbg_gen_rdy_o = sfifo_genreq_not_full; + assign ctr_drbg_gen_rdy_o = !sfifo_genreq_full; assign ctr_drbg_gen_sfifo_ggenreq_err_o = - {(sfifo_genreq_push && !sfifo_genreq_not_full), + {(sfifo_genreq_push && sfifo_genreq_full), (sfifo_genreq_pop && !sfifo_genreq_not_empty), - (!sfifo_genreq_not_full && !sfifo_genreq_not_empty)}; + (sfifo_genreq_full && !sfifo_genreq_not_empty)}; @@ -300,15 +309,17 @@ sfifo_adstage_push = 1'b0; block_encrypt_req_o = 1'b0; sfifo_genreq_pop = 1'b0; + ctr_drbg_gen_sm_err_o = 1'b0; unique case (state_q) // ReqIdle: increment v this cycle, push in next - ReqIdle: - if (sfifo_genreq_not_empty && sfifo_adstage_not_full) begin + ReqIdle: begin + if (sfifo_genreq_not_empty && !sfifo_adstage_full) begin v_ctr_load = 1'b1; sfifo_adstage_push = 1'b1; state_d = ReqSend; end - ReqSend: + end + ReqSend: begin if (!interate_ctr_done) begin block_encrypt_req_o = 1'b1; if (block_encrypt_rdy_i) begin @@ -319,7 +330,11 @@ sfifo_genreq_pop = 1'b1; state_d = ReqIdle; end - default: state_d = ReqIdle; + end + ReqError: begin + ctr_drbg_gen_sm_err_o = 1'b1; + end + default: state_d = ReqError; endcase end @@ -337,24 +352,23 @@ .rst_ni (rst_ni), .clr_i (!ctr_drbg_gen_enable_i), .wvalid_i (sfifo_adstage_push), - .wready_o (sfifo_adstage_not_full), + .wready_o (), .wdata_i (sfifo_adstage_wdata), .rvalid_o (sfifo_adstage_not_empty), .rready_i (sfifo_adstage_pop), .rdata_o (sfifo_adstage_rdata), - .full_o (), + .full_o (sfifo_adstage_full), .depth_o () ); -// assign sfifo_adstage_push = sfifo_genreq_pop; assign sfifo_adstage_wdata = {genreq_key,genreq_v,genreq_rc,genreq_fips,genreq_adata}; assign sfifo_adstage_pop = sfifo_adstage_not_empty && sfifo_bencack_pop; assign {adstage_key,adstage_v,adstage_rc,adstage_fips,adstage_adata} = sfifo_adstage_rdata; assign ctr_drbg_gen_sfifo_gadstage_err_o = - {(sfifo_adstage_push && !sfifo_adstage_not_full), + {(sfifo_adstage_push && sfifo_adstage_full), (sfifo_adstage_pop && !sfifo_adstage_not_empty), - (!sfifo_adstage_not_full && !sfifo_adstage_not_empty)}; + (sfifo_adstage_full && !sfifo_adstage_not_empty)}; @@ -371,29 +385,29 @@ .rst_ni (rst_ni), .clr_i (!ctr_drbg_gen_enable_i), .wvalid_i (sfifo_bencack_push), - .wready_o (sfifo_bencack_not_full), + .wready_o (), .wdata_i (sfifo_bencack_wdata), .rvalid_o (sfifo_bencack_not_empty), .rready_i (sfifo_bencack_pop), .rdata_o (sfifo_bencack_rdata), - .full_o (), + .full_o (sfifo_bencack_full), .depth_o () ); assign bencack_ccmd_modified = (block_encrypt_ccmd_i == GENB) ? GENU : INV; - assign sfifo_bencack_push = sfifo_bencack_not_full && block_encrypt_ack_i; + assign sfifo_bencack_push = !sfifo_bencack_full && block_encrypt_ack_i; assign sfifo_bencack_wdata = {block_encrypt_v_i,block_encrypt_inst_id_i,bencack_ccmd_modified}; - assign block_encrypt_rdy_o = sfifo_bencack_not_full; + assign block_encrypt_rdy_o = !sfifo_bencack_full; - assign sfifo_bencack_pop = sfifo_rcstage_not_full && sfifo_bencack_not_empty && upd_gen_rdy_i; + assign sfifo_bencack_pop = !sfifo_rcstage_full && sfifo_bencack_not_empty && upd_gen_rdy_i; assign {sfifo_bencack_bits,sfifo_bencack_inst_id,sfifo_bencack_ccmd} = sfifo_bencack_rdata; assign ctr_drbg_gen_sfifo_gbencack_err_o = - {(sfifo_bencack_push && !sfifo_bencack_not_full), + {(sfifo_bencack_push && sfifo_bencack_full), (sfifo_bencack_pop && !sfifo_bencack_not_empty), - (!sfifo_bencack_not_full && !sfifo_bencack_not_empty)}; + (sfifo_bencack_full && !sfifo_bencack_not_empty)}; //-------------------------------------------- @@ -423,12 +437,12 @@ .rst_ni (rst_ni), .clr_i (!ctr_drbg_gen_enable_i), .wvalid_i (sfifo_rcstage_push), - .wready_o (sfifo_rcstage_not_full), + .wready_o (), .wdata_i (sfifo_rcstage_wdata), .rvalid_o (sfifo_rcstage_not_empty), .rready_i (sfifo_rcstage_pop), .rdata_o (sfifo_rcstage_rdata), - .full_o (), + .full_o (sfifo_rcstage_full), .depth_o () ); @@ -439,11 +453,11 @@ assign ctr_drbg_gen_sfifo_grcstage_err_o = - {(sfifo_rcstage_push && !sfifo_rcstage_not_full), + {(sfifo_rcstage_push && sfifo_rcstage_full), (sfifo_rcstage_pop && !sfifo_rcstage_not_empty), - (!sfifo_rcstage_not_full && !sfifo_rcstage_not_empty)}; + (sfifo_rcstage_full && !sfifo_rcstage_not_empty)}; - assign gen_upd_rdy_o = sfifo_rcstage_not_empty && sfifo_genbits_not_full; + assign gen_upd_rdy_o = sfifo_rcstage_not_empty && !sfifo_genbits_full; //-------------------------------------------- @@ -459,12 +473,12 @@ .rst_ni (rst_ni), .clr_i (!ctr_drbg_gen_enable_i), .wvalid_i (sfifo_genbits_push), - .wready_o (sfifo_genbits_not_full), + .wready_o (), .wdata_i (sfifo_genbits_wdata), .rvalid_o (sfifo_genbits_not_empty), .rready_i (sfifo_genbits_pop), .rdata_o (sfifo_genbits_rdata), - .full_o (), + .full_o (sfifo_genbits_full), .depth_o () ); @@ -482,9 +496,9 @@ ctr_drbg_gen_inst_id_o,ctr_drbg_gen_ccmd_o} = sfifo_genbits_rdata; assign ctr_drbg_gen_sfifo_ggenbits_err_o = - {(sfifo_genbits_push && !sfifo_genbits_not_full), + {(sfifo_genbits_push && sfifo_genbits_full), (sfifo_genbits_pop && !sfifo_genbits_not_empty), - (!sfifo_genbits_not_full && !sfifo_genbits_not_empty)}; + (sfifo_genbits_full && !sfifo_genbits_not_empty)}; // block ack assign ctr_drbg_gen_ack_o = sfifo_genbits_pop;
diff --git a/hw/ip/csrng/rtl/csrng_ctr_drbg_upd.sv b/hw/ip/csrng/rtl/csrng_ctr_drbg_upd.sv index 64fef2b..3e198bd 100644 --- a/hw/ip/csrng/rtl/csrng_ctr_drbg_upd.sv +++ b/hw/ip/csrng/rtl/csrng_ctr_drbg_upd.sv
@@ -48,7 +48,9 @@ output logic [2:0] ctr_drbg_upd_sfifo_bencreq_err_o, output logic [2:0] ctr_drbg_upd_sfifo_bencack_err_o, output logic [2:0] ctr_drbg_upd_sfifo_pdata_err_o, - output logic [2:0] ctr_drbg_upd_sfifo_final_err_o + output logic [2:0] ctr_drbg_upd_sfifo_final_err_o, + output logic ctr_drbg_updbe_sm_err_o, + output logic ctr_drbg_updob_sm_err_o ); localparam int UpdReqFifoDepth = 1; @@ -73,7 +75,7 @@ logic sfifo_updreq_push; logic [UpdReqFifoWidth-1:0] sfifo_updreq_wdata; logic sfifo_updreq_pop; - logic sfifo_updreq_not_full; + logic sfifo_updreq_full; logic sfifo_updreq_not_empty; // breakout logic [Cmd-1:0] sfifo_updreq_ccmd; @@ -87,7 +89,7 @@ logic sfifo_bencreq_push; logic [BlkEncReqFifoWidth-1:0] sfifo_bencreq_wdata; logic sfifo_bencreq_pop; - logic sfifo_bencreq_not_full; + logic sfifo_bencreq_full; logic sfifo_bencreq_not_empty; // breakout logic [Cmd-1:0] sfifo_bencreq_ccmd; @@ -100,7 +102,7 @@ logic sfifo_bencack_push; logic [BlkEncAckFifoWidth-1:0] sfifo_bencack_wdata; logic sfifo_bencack_pop; - logic sfifo_bencack_not_full; + logic sfifo_bencack_full; logic sfifo_bencack_not_empty; // breakout logic [Cmd-1:0] sfifo_bencack_ccmd; @@ -112,7 +114,7 @@ logic sfifo_pdata_push; logic [PDataFifoWidth-1:0] sfifo_pdata_wdata; logic sfifo_pdata_pop; - logic sfifo_pdata_not_full; + logic sfifo_pdata_full; logic sfifo_pdata_not_empty; logic [SeedLen-1:0] sfifo_pdata_v; @@ -121,7 +123,7 @@ logic sfifo_final_push; logic [FinalFifoWidth-1:0] sfifo_final_wdata; logic sfifo_final_pop; - logic sfifo_final_not_full; + logic sfifo_final_full; logic sfifo_final_not_empty; // breakout logic [Cmd-1:0] sfifo_final_ccmd; @@ -142,28 +144,34 @@ logic [CtrLen-1:0] v_ctr_q, v_ctr_d; logic [1:0] interate_ctr_q, interate_ctr_d; logic [1:0] concat_ctr_q, concat_ctr_d; -// logic [1:0] ctr_drbg_upd_sts_q, ctr_drbg_upd_sts_d; logic [SeedLen-1:0] concat_outblk_q, concat_outblk_d; logic [Cmd-1:0] concat_ccmd_q, concat_ccmd_d; logic [StateId-1:0] concat_inst_id_q, concat_inst_id_d; - // Encoding generated with ./sparse-fsm-encode.py -d 3 -m 2 -n 4 -s 2483430365 - // Hamming distance histogram: - // - // 0: -- - // 1: -- - // 2: -- - // 3: |||||||||||||||||||| (100.00%) - // 4: -- - // - // Minimum Hamming distance: 3 - // Maximum Hamming distance: 3 - // +// Encoding generated with: +// $ ./util/design/sparse-fsm-encode.py -d 3 -m 3 -n 5 \ +// -s 2557753240 --language=sv +// +// Hamming distance histogram: +// +// 0: -- +// 1: -- +// 2: -- +// 3: |||||||||||||||||||| (66.67%) +// 4: |||||||||| (33.33%) +// 5: -- +// +// Minimum Hamming distance: 3 +// Maximum Hamming distance: 4 +// Minimum Hamming weight: 2 +// Maximum Hamming weight: 3 +// - localparam int BlkEncStateWidth = 4; + localparam int BlkEncStateWidth = 5; typedef enum logic [BlkEncStateWidth-1:0] { - ReqIdle = 4'b0001, - ReqSend = 4'b0110 + ReqIdle = 5'b00110, + ReqSend = 5'b10011, + BEError = 5'b11100 } blk_enc_state_e; blk_enc_state_e blk_enc_state_d, blk_enc_state_q; @@ -184,26 +192,32 @@ assign blk_enc_state_q = blk_enc_state_e'(blk_enc_state_raw_q); - // Encoding generated with ./sparse-fsm-encode.py -d 3 -m 3 -n 6 -s 4062121537 - // Hamming distance histogram: - // - // 0: -- - // 1: -- - // 2: -- - // 3: |||||||||||||||||||| (66.67%) - // 4: |||||||||| (33.33%) - // 5: -- - // 6: -- - // - // Minimum Hamming distance: 3 - // Maximum Hamming distance: 4 - // +// Encoding generated with: +// $ ./util/design/sparse-fsm-encode.py -d 3 -m 4 -n 6 \ +// -s 400877681 --language=sv +// +// Hamming distance histogram: +// +// 0: -- +// 1: -- +// 2: -- +// 3: |||||||||||||||||||| (66.67%) +// 4: ||||| (16.67%) +// 5: -- +// 6: ||||| (16.67%) +// +// Minimum Hamming distance: 3 +// Maximum Hamming distance: 6 +// Minimum Hamming weight: 2 +// Maximum Hamming weight: 4 +// localparam int OutBlkStateWidth = 6; typedef enum logic [OutBlkStateWidth-1:0] { - AckIdle = 6'b111001, - Load = 6'b011100, - Shift = 6'b110010 + AckIdle = 6'b110110, + Load = 6'b110001, + Shift = 6'b001001, + OBError = 6'b011100 } outblk_state_e; outblk_state_e outblk_state_d, outblk_state_q; @@ -255,27 +269,27 @@ .rst_ni (rst_ni), .clr_i (!ctr_drbg_upd_enable_i), .wvalid_i (sfifo_updreq_push), - .wready_o (sfifo_updreq_not_full), + .wready_o (), .wdata_i (sfifo_updreq_wdata), .rvalid_o (sfifo_updreq_not_empty), .rready_i (sfifo_updreq_pop), .rdata_o (sfifo_updreq_rdata), - .full_o (), + .full_o (sfifo_updreq_full), .depth_o () ); - assign sfifo_updreq_push = sfifo_updreq_not_full && ctr_drbg_upd_req_i; + assign sfifo_updreq_push = !sfifo_updreq_full && ctr_drbg_upd_req_i; assign sfifo_updreq_wdata = {ctr_drbg_upd_key_i,ctr_drbg_upd_v_i,ctr_drbg_upd_pdata_i, ctr_drbg_upd_inst_id_i,ctr_drbg_upd_ccmd_i}; - assign ctr_drbg_upd_rdy_o = sfifo_updreq_not_full; + assign ctr_drbg_upd_rdy_o = !sfifo_updreq_full; assign {sfifo_updreq_key,sfifo_updreq_v,sfifo_updreq_pdata, sfifo_updreq_inst_id,sfifo_updreq_ccmd} = sfifo_updreq_rdata; assign ctr_drbg_upd_sfifo_updreq_err_o = - {(sfifo_updreq_push && !sfifo_updreq_not_full), + {(sfifo_updreq_push && sfifo_updreq_full), (sfifo_updreq_pop && !sfifo_updreq_not_empty), - (!sfifo_updreq_not_full && !sfifo_updreq_not_empty)}; + (sfifo_updreq_full && !sfifo_updreq_not_empty)}; //-------------------------------------------- // prepare value for block_encrypt step @@ -315,17 +329,19 @@ sfifo_pdata_push = 1'b0; sfifo_bencreq_push = 1'b0; sfifo_updreq_pop = 1'b0; + ctr_drbg_updbe_sm_err_o = 1'b0; unique case (blk_enc_state_q) // ReqIdle: increment v this cycle, push in next - ReqIdle: - if (sfifo_updreq_not_empty && sfifo_bencreq_not_full && sfifo_pdata_not_full) begin + ReqIdle: begin + if (sfifo_updreq_not_empty && !sfifo_bencreq_full && !sfifo_pdata_full) begin v_ctr_load = 1'b1; sfifo_pdata_push = 1'b1; blk_enc_state_d = ReqSend; end - ReqSend: + end + ReqSend: begin if (!interate_ctr_done) begin - if (sfifo_bencreq_not_full) begin + if (!sfifo_bencreq_full) begin v_ctr_inc = 1'b1; interate_ctr_inc = 1'b1; sfifo_bencreq_push = 1'b1; @@ -334,7 +350,11 @@ sfifo_updreq_pop = 1'b1; blk_enc_state_d = ReqIdle; end - default: blk_enc_state_d = ReqIdle; + end + BEError: begin + ctr_drbg_updbe_sm_err_o = 1'b1; + end + default: blk_enc_state_d = BEError; endcase // case (blk_enc_state_q) end @@ -351,12 +371,12 @@ .rst_ni (rst_ni), .clr_i (!ctr_drbg_upd_enable_i), .wvalid_i (sfifo_bencreq_push), - .wready_o (sfifo_bencreq_not_full), + .wready_o (), .wdata_i (sfifo_bencreq_wdata), .rvalid_o (sfifo_bencreq_not_empty), .rready_i (sfifo_bencreq_pop), .rdata_o (sfifo_bencreq_rdata), - .full_o (), + .full_o (sfifo_bencreq_full), .depth_o () ); @@ -375,9 +395,9 @@ assign block_encrypt_ccmd_o = sfifo_bencreq_ccmd; assign ctr_drbg_upd_sfifo_bencreq_err_o = - {(sfifo_bencreq_push && !sfifo_bencreq_not_full), + {(sfifo_bencreq_push && sfifo_bencreq_full), (sfifo_bencreq_pop && !sfifo_bencreq_not_empty), - (!sfifo_bencreq_not_full && !sfifo_bencreq_not_empty)}; + (sfifo_bencreq_full && !sfifo_bencreq_not_empty)}; //-------------------------------------------- // block_encrypt response fifo from block encrypt @@ -392,25 +412,25 @@ .rst_ni (rst_ni), .clr_i (!ctr_drbg_upd_enable_i), .wvalid_i (sfifo_bencack_push), - .wready_o (sfifo_bencack_not_full), + .wready_o (), .wdata_i (sfifo_bencack_wdata), .rvalid_o (sfifo_bencack_not_empty), .rready_i (sfifo_bencack_pop), .rdata_o (sfifo_bencack_rdata), - .full_o (), + .full_o (sfifo_bencack_full), .depth_o () ); - assign sfifo_bencack_push = sfifo_bencack_not_full && block_encrypt_ack_i; + assign sfifo_bencack_push = !sfifo_bencack_full && block_encrypt_ack_i; assign sfifo_bencack_wdata = {block_encrypt_v_i,block_encrypt_inst_id_i,block_encrypt_ccmd_i}; - assign block_encrypt_rdy_o = sfifo_bencack_not_full; + assign block_encrypt_rdy_o = !sfifo_bencack_full; assign {sfifo_bencack_v,sfifo_bencack_inst_id,sfifo_bencack_ccmd} = sfifo_bencack_rdata; assign ctr_drbg_upd_sfifo_bencack_err_o = - {(sfifo_bencack_push && !sfifo_bencack_not_full), + {(sfifo_bencack_push && sfifo_bencack_full), (sfifo_bencack_pop && !sfifo_bencack_not_empty), - (!sfifo_bencack_not_full && !sfifo_bencack_not_empty)}; + (sfifo_bencack_full && !sfifo_bencack_not_empty)}; //-------------------------------------------- // fifo to stage provided_data, waiting for blk_encrypt to ack @@ -425,12 +445,12 @@ .rst_ni (rst_ni), .clr_i (!ctr_drbg_upd_enable_i), .wvalid_i (sfifo_pdata_push), - .wready_o (sfifo_pdata_not_full), + .wready_o (), .wdata_i (sfifo_pdata_wdata), .rvalid_o (sfifo_pdata_not_empty), .rready_i (sfifo_pdata_pop), .rdata_o (sfifo_pdata_rdata), - .full_o (), + .full_o (sfifo_pdata_full), .depth_o () ); @@ -439,9 +459,9 @@ assign sfifo_pdata_v = sfifo_pdata_rdata; assign ctr_drbg_upd_sfifo_pdata_err_o = - {(sfifo_pdata_push && !sfifo_pdata_not_full), + {(sfifo_pdata_push && sfifo_pdata_full), (sfifo_pdata_pop && !sfifo_pdata_not_empty), - (!sfifo_pdata_not_full && !sfifo_pdata_not_empty)}; + (sfifo_pdata_full && !sfifo_pdata_not_empty)}; //-------------------------------------------- // shifting logic to receive values from block_encrypt @@ -476,19 +496,22 @@ sfifo_pdata_pop = 1'b0; sfifo_bencack_pop = 1'b0; sfifo_final_push = 1'b0; + ctr_drbg_updob_sm_err_o = 1'b0; unique case (outblk_state_q) // AckIdle: increment v this cycle, push in next - AckIdle: - if (sfifo_bencack_not_empty && sfifo_pdata_not_empty && sfifo_final_not_full) begin + AckIdle: begin + if (sfifo_bencack_not_empty && sfifo_pdata_not_empty && !sfifo_final_full) begin outblk_state_d = Load; end - Load: + end + Load: begin if (sfifo_bencack_not_empty) begin concat_ctr_inc = 1'b1; sfifo_bencack_pop = 1'b1; outblk_state_d = Shift; end - Shift: + end + Shift: begin if (concat_ctr_done) begin sfifo_pdata_pop = 1'b1; sfifo_final_push = 1'b1; @@ -497,6 +520,10 @@ concat_outblk_shift = 1'b1; outblk_state_d = Load; end + end + OBError: begin + ctr_drbg_updob_sm_err_o = 1'b1; + end default: outblk_state_d = AckIdle; endcase end @@ -518,12 +545,12 @@ .rst_ni (rst_ni), .clr_i (!ctr_drbg_upd_enable_i), .wvalid_i (sfifo_final_push), - .wready_o (sfifo_final_not_full), + .wready_o (), .wdata_i (sfifo_final_wdata), .rvalid_o (sfifo_final_not_empty), .rready_i (sfifo_final_pop), .rdata_o (sfifo_final_rdata), - .full_o (), + .full_o (sfifo_final_full), .depth_o () ); @@ -539,9 +566,9 @@ assign ctr_drbg_upd_v_o = sfifo_final_v; assign ctr_drbg_upd_sfifo_final_err_o = - {(sfifo_final_push && !sfifo_final_not_full), + {(sfifo_final_push && sfifo_final_full), (sfifo_final_pop && !sfifo_final_not_empty), - (!sfifo_final_not_full && !sfifo_final_not_empty)}; + (sfifo_final_full && !sfifo_final_not_empty)}; endmodule
diff --git a/hw/ip/csrng/rtl/csrng_main_sm.sv b/hw/ip/csrng/rtl/csrng_main_sm.sv index 390b0f2..824bceb 100644 --- a/hw/ip/csrng/rtl/csrng_main_sm.sv +++ b/hw/ip/csrng/rtl/csrng_main_sm.sv
@@ -23,37 +23,44 @@ output logic reseed_req_o, output logic generate_req_o, output logic update_req_o, - output logic uninstant_req_o + output logic uninstant_req_o, + output logic main_sm_err_o ); - // Encoding generated with ./sparse-fsm-encode.py -d 3 -m 9 -n 8 -s 3053040243 - // Hamming distance histogram: - // - // 0: -- - // 1: -- - // 2: -- - // 3: |||||||||||||||||||| (30.56%) - // 4: |||||||||||||||||||| (30.56%) - // 5: |||||||||||| (19.44%) - // 6: ||||||||| (13.89%) - // 7: ||| (5.56%) - // 8: -- - // - // Minimum Hamming distance: 3 - // Maximum Hamming distance: 7 - // +// Encoding generated with: +// $ ./util/design/sparse-fsm-encode.py -d 3 -m 10 -n 8 \ +// -s 845453599 --language=sv +// +// Hamming distance histogram: +// +// 0: -- +// 1: -- +// 2: -- +// 3: ||||||||||||||| (26.67%) +// 4: |||||||||||||||||||| (35.56%) +// 5: ||||||||||||||| (26.67%) +// 6: ||||| (8.89%) +// 7: -- +// 8: | (2.22%) +// +// Minimum Hamming distance: 3 +// Maximum Hamming distance: 8 +// Minimum Hamming weight: 2 +// Maximum Hamming weight: 7 +// localparam int StateWidth = 8; typedef enum logic [StateWidth-1:0] { - Idle = 8'b01100100, // idle - InstantPrep = 8'b11000010, // instantiate prep - InstantReq = 8'b11000101, // instantiate request (takes adata or entropy) - ReseedPrep = 8'b00010001, // reseed prep - ReseedReq = 8'b10110010, // reseed request (takes adata and entropy and Key,V,RC) - GenerateReq = 8'b01111010, // generate request (takes adata? and Key,V,RC) - UpdatePrep = 8'b00001101, // update prep - UpdateReq = 8'b10101011, // update request (takes adata and Key,V,RC) - UninstantReq = 8'b00101000 // uninstantiate request (no input) + Idle = 8'b10111111, // idle + InstantPrep = 8'b11011101, // instantiate prep + InstantReq = 8'b00010100, // instantiate request (takes adata or entropy) + ReseedPrep = 8'b11000001, // reseed prep + ReseedReq = 8'b01100100, // reseed request (takes adata and entropy and Key,V,RC) + GenerateReq = 8'b10101100, // generate request (takes adata? and Key,V,RC) + UpdatePrep = 8'b11010010, // update prep + UpdateReq = 8'b11111000, // update request (takes adata and Key,V,RC) + UninstantReq = 8'b11101011, // uninstantiate request (no input) + Error = 8'b00001010 // error state, results in fatal alert } state_e; state_e state_d, state_q; @@ -83,6 +90,7 @@ generate_req_o = 1'b0; update_req_o = 1'b0; uninstant_req_o = 1'b0; + main_sm_err_o = 1'b0; unique case (state_q) Idle: begin if (ctr_drbg_cmd_req_rdy_i) begin @@ -154,7 +162,10 @@ uninstant_req_o = 1'b1; state_d = Idle; end - default: state_d = Idle; + Error: begin + main_sm_err_o = 1'b1; + end + default: state_d = Error; endcase end
diff --git a/hw/ip/csrng/rtl/csrng_reg_pkg.sv b/hw/ip/csrng/rtl/csrng_reg_pkg.sv index 132938a..350c5a6 100644 --- a/hw/ip/csrng/rtl/csrng_reg_pkg.sv +++ b/hw/ip/csrng/rtl/csrng_reg_pkg.sv
@@ -8,6 +8,7 @@ // Param list parameter int NHwApps = 2; + parameter int NumAlerts = 1; // Address width within the block parameter int BlockAw = 6; @@ -27,7 +28,7 @@ } cs_hw_inst_exc; struct packed { logic q; - } cs_fifo_err; + } cs_fatal_err; } csrng_reg2hw_intr_state_reg_t; typedef struct packed { @@ -42,7 +43,7 @@ } cs_hw_inst_exc; struct packed { logic q; - } cs_fifo_err; + } cs_fatal_err; } csrng_reg2hw_intr_enable_reg_t; typedef struct packed { @@ -61,11 +62,16 @@ struct packed { logic q; logic qe; - } cs_fifo_err; + } cs_fatal_err; } csrng_reg2hw_intr_test_reg_t; typedef struct packed { logic q; + logic qe; + } csrng_reg2hw_alert_test_reg_t; + + typedef struct packed { + logic q; } csrng_reg2hw_regwen_reg_t; typedef struct packed { @@ -100,6 +106,11 @@ logic re; } csrng_reg2hw_int_state_val_reg_t; + typedef struct packed { + logic [4:0] q; + logic qe; + } csrng_reg2hw_err_code_test_reg_t; + typedef struct packed { struct packed { @@ -117,7 +128,7 @@ struct packed { logic d; logic de; - } cs_fifo_err; + } cs_fatal_err; } csrng_hw2reg_intr_state_reg_t; typedef struct packed { @@ -232,6 +243,30 @@ struct packed { logic d; logic de; + } cmd_stage_sm_err; + struct packed { + logic d; + logic de; + } main_sm_err; + struct packed { + logic d; + logic de; + } drbg_gen_sm_err; + struct packed { + logic d; + logic de; + } drbg_updbe_sm_err; + struct packed { + logic d; + logic de; + } drbg_updob_sm_err; + struct packed { + logic d; + logic de; + } aes_cipher_sm_err; + struct packed { + logic d; + logic de; } fifo_write_err; struct packed { logic d; @@ -248,46 +283,50 @@ // Register to internal design logic // /////////////////////////////////////// typedef struct packed { - csrng_reg2hw_intr_state_reg_t intr_state; // [126:123] - csrng_reg2hw_intr_enable_reg_t intr_enable; // [122:119] - csrng_reg2hw_intr_test_reg_t intr_test; // [118:111] - csrng_reg2hw_regwen_reg_t regwen; // [110:110] - csrng_reg2hw_ctrl_reg_t ctrl; // [109:104] - csrng_reg2hw_cmd_req_reg_t cmd_req; // [103:71] - csrng_reg2hw_genbits_reg_t genbits; // [70:38] - csrng_reg2hw_int_state_num_reg_t int_state_num; // [37:33] - csrng_reg2hw_int_state_val_reg_t int_state_val; // [32:0] + csrng_reg2hw_intr_state_reg_t intr_state; // [134:131] + csrng_reg2hw_intr_enable_reg_t intr_enable; // [130:127] + csrng_reg2hw_intr_test_reg_t intr_test; // [126:119] + csrng_reg2hw_alert_test_reg_t alert_test; // [118:117] + csrng_reg2hw_regwen_reg_t regwen; // [116:116] + csrng_reg2hw_ctrl_reg_t ctrl; // [115:110] + csrng_reg2hw_cmd_req_reg_t cmd_req; // [109:77] + csrng_reg2hw_genbits_reg_t genbits; // [76:44] + csrng_reg2hw_int_state_num_reg_t int_state_num; // [43:39] + csrng_reg2hw_int_state_val_reg_t int_state_val; // [38:6] + csrng_reg2hw_err_code_test_reg_t err_code_test; // [5:0] } csrng_reg2hw_t; /////////////////////////////////////// // Internal design logic to register // /////////////////////////////////////// typedef struct packed { - csrng_hw2reg_intr_state_reg_t intr_state; // [158:151] - csrng_hw2reg_sum_sts_reg_t sum_sts; // [150:124] - csrng_hw2reg_sw_cmd_sts_reg_t sw_cmd_sts; // [123:120] - csrng_hw2reg_genbits_vld_reg_t genbits_vld; // [119:118] - csrng_hw2reg_genbits_reg_t genbits; // [117:86] - csrng_hw2reg_int_state_val_reg_t int_state_val; // [85:54] - csrng_hw2reg_hw_exc_sts_reg_t hw_exc_sts; // [53:38] - csrng_hw2reg_err_code_reg_t err_code; // [37:0] + csrng_hw2reg_intr_state_reg_t intr_state; // [170:163] + csrng_hw2reg_sum_sts_reg_t sum_sts; // [162:136] + csrng_hw2reg_sw_cmd_sts_reg_t sw_cmd_sts; // [135:132] + csrng_hw2reg_genbits_vld_reg_t genbits_vld; // [131:130] + csrng_hw2reg_genbits_reg_t genbits; // [129:98] + csrng_hw2reg_int_state_val_reg_t int_state_val; // [97:66] + csrng_hw2reg_hw_exc_sts_reg_t hw_exc_sts; // [65:50] + csrng_hw2reg_err_code_reg_t err_code; // [49:0] } csrng_hw2reg_t; // Register Address parameter logic [BlockAw-1:0] CSRNG_INTR_STATE_OFFSET = 6'h 0; parameter logic [BlockAw-1:0] CSRNG_INTR_ENABLE_OFFSET = 6'h 4; parameter logic [BlockAw-1:0] CSRNG_INTR_TEST_OFFSET = 6'h 8; - parameter logic [BlockAw-1:0] CSRNG_REGWEN_OFFSET = 6'h c; - parameter logic [BlockAw-1:0] CSRNG_CTRL_OFFSET = 6'h 10; - parameter logic [BlockAw-1:0] CSRNG_SUM_STS_OFFSET = 6'h 14; - parameter logic [BlockAw-1:0] CSRNG_CMD_REQ_OFFSET = 6'h 18; - parameter logic [BlockAw-1:0] CSRNG_SW_CMD_STS_OFFSET = 6'h 1c; - parameter logic [BlockAw-1:0] CSRNG_GENBITS_VLD_OFFSET = 6'h 20; - parameter logic [BlockAw-1:0] CSRNG_GENBITS_OFFSET = 6'h 24; - parameter logic [BlockAw-1:0] CSRNG_INT_STATE_NUM_OFFSET = 6'h 28; - parameter logic [BlockAw-1:0] CSRNG_INT_STATE_VAL_OFFSET = 6'h 2c; - parameter logic [BlockAw-1:0] CSRNG_HW_EXC_STS_OFFSET = 6'h 30; - parameter logic [BlockAw-1:0] CSRNG_ERR_CODE_OFFSET = 6'h 34; + parameter logic [BlockAw-1:0] CSRNG_ALERT_TEST_OFFSET = 6'h c; + parameter logic [BlockAw-1:0] CSRNG_REGWEN_OFFSET = 6'h 10; + parameter logic [BlockAw-1:0] CSRNG_CTRL_OFFSET = 6'h 14; + parameter logic [BlockAw-1:0] CSRNG_SUM_STS_OFFSET = 6'h 18; + parameter logic [BlockAw-1:0] CSRNG_CMD_REQ_OFFSET = 6'h 1c; + parameter logic [BlockAw-1:0] CSRNG_SW_CMD_STS_OFFSET = 6'h 20; + parameter logic [BlockAw-1:0] CSRNG_GENBITS_VLD_OFFSET = 6'h 24; + parameter logic [BlockAw-1:0] CSRNG_GENBITS_OFFSET = 6'h 28; + parameter logic [BlockAw-1:0] CSRNG_INT_STATE_NUM_OFFSET = 6'h 2c; + parameter logic [BlockAw-1:0] CSRNG_INT_STATE_VAL_OFFSET = 6'h 30; + parameter logic [BlockAw-1:0] CSRNG_HW_EXC_STS_OFFSET = 6'h 34; + parameter logic [BlockAw-1:0] CSRNG_ERR_CODE_OFFSET = 6'h 38; + parameter logic [BlockAw-1:0] CSRNG_ERR_CODE_TEST_OFFSET = 6'h 3c; // Register Index @@ -295,6 +334,7 @@ CSRNG_INTR_STATE, CSRNG_INTR_ENABLE, CSRNG_INTR_TEST, + CSRNG_ALERT_TEST, CSRNG_REGWEN, CSRNG_CTRL, CSRNG_SUM_STS, @@ -305,25 +345,28 @@ CSRNG_INT_STATE_NUM, CSRNG_INT_STATE_VAL, CSRNG_HW_EXC_STS, - CSRNG_ERR_CODE + CSRNG_ERR_CODE, + CSRNG_ERR_CODE_TEST } csrng_id_e; // Register width information to check illegal writes - parameter logic [3:0] CSRNG_PERMIT [14] = '{ + parameter logic [3:0] CSRNG_PERMIT [16] = '{ 4'b 0001, // index[ 0] CSRNG_INTR_STATE 4'b 0001, // index[ 1] CSRNG_INTR_ENABLE 4'b 0001, // index[ 2] CSRNG_INTR_TEST - 4'b 0001, // index[ 3] CSRNG_REGWEN - 4'b 0111, // index[ 4] CSRNG_CTRL - 4'b 1111, // index[ 5] CSRNG_SUM_STS - 4'b 1111, // index[ 6] CSRNG_CMD_REQ - 4'b 0001, // index[ 7] CSRNG_SW_CMD_STS - 4'b 0001, // index[ 8] CSRNG_GENBITS_VLD - 4'b 1111, // index[ 9] CSRNG_GENBITS - 4'b 0001, // index[10] CSRNG_INT_STATE_NUM - 4'b 1111, // index[11] CSRNG_INT_STATE_VAL - 4'b 0011, // index[12] CSRNG_HW_EXC_STS - 4'b 1111 // index[13] CSRNG_ERR_CODE + 4'b 0001, // index[ 3] CSRNG_ALERT_TEST + 4'b 0001, // index[ 4] CSRNG_REGWEN + 4'b 0111, // index[ 5] CSRNG_CTRL + 4'b 1111, // index[ 6] CSRNG_SUM_STS + 4'b 1111, // index[ 7] CSRNG_CMD_REQ + 4'b 0001, // index[ 8] CSRNG_SW_CMD_STS + 4'b 0001, // index[ 9] CSRNG_GENBITS_VLD + 4'b 1111, // index[10] CSRNG_GENBITS + 4'b 0001, // index[11] CSRNG_INT_STATE_NUM + 4'b 1111, // index[12] CSRNG_INT_STATE_VAL + 4'b 0011, // index[13] CSRNG_HW_EXC_STS + 4'b 1111, // index[14] CSRNG_ERR_CODE + 4'b 0001 // index[15] CSRNG_ERR_CODE_TEST }; endpackage
diff --git a/hw/ip/csrng/rtl/csrng_reg_top.sv b/hw/ip/csrng/rtl/csrng_reg_top.sv index cab2481..ce7fc8d 100644 --- a/hw/ip/csrng/rtl/csrng_reg_top.sv +++ b/hw/ip/csrng/rtl/csrng_reg_top.sv
@@ -80,9 +80,9 @@ logic intr_state_cs_hw_inst_exc_qs; logic intr_state_cs_hw_inst_exc_wd; logic intr_state_cs_hw_inst_exc_we; - logic intr_state_cs_fifo_err_qs; - logic intr_state_cs_fifo_err_wd; - logic intr_state_cs_fifo_err_we; + logic intr_state_cs_fatal_err_qs; + logic intr_state_cs_fatal_err_wd; + logic intr_state_cs_fatal_err_we; logic intr_enable_cs_cmd_req_done_qs; logic intr_enable_cs_cmd_req_done_wd; logic intr_enable_cs_cmd_req_done_we; @@ -92,17 +92,19 @@ logic intr_enable_cs_hw_inst_exc_qs; logic intr_enable_cs_hw_inst_exc_wd; logic intr_enable_cs_hw_inst_exc_we; - logic intr_enable_cs_fifo_err_qs; - logic intr_enable_cs_fifo_err_wd; - logic intr_enable_cs_fifo_err_we; + logic intr_enable_cs_fatal_err_qs; + logic intr_enable_cs_fatal_err_wd; + logic intr_enable_cs_fatal_err_we; logic intr_test_cs_cmd_req_done_wd; logic intr_test_cs_cmd_req_done_we; logic intr_test_cs_entropy_req_wd; logic intr_test_cs_entropy_req_we; logic intr_test_cs_hw_inst_exc_wd; logic intr_test_cs_hw_inst_exc_we; - logic intr_test_cs_fifo_err_wd; - logic intr_test_cs_fifo_err_we; + logic intr_test_cs_fatal_err_wd; + logic intr_test_cs_fatal_err_we; + logic alert_test_wd; + logic alert_test_we; logic regwen_qs; logic regwen_wd; logic regwen_we; @@ -136,62 +138,33 @@ logic [14:0] hw_exc_sts_wd; logic hw_exc_sts_we; logic err_code_sfifo_cmd_err_qs; - logic err_code_sfifo_cmd_err_wd; - logic err_code_sfifo_cmd_err_we; logic err_code_sfifo_genbits_err_qs; - logic err_code_sfifo_genbits_err_wd; - logic err_code_sfifo_genbits_err_we; logic err_code_sfifo_cmdreq_err_qs; - logic err_code_sfifo_cmdreq_err_wd; - logic err_code_sfifo_cmdreq_err_we; logic err_code_sfifo_rcstage_err_qs; - logic err_code_sfifo_rcstage_err_wd; - logic err_code_sfifo_rcstage_err_we; logic err_code_sfifo_keyvrc_err_qs; - logic err_code_sfifo_keyvrc_err_wd; - logic err_code_sfifo_keyvrc_err_we; logic err_code_sfifo_updreq_err_qs; - logic err_code_sfifo_updreq_err_wd; - logic err_code_sfifo_updreq_err_we; logic err_code_sfifo_bencreq_err_qs; - logic err_code_sfifo_bencreq_err_wd; - logic err_code_sfifo_bencreq_err_we; logic err_code_sfifo_bencack_err_qs; - logic err_code_sfifo_bencack_err_wd; - logic err_code_sfifo_bencack_err_we; logic err_code_sfifo_pdata_err_qs; - logic err_code_sfifo_pdata_err_wd; - logic err_code_sfifo_pdata_err_we; logic err_code_sfifo_final_err_qs; - logic err_code_sfifo_final_err_wd; - logic err_code_sfifo_final_err_we; logic err_code_sfifo_gbencack_err_qs; - logic err_code_sfifo_gbencack_err_wd; - logic err_code_sfifo_gbencack_err_we; logic err_code_sfifo_grcstage_err_qs; - logic err_code_sfifo_grcstage_err_wd; - logic err_code_sfifo_grcstage_err_we; logic err_code_sfifo_ggenreq_err_qs; - logic err_code_sfifo_ggenreq_err_wd; - logic err_code_sfifo_ggenreq_err_we; logic err_code_sfifo_gadstage_err_qs; - logic err_code_sfifo_gadstage_err_wd; - logic err_code_sfifo_gadstage_err_we; logic err_code_sfifo_ggenbits_err_qs; - logic err_code_sfifo_ggenbits_err_wd; - logic err_code_sfifo_ggenbits_err_we; logic err_code_sfifo_blkenc_err_qs; - logic err_code_sfifo_blkenc_err_wd; - logic err_code_sfifo_blkenc_err_we; + logic err_code_cmd_stage_sm_err_qs; + logic err_code_main_sm_err_qs; + logic err_code_drbg_gen_sm_err_qs; + logic err_code_drbg_updbe_sm_err_qs; + logic err_code_drbg_updob_sm_err_qs; + logic err_code_aes_cipher_sm_err_qs; logic err_code_fifo_write_err_qs; - logic err_code_fifo_write_err_wd; - logic err_code_fifo_write_err_we; logic err_code_fifo_read_err_qs; - logic err_code_fifo_read_err_wd; - logic err_code_fifo_read_err_we; logic err_code_fifo_state_err_qs; - logic err_code_fifo_state_err_wd; - logic err_code_fifo_state_err_we; + logic [4:0] err_code_test_qs; + logic [4:0] err_code_test_wd; + logic err_code_test_we; // Register instances // R[intr_state]: V(False) @@ -274,29 +247,29 @@ ); - // F[cs_fifo_err]: 3:3 + // F[cs_fatal_err]: 3:3 prim_subreg #( .DW (1), .SWACCESS("W1C"), .RESVAL (1'h0) - ) u_intr_state_cs_fifo_err ( + ) u_intr_state_cs_fatal_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (intr_state_cs_fifo_err_we), - .wd (intr_state_cs_fifo_err_wd), + .we (intr_state_cs_fatal_err_we), + .wd (intr_state_cs_fatal_err_wd), // from internal hardware - .de (hw2reg.intr_state.cs_fifo_err.de), - .d (hw2reg.intr_state.cs_fifo_err.d ), + .de (hw2reg.intr_state.cs_fatal_err.de), + .d (hw2reg.intr_state.cs_fatal_err.d ), // to internal hardware .qe (), - .q (reg2hw.intr_state.cs_fifo_err.q ), + .q (reg2hw.intr_state.cs_fatal_err.q ), // to register interface (read) - .qs (intr_state_cs_fifo_err_qs) + .qs (intr_state_cs_fatal_err_qs) ); @@ -380,18 +353,18 @@ ); - // F[cs_fifo_err]: 3:3 + // F[cs_fatal_err]: 3:3 prim_subreg #( .DW (1), .SWACCESS("RW"), .RESVAL (1'h0) - ) u_intr_enable_cs_fifo_err ( + ) u_intr_enable_cs_fatal_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (intr_enable_cs_fifo_err_we), - .wd (intr_enable_cs_fifo_err_wd), + .we (intr_enable_cs_fatal_err_we), + .wd (intr_enable_cs_fatal_err_wd), // from internal hardware .de (1'b0), @@ -399,10 +372,10 @@ // to internal hardware .qe (), - .q (reg2hw.intr_enable.cs_fifo_err.q ), + .q (reg2hw.intr_enable.cs_fatal_err.q ), // to register interface (read) - .qs (intr_enable_cs_fifo_err_qs) + .qs (intr_enable_cs_fatal_err_qs) ); @@ -453,17 +426,33 @@ ); - // F[cs_fifo_err]: 3:3 + // F[cs_fatal_err]: 3:3 prim_subreg_ext #( .DW (1) - ) u_intr_test_cs_fifo_err ( + ) u_intr_test_cs_fatal_err ( .re (1'b0), - .we (intr_test_cs_fifo_err_we), - .wd (intr_test_cs_fifo_err_wd), + .we (intr_test_cs_fatal_err_we), + .wd (intr_test_cs_fatal_err_wd), .d ('0), .qre (), - .qe (reg2hw.intr_test.cs_fifo_err.qe), - .q (reg2hw.intr_test.cs_fifo_err.q ), + .qe (reg2hw.intr_test.cs_fatal_err.qe), + .q (reg2hw.intr_test.cs_fatal_err.q ), + .qs () + ); + + + // R[alert_test]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_alert_test ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_wd), + .d ('0), + .qre (), + .qe (reg2hw.alert_test.qe), + .q (reg2hw.alert_test.q ), .qs () ); @@ -828,15 +817,14 @@ // F[sfifo_cmd_err]: 0:0 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_cmd_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_cmd_err_we), - .wd (err_code_sfifo_cmd_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_cmd_err.de), @@ -854,15 +842,14 @@ // F[sfifo_genbits_err]: 1:1 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_genbits_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_genbits_err_we), - .wd (err_code_sfifo_genbits_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_genbits_err.de), @@ -880,15 +867,14 @@ // F[sfifo_cmdreq_err]: 2:2 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_cmdreq_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_cmdreq_err_we), - .wd (err_code_sfifo_cmdreq_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_cmdreq_err.de), @@ -906,15 +892,14 @@ // F[sfifo_rcstage_err]: 3:3 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_rcstage_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_rcstage_err_we), - .wd (err_code_sfifo_rcstage_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_rcstage_err.de), @@ -932,15 +917,14 @@ // F[sfifo_keyvrc_err]: 4:4 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_keyvrc_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_keyvrc_err_we), - .wd (err_code_sfifo_keyvrc_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_keyvrc_err.de), @@ -958,15 +942,14 @@ // F[sfifo_updreq_err]: 5:5 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_updreq_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_updreq_err_we), - .wd (err_code_sfifo_updreq_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_updreq_err.de), @@ -984,15 +967,14 @@ // F[sfifo_bencreq_err]: 6:6 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_bencreq_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_bencreq_err_we), - .wd (err_code_sfifo_bencreq_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_bencreq_err.de), @@ -1010,15 +992,14 @@ // F[sfifo_bencack_err]: 7:7 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_bencack_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_bencack_err_we), - .wd (err_code_sfifo_bencack_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_bencack_err.de), @@ -1036,15 +1017,14 @@ // F[sfifo_pdata_err]: 8:8 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_pdata_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_pdata_err_we), - .wd (err_code_sfifo_pdata_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_pdata_err.de), @@ -1062,15 +1042,14 @@ // F[sfifo_final_err]: 9:9 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_final_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_final_err_we), - .wd (err_code_sfifo_final_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_final_err.de), @@ -1088,15 +1067,14 @@ // F[sfifo_gbencack_err]: 10:10 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_gbencack_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_gbencack_err_we), - .wd (err_code_sfifo_gbencack_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_gbencack_err.de), @@ -1114,15 +1092,14 @@ // F[sfifo_grcstage_err]: 11:11 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_grcstage_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_grcstage_err_we), - .wd (err_code_sfifo_grcstage_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_grcstage_err.de), @@ -1140,15 +1117,14 @@ // F[sfifo_ggenreq_err]: 12:12 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_ggenreq_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_ggenreq_err_we), - .wd (err_code_sfifo_ggenreq_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_ggenreq_err.de), @@ -1166,15 +1142,14 @@ // F[sfifo_gadstage_err]: 13:13 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_gadstage_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_gadstage_err_we), - .wd (err_code_sfifo_gadstage_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_gadstage_err.de), @@ -1192,15 +1167,14 @@ // F[sfifo_ggenbits_err]: 14:14 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_ggenbits_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_ggenbits_err_we), - .wd (err_code_sfifo_ggenbits_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_ggenbits_err.de), @@ -1218,15 +1192,14 @@ // F[sfifo_blkenc_err]: 15:15 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_sfifo_blkenc_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_sfifo_blkenc_err_we), - .wd (err_code_sfifo_blkenc_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.sfifo_blkenc_err.de), @@ -1241,18 +1214,167 @@ ); + // F[cmd_stage_sm_err]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_err_code_cmd_stage_sm_err ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.err_code.cmd_stage_sm_err.de), + .d (hw2reg.err_code.cmd_stage_sm_err.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (err_code_cmd_stage_sm_err_qs) + ); + + + // F[main_sm_err]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_err_code_main_sm_err ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.err_code.main_sm_err.de), + .d (hw2reg.err_code.main_sm_err.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (err_code_main_sm_err_qs) + ); + + + // F[drbg_gen_sm_err]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_err_code_drbg_gen_sm_err ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.err_code.drbg_gen_sm_err.de), + .d (hw2reg.err_code.drbg_gen_sm_err.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (err_code_drbg_gen_sm_err_qs) + ); + + + // F[drbg_updbe_sm_err]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_err_code_drbg_updbe_sm_err ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.err_code.drbg_updbe_sm_err.de), + .d (hw2reg.err_code.drbg_updbe_sm_err.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (err_code_drbg_updbe_sm_err_qs) + ); + + + // F[drbg_updob_sm_err]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_err_code_drbg_updob_sm_err ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.err_code.drbg_updob_sm_err.de), + .d (hw2reg.err_code.drbg_updob_sm_err.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (err_code_drbg_updob_sm_err_qs) + ); + + + // F[aes_cipher_sm_err]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RO"), + .RESVAL (1'h0) + ) u_err_code_aes_cipher_sm_err ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.err_code.aes_cipher_sm_err.de), + .d (hw2reg.err_code.aes_cipher_sm_err.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (err_code_aes_cipher_sm_err_qs) + ); + + // F[fifo_write_err]: 28:28 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_fifo_write_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_fifo_write_err_we), - .wd (err_code_fifo_write_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.fifo_write_err.de), @@ -1270,15 +1392,14 @@ // F[fifo_read_err]: 29:29 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_fifo_read_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_fifo_read_err_we), - .wd (err_code_fifo_read_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.fifo_read_err.de), @@ -1296,15 +1417,14 @@ // F[fifo_state_err]: 30:30 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("RO"), .RESVAL (1'h0) ) u_err_code_fifo_state_err ( .clk_i (clk_i ), .rst_ni (rst_ni ), - // from register interface - .we (err_code_fifo_state_err_we), - .wd (err_code_fifo_state_err_wd), + .we (1'b0), + .wd ('0 ), // from internal hardware .de (hw2reg.err_code.fifo_state_err.de), @@ -1319,25 +1439,54 @@ ); + // R[err_code_test]: V(False) + + prim_subreg #( + .DW (5), + .SWACCESS("RW"), + .RESVAL (5'h0) + ) u_err_code_test ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (err_code_test_we & regwen_qs), + .wd (err_code_test_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.err_code_test.qe), + .q (reg2hw.err_code_test.q ), + + // to register interface (read) + .qs (err_code_test_qs) + ); - logic [13:0] addr_hit; + + + logic [15:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == CSRNG_INTR_STATE_OFFSET); addr_hit[ 1] = (reg_addr == CSRNG_INTR_ENABLE_OFFSET); addr_hit[ 2] = (reg_addr == CSRNG_INTR_TEST_OFFSET); - addr_hit[ 3] = (reg_addr == CSRNG_REGWEN_OFFSET); - addr_hit[ 4] = (reg_addr == CSRNG_CTRL_OFFSET); - addr_hit[ 5] = (reg_addr == CSRNG_SUM_STS_OFFSET); - addr_hit[ 6] = (reg_addr == CSRNG_CMD_REQ_OFFSET); - addr_hit[ 7] = (reg_addr == CSRNG_SW_CMD_STS_OFFSET); - addr_hit[ 8] = (reg_addr == CSRNG_GENBITS_VLD_OFFSET); - addr_hit[ 9] = (reg_addr == CSRNG_GENBITS_OFFSET); - addr_hit[10] = (reg_addr == CSRNG_INT_STATE_NUM_OFFSET); - addr_hit[11] = (reg_addr == CSRNG_INT_STATE_VAL_OFFSET); - addr_hit[12] = (reg_addr == CSRNG_HW_EXC_STS_OFFSET); - addr_hit[13] = (reg_addr == CSRNG_ERR_CODE_OFFSET); + addr_hit[ 3] = (reg_addr == CSRNG_ALERT_TEST_OFFSET); + addr_hit[ 4] = (reg_addr == CSRNG_REGWEN_OFFSET); + addr_hit[ 5] = (reg_addr == CSRNG_CTRL_OFFSET); + addr_hit[ 6] = (reg_addr == CSRNG_SUM_STS_OFFSET); + addr_hit[ 7] = (reg_addr == CSRNG_CMD_REQ_OFFSET); + addr_hit[ 8] = (reg_addr == CSRNG_SW_CMD_STS_OFFSET); + addr_hit[ 9] = (reg_addr == CSRNG_GENBITS_VLD_OFFSET); + addr_hit[10] = (reg_addr == CSRNG_GENBITS_OFFSET); + addr_hit[11] = (reg_addr == CSRNG_INT_STATE_NUM_OFFSET); + addr_hit[12] = (reg_addr == CSRNG_INT_STATE_VAL_OFFSET); + addr_hit[13] = (reg_addr == CSRNG_HW_EXC_STS_OFFSET); + addr_hit[14] = (reg_addr == CSRNG_ERR_CODE_OFFSET); + addr_hit[15] = (reg_addr == CSRNG_ERR_CODE_TEST_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -1359,6 +1508,8 @@ if (addr_hit[11] && reg_we && (CSRNG_PERMIT[11] != (CSRNG_PERMIT[11] & reg_be))) wr_err = 1'b1 ; if (addr_hit[12] && reg_we && (CSRNG_PERMIT[12] != (CSRNG_PERMIT[12] & reg_be))) wr_err = 1'b1 ; if (addr_hit[13] && reg_we && (CSRNG_PERMIT[13] != (CSRNG_PERMIT[13] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[14] && reg_we && (CSRNG_PERMIT[14] != (CSRNG_PERMIT[14] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[15] && reg_we && (CSRNG_PERMIT[15] != (CSRNG_PERMIT[15] & reg_be))) wr_err = 1'b1 ; end assign intr_state_cs_cmd_req_done_we = addr_hit[0] & reg_we & ~wr_err; @@ -1370,8 +1521,8 @@ assign intr_state_cs_hw_inst_exc_we = addr_hit[0] & reg_we & ~wr_err; assign intr_state_cs_hw_inst_exc_wd = reg_wdata[2]; - assign intr_state_cs_fifo_err_we = addr_hit[0] & reg_we & ~wr_err; - assign intr_state_cs_fifo_err_wd = reg_wdata[3]; + assign intr_state_cs_fatal_err_we = addr_hit[0] & reg_we & ~wr_err; + assign intr_state_cs_fatal_err_wd = reg_wdata[3]; assign intr_enable_cs_cmd_req_done_we = addr_hit[1] & reg_we & ~wr_err; assign intr_enable_cs_cmd_req_done_wd = reg_wdata[0]; @@ -1382,8 +1533,8 @@ assign intr_enable_cs_hw_inst_exc_we = addr_hit[1] & reg_we & ~wr_err; assign intr_enable_cs_hw_inst_exc_wd = reg_wdata[2]; - assign intr_enable_cs_fifo_err_we = addr_hit[1] & reg_we & ~wr_err; - assign intr_enable_cs_fifo_err_wd = reg_wdata[3]; + assign intr_enable_cs_fatal_err_we = addr_hit[1] & reg_we & ~wr_err; + assign intr_enable_cs_fatal_err_wd = reg_wdata[3]; assign intr_test_cs_cmd_req_done_we = addr_hit[2] & reg_we & ~wr_err; assign intr_test_cs_cmd_req_done_wd = reg_wdata[0]; @@ -1394,98 +1545,72 @@ assign intr_test_cs_hw_inst_exc_we = addr_hit[2] & reg_we & ~wr_err; assign intr_test_cs_hw_inst_exc_wd = reg_wdata[2]; - assign intr_test_cs_fifo_err_we = addr_hit[2] & reg_we & ~wr_err; - assign intr_test_cs_fifo_err_wd = reg_wdata[3]; + assign intr_test_cs_fatal_err_we = addr_hit[2] & reg_we & ~wr_err; + assign intr_test_cs_fatal_err_wd = reg_wdata[3]; - assign regwen_we = addr_hit[3] & reg_we & ~wr_err; + assign alert_test_we = addr_hit[3] & reg_we & ~wr_err; + assign alert_test_wd = reg_wdata[0]; + + assign regwen_we = addr_hit[4] & reg_we & ~wr_err; assign regwen_wd = reg_wdata[0]; - assign ctrl_enable_we = addr_hit[4] & reg_we & ~wr_err; + assign ctrl_enable_we = addr_hit[5] & reg_we & ~wr_err; assign ctrl_enable_wd = reg_wdata[0]; - assign ctrl_aes_cipher_disable_we = addr_hit[4] & reg_we & ~wr_err; + assign ctrl_aes_cipher_disable_we = addr_hit[5] & reg_we & ~wr_err; assign ctrl_aes_cipher_disable_wd = reg_wdata[1]; - assign ctrl_fifo_depth_sts_sel_we = addr_hit[4] & reg_we & ~wr_err; + assign ctrl_fifo_depth_sts_sel_we = addr_hit[5] & reg_we & ~wr_err; assign ctrl_fifo_depth_sts_sel_wd = reg_wdata[19:16]; - assign cmd_req_we = addr_hit[6] & reg_we & ~wr_err; + assign cmd_req_we = addr_hit[7] & reg_we & ~wr_err; assign cmd_req_wd = reg_wdata[31:0]; - assign genbits_vld_genbits_vld_re = addr_hit[8] && reg_re; + assign genbits_vld_genbits_vld_re = addr_hit[9] && reg_re; - assign genbits_vld_genbits_fips_re = addr_hit[8] && reg_re; + assign genbits_vld_genbits_fips_re = addr_hit[9] && reg_re; - assign genbits_re = addr_hit[9] && reg_re; + assign genbits_re = addr_hit[10] && reg_re; - assign int_state_num_we = addr_hit[10] & reg_we & ~wr_err; + assign int_state_num_we = addr_hit[11] & reg_we & ~wr_err; assign int_state_num_wd = reg_wdata[3:0]; - assign int_state_val_re = addr_hit[11] && reg_re; + assign int_state_val_re = addr_hit[12] && reg_re; - assign hw_exc_sts_we = addr_hit[12] & reg_we & ~wr_err; + assign hw_exc_sts_we = addr_hit[13] & reg_we & ~wr_err; assign hw_exc_sts_wd = reg_wdata[14:0]; - assign err_code_sfifo_cmd_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_cmd_err_wd = reg_wdata[0]; - assign err_code_sfifo_genbits_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_genbits_err_wd = reg_wdata[1]; - assign err_code_sfifo_cmdreq_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_cmdreq_err_wd = reg_wdata[2]; - assign err_code_sfifo_rcstage_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_rcstage_err_wd = reg_wdata[3]; - assign err_code_sfifo_keyvrc_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_keyvrc_err_wd = reg_wdata[4]; - assign err_code_sfifo_updreq_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_updreq_err_wd = reg_wdata[5]; - assign err_code_sfifo_bencreq_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_bencreq_err_wd = reg_wdata[6]; - assign err_code_sfifo_bencack_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_bencack_err_wd = reg_wdata[7]; - assign err_code_sfifo_pdata_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_pdata_err_wd = reg_wdata[8]; - assign err_code_sfifo_final_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_final_err_wd = reg_wdata[9]; - assign err_code_sfifo_gbencack_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_gbencack_err_wd = reg_wdata[10]; - assign err_code_sfifo_grcstage_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_grcstage_err_wd = reg_wdata[11]; - assign err_code_sfifo_ggenreq_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_ggenreq_err_wd = reg_wdata[12]; - assign err_code_sfifo_gadstage_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_gadstage_err_wd = reg_wdata[13]; - assign err_code_sfifo_ggenbits_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_ggenbits_err_wd = reg_wdata[14]; - assign err_code_sfifo_blkenc_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_sfifo_blkenc_err_wd = reg_wdata[15]; - assign err_code_fifo_write_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_fifo_write_err_wd = reg_wdata[28]; - assign err_code_fifo_read_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_fifo_read_err_wd = reg_wdata[29]; - assign err_code_fifo_state_err_we = addr_hit[13] & reg_we & ~wr_err; - assign err_code_fifo_state_err_wd = reg_wdata[30]; + + + + + + + + assign err_code_test_we = addr_hit[15] & reg_we & ~wr_err; + assign err_code_test_wd = reg_wdata[4:0]; // Read data return always_comb begin @@ -1495,14 +1620,14 @@ reg_rdata_next[0] = intr_state_cs_cmd_req_done_qs; reg_rdata_next[1] = intr_state_cs_entropy_req_qs; reg_rdata_next[2] = intr_state_cs_hw_inst_exc_qs; - reg_rdata_next[3] = intr_state_cs_fifo_err_qs; + reg_rdata_next[3] = intr_state_cs_fatal_err_qs; end addr_hit[1]: begin reg_rdata_next[0] = intr_enable_cs_cmd_req_done_qs; reg_rdata_next[1] = intr_enable_cs_entropy_req_qs; reg_rdata_next[2] = intr_enable_cs_hw_inst_exc_qs; - reg_rdata_next[3] = intr_enable_cs_fifo_err_qs; + reg_rdata_next[3] = intr_enable_cs_fatal_err_qs; end addr_hit[2]: begin @@ -1513,51 +1638,55 @@ end addr_hit[3]: begin - reg_rdata_next[0] = regwen_qs; + reg_rdata_next[0] = '0; end addr_hit[4]: begin + reg_rdata_next[0] = regwen_qs; + end + + addr_hit[5]: begin reg_rdata_next[0] = ctrl_enable_qs; reg_rdata_next[1] = ctrl_aes_cipher_disable_qs; reg_rdata_next[19:16] = ctrl_fifo_depth_sts_sel_qs; end - addr_hit[5]: begin + addr_hit[6]: begin reg_rdata_next[23:0] = sum_sts_fifo_depth_sts_qs; reg_rdata_next[31] = sum_sts_diag_qs; end - addr_hit[6]: begin + addr_hit[7]: begin reg_rdata_next[31:0] = '0; end - addr_hit[7]: begin + addr_hit[8]: begin reg_rdata_next[0] = sw_cmd_sts_cmd_rdy_qs; reg_rdata_next[1] = sw_cmd_sts_cmd_sts_qs; end - addr_hit[8]: begin + addr_hit[9]: begin reg_rdata_next[0] = genbits_vld_genbits_vld_qs; reg_rdata_next[1] = genbits_vld_genbits_fips_qs; end - addr_hit[9]: begin + addr_hit[10]: begin reg_rdata_next[31:0] = genbits_qs; end - addr_hit[10]: begin + addr_hit[11]: begin reg_rdata_next[3:0] = int_state_num_qs; end - addr_hit[11]: begin + addr_hit[12]: begin reg_rdata_next[31:0] = int_state_val_qs; end - addr_hit[12]: begin + addr_hit[13]: begin reg_rdata_next[14:0] = hw_exc_sts_qs; end - addr_hit[13]: begin + addr_hit[14]: begin reg_rdata_next[0] = err_code_sfifo_cmd_err_qs; reg_rdata_next[1] = err_code_sfifo_genbits_err_qs; reg_rdata_next[2] = err_code_sfifo_cmdreq_err_qs; @@ -1574,11 +1703,21 @@ reg_rdata_next[13] = err_code_sfifo_gadstage_err_qs; reg_rdata_next[14] = err_code_sfifo_ggenbits_err_qs; reg_rdata_next[15] = err_code_sfifo_blkenc_err_qs; + reg_rdata_next[20] = err_code_cmd_stage_sm_err_qs; + reg_rdata_next[21] = err_code_main_sm_err_qs; + reg_rdata_next[22] = err_code_drbg_gen_sm_err_qs; + reg_rdata_next[23] = err_code_drbg_updbe_sm_err_qs; + reg_rdata_next[24] = err_code_drbg_updob_sm_err_qs; + reg_rdata_next[25] = err_code_aes_cipher_sm_err_qs; reg_rdata_next[28] = err_code_fifo_write_err_qs; reg_rdata_next[29] = err_code_fifo_read_err_qs; reg_rdata_next[30] = err_code_fifo_state_err_qs; end + addr_hit[15]: begin + reg_rdata_next[4:0] = err_code_test_qs; + end + default: begin reg_rdata_next = '1; end
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 2a85a17..f8a2ee8 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -6107,7 +6107,7 @@ { name: SBoxImpl type: aes_pkg::sbox_impl_e - default: aes_pkg::SBoxImplCanright + default: aes_pkg::SBoxImplLut desc: Selection of the S-Box implementation. See aes_pkg.sv. local: "false" expose: "true" @@ -6155,7 +6155,7 @@ type: interrupt } { - name: cs_fifo_err + name: cs_fatal_err width: 1 bits: "3" bitinfo: @@ -6167,7 +6167,22 @@ type: interrupt } ] - alert_list: [] + alert_list: + [ + { + name: fatal_alert + width: 1 + bits: "0" + bitinfo: + [ + 1 + 1 + 0 + ] + type: alert + async: 1 + } + ] wakeup_list: [] reset_request_list: [] scan: "false" @@ -10805,7 +10820,7 @@ module_name: csrng } { - name: csrng_cs_fifo_err + name: csrng_cs_fatal_err width: 1 bits: "3" bitinfo: @@ -10918,6 +10933,7 @@ otp_ctrl lc_ctrl entropy_src + csrng sram_ctrl_main sram_ctrl_ret_aon flash_ctrl @@ -11177,6 +11193,20 @@ module_name: entropy_src } { + name: csrng_fatal_alert + width: 1 + bits: "0" + bitinfo: + [ + 1 + 1 + 0 + ] + type: alert + async: 1 + module_name: csrng + } + { name: sram_ctrl_main_fatal_parity_error width: 1 bits: "0"
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index a2053f9..f6e444a 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -844,7 +844,8 @@ // list all modules that expose alerts // first item goes to LSB of the alert source alert_module: [ "aes", "otbn", "sensor_ctrl_aon", "keymgr", "otp_ctrl", "lc_ctrl", - "entropy_src", "sram_ctrl_main", "sram_ctrl_ret_aon", "flash_ctrl"] + "entropy_src","csrng", + "sram_ctrl_main", "sram_ctrl_ret_aon", "flash_ctrl"] // generated list of alerts: alert: [
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv index b5f25a7..2ecf2cd 100644 --- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -22,8 +22,9 @@ assign alert_if[15].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0]; assign alert_if[16].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1]; assign alert_if[17].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0]; -assign alert_if[18].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0]; -assign alert_if[19].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0]; -assign alert_if[20].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0]; -assign alert_if[21].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1]; -assign alert_if[22].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2]; +assign alert_if[18].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0]; +assign alert_if[19].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0]; +assign alert_if[20].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0]; +assign alert_if[21].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0]; +assign alert_if[22].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1]; +assign alert_if[23].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
diff --git a/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv index 08608ac..c66641a 100644 --- a/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv
@@ -23,6 +23,7 @@ "lc_ctrl_fatal_prog_error", "lc_ctrl_fatal_state_error", "entropy_src_recov_alert_count_met", + "csrng_fatal_alert", "sram_ctrl_main_fatal_parity_error", "sram_ctrl_ret_aon_fatal_parity_error", "flash_ctrl_recov_err", @@ -30,4 +31,4 @@ "flash_ctrl_recov_ecc_err" }; -parameter uint NUM_ALERTS = 23; +parameter uint NUM_ALERTS = 24;
diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson index 47cf109..7e71e54 100644 --- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson +++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
@@ -46,7 +46,7 @@ { name: "NAlerts", desc: "Number of peripheral inputs", type: "int", - default: "23", + default: "24", local: "true" }, { name: "EscCntDw", @@ -64,7 +64,7 @@ { name: "AsyncOn", desc: "Number of peripheral outputs", type: "logic [NAlerts-1:0]", - default: "23'b11101100001100000001111", + default: "24'b111011100001100000001111", local: "true" }, { name: "N_CLASSES",
diff --git a/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv b/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv index 650489b..2dfb5b7 100644 --- a/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv +++ b/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv
@@ -10,5 +10,5 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -parameter uint NUM_ALERTS = 23; -parameter bit [NUM_ALERTS-1:0] ASYNC_ON = 23'b11101100001100000001111; +parameter uint NUM_ALERTS = 24; +parameter bit [NUM_ALERTS-1:0] ASYNC_ON = 24'b111011100001100000001111;
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv index 0e16ead..292763c 100644 --- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv +++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
@@ -7,10 +7,10 @@ package alert_handler_reg_pkg; // Param list - parameter int NAlerts = 23; + parameter int NAlerts = 24; parameter int EscCntDw = 32; parameter int AccuCntDw = 16; - parameter logic [NAlerts-1:0] AsyncOn = 23'b11101100001100000001111; + parameter logic [NAlerts-1:0] AsyncOn = 24'b111011100001100000001111; parameter int N_CLASSES = 4; parameter int N_ESC_SEV = 4; parameter int N_PHASES = 4; @@ -457,14 +457,14 @@ // Register to internal design logic // /////////////////////////////////////// typedef struct packed { - alert_handler_reg2hw_intr_state_reg_t intr_state; // [916:913] - alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [912:909] - alert_handler_reg2hw_intr_test_reg_t intr_test; // [908:901] - alert_handler_reg2hw_regwen_reg_t regwen; // [900:900] - alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [899:876] - alert_handler_reg2hw_alert_en_mreg_t [22:0] alert_en; // [875:853] - alert_handler_reg2hw_alert_class_mreg_t [22:0] alert_class; // [852:807] - alert_handler_reg2hw_alert_cause_mreg_t [22:0] alert_cause; // [806:784] + alert_handler_reg2hw_intr_state_reg_t intr_state; // [920:917] + alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [916:913] + alert_handler_reg2hw_intr_test_reg_t intr_test; // [912:905] + alert_handler_reg2hw_regwen_reg_t regwen; // [904:904] + alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [903:880] + alert_handler_reg2hw_alert_en_mreg_t [23:0] alert_en; // [879:856] + alert_handler_reg2hw_alert_class_mreg_t [23:0] alert_class; // [855:808] + alert_handler_reg2hw_alert_cause_mreg_t [23:0] alert_cause; // [807:784] alert_handler_reg2hw_loc_alert_en_mreg_t [3:0] loc_alert_en; // [783:780] alert_handler_reg2hw_loc_alert_class_mreg_t [3:0] loc_alert_class; // [779:772] alert_handler_reg2hw_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [771:768] @@ -506,8 +506,8 @@ // Internal design logic to register // /////////////////////////////////////// typedef struct packed { - alert_handler_hw2reg_intr_state_reg_t intr_state; // [273:266] - alert_handler_hw2reg_alert_cause_mreg_t [22:0] alert_cause; // [265:220] + alert_handler_hw2reg_intr_state_reg_t intr_state; // [275:268] + alert_handler_hw2reg_alert_cause_mreg_t [23:0] alert_cause; // [267:220] alert_handler_hw2reg_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [219:212] alert_handler_hw2reg_classa_regwen_reg_t classa_regwen; // [211:210] alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194]
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv index cfb36b7..2826e40 100644 --- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv +++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
@@ -178,6 +178,9 @@ logic alert_en_en_a_22_qs; logic alert_en_en_a_22_wd; logic alert_en_en_a_22_we; + logic alert_en_en_a_23_qs; + logic alert_en_en_a_23_wd; + logic alert_en_en_a_23_we; logic [1:0] alert_class_0_class_a_0_qs; logic [1:0] alert_class_0_class_a_0_wd; logic alert_class_0_class_a_0_we; @@ -247,6 +250,9 @@ logic [1:0] alert_class_1_class_a_22_qs; logic [1:0] alert_class_1_class_a_22_wd; logic alert_class_1_class_a_22_we; + logic [1:0] alert_class_1_class_a_23_qs; + logic [1:0] alert_class_1_class_a_23_wd; + logic alert_class_1_class_a_23_we; logic alert_cause_a_0_qs; logic alert_cause_a_0_wd; logic alert_cause_a_0_we; @@ -316,6 +322,9 @@ logic alert_cause_a_22_qs; logic alert_cause_a_22_wd; logic alert_cause_a_22_we; + logic alert_cause_a_23_qs; + logic alert_cause_a_23_wd; + logic alert_cause_a_23_we; logic loc_alert_en_en_la_0_qs; logic loc_alert_en_en_la_0_wd; logic loc_alert_en_en_la_0_we; @@ -1520,6 +1529,32 @@ ); + // F[en_a_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_alert_en_en_a_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (alert_en_en_a_23_we & regwen_qs), + .wd (alert_en_en_a_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en[23].q ), + + // to register interface (read) + .qs (alert_en_en_a_23_qs) + ); + + // Subregister 0 of Multireg alert_class @@ -2126,6 +2161,32 @@ ); + // F[class_a_23]: 15:14 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_alert_class_1_class_a_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (alert_class_1_class_a_23_we & regwen_qs), + .wd (alert_class_1_class_a_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class[23].q ), + + // to register interface (read) + .qs (alert_class_1_class_a_23_qs) + ); + + // Subregister 0 of Multireg alert_cause @@ -2729,6 +2790,32 @@ ); + // F[a_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_alert_cause_a_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_cause_a_23_we), + .wd (alert_cause_a_23_wd), + + // from internal hardware + .de (hw2reg.alert_cause[23].de), + .d (hw2reg.alert_cause[23].d ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[23].q ), + + // to register interface (read) + .qs (alert_cause_a_23_qs) + ); + + // Subregister 0 of Multireg loc_alert_en @@ -5402,6 +5489,9 @@ assign alert_en_en_a_22_we = addr_hit[5] & reg_we & ~wr_err; assign alert_en_en_a_22_wd = reg_wdata[22]; + assign alert_en_en_a_23_we = addr_hit[5] & reg_we & ~wr_err; + assign alert_en_en_a_23_wd = reg_wdata[23]; + assign alert_class_0_class_a_0_we = addr_hit[6] & reg_we & ~wr_err; assign alert_class_0_class_a_0_wd = reg_wdata[1:0]; @@ -5471,6 +5561,9 @@ assign alert_class_1_class_a_22_we = addr_hit[7] & reg_we & ~wr_err; assign alert_class_1_class_a_22_wd = reg_wdata[13:12]; + assign alert_class_1_class_a_23_we = addr_hit[7] & reg_we & ~wr_err; + assign alert_class_1_class_a_23_wd = reg_wdata[15:14]; + assign alert_cause_a_0_we = addr_hit[8] & reg_we & ~wr_err; assign alert_cause_a_0_wd = reg_wdata[0]; @@ -5540,6 +5633,9 @@ assign alert_cause_a_22_we = addr_hit[8] & reg_we & ~wr_err; assign alert_cause_a_22_wd = reg_wdata[22]; + assign alert_cause_a_23_we = addr_hit[8] & reg_we & ~wr_err; + assign alert_cause_a_23_wd = reg_wdata[23]; + assign loc_alert_en_en_la_0_we = addr_hit[9] & reg_we & ~wr_err; assign loc_alert_en_en_la_0_wd = reg_wdata[0]; @@ -5873,6 +5969,7 @@ reg_rdata_next[20] = alert_en_en_a_20_qs; reg_rdata_next[21] = alert_en_en_a_21_qs; reg_rdata_next[22] = alert_en_en_a_22_qs; + reg_rdata_next[23] = alert_en_en_a_23_qs; end addr_hit[6]: begin @@ -5902,6 +5999,7 @@ reg_rdata_next[9:8] = alert_class_1_class_a_20_qs; reg_rdata_next[11:10] = alert_class_1_class_a_21_qs; reg_rdata_next[13:12] = alert_class_1_class_a_22_qs; + reg_rdata_next[15:14] = alert_class_1_class_a_23_qs; end addr_hit[8]: begin @@ -5928,6 +6026,7 @@ reg_rdata_next[20] = alert_cause_a_20_qs; reg_rdata_next[21] = alert_cause_a_21_qs; reg_rdata_next[22] = alert_cause_a_22_qs; + reg_rdata_next[23] = alert_cause_a_23_qs; end addr_hit[9]: begin
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 31206e5..692a88d 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -18,7 +18,7 @@ parameter bit SecAesAllowForcingMasks = 1'b0, parameter bit KmacEnMasking = 0, parameter int KmacReuseShare = 0, - parameter aes_pkg::sbox_impl_e CsrngSBoxImpl = aes_pkg::SBoxImplCanright, + parameter aes_pkg::sbox_impl_e CsrngSBoxImpl = aes_pkg::SBoxImplLut, parameter otbn_pkg::regfile_e OtbnRegFile = otbn_pkg::RegFileFF, // Manually defined parameters @@ -350,7 +350,7 @@ logic intr_csrng_cs_cmd_req_done; logic intr_csrng_cs_entropy_req; logic intr_csrng_cs_hw_inst_exc; - logic intr_csrng_cs_fifo_err; + logic intr_csrng_cs_fatal_err; logic intr_entropy_src_es_entropy_valid; logic intr_entropy_src_es_health_test_failed; logic intr_entropy_src_es_fifo_err; @@ -1821,7 +1821,11 @@ .intr_cs_cmd_req_done_o (intr_csrng_cs_cmd_req_done), .intr_cs_entropy_req_o (intr_csrng_cs_entropy_req), .intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc), - .intr_cs_fifo_err_o (intr_csrng_cs_fifo_err), + .intr_cs_fatal_err_o (intr_csrng_cs_fatal_err), + + // [19]: fatal_alert + .alert_tx_o ( alert_tx[19:19] ), + .alert_rx_i ( alert_rx[19:19] ), // Inter-module signals .csrng_cmd_i(csrng_csrng_cmd_req), @@ -1845,9 +1849,9 @@ .intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed), .intr_es_fifo_err_o (intr_entropy_src_es_fifo_err), - // [19]: recov_alert_count_met - .alert_tx_o ( alert_tx[19:19] ), - .alert_rx_i ( alert_rx[19:19] ), + // [20]: recov_alert_count_met + .alert_tx_o ( alert_tx[20:20] ), + .alert_rx_i ( alert_rx[20:20] ), // Inter-module signals .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req), @@ -1908,9 +1912,9 @@ .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce) ) u_sram_ctrl_main ( - // [20]: fatal_parity_error - .alert_tx_o ( alert_tx[20:20] ), - .alert_rx_i ( alert_rx[20:20] ), + // [21]: fatal_parity_error + .alert_tx_o ( alert_tx[21:21] ), + .alert_rx_i ( alert_rx[21:21] ), // Inter-module signals .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]), @@ -1935,10 +1939,10 @@ // Interrupt .intr_done_o (intr_otbn_done), - // [21]: fatal - // [22]: recov - .alert_tx_o ( alert_tx[22:21] ), - .alert_rx_i ( alert_rx[22:21] ), + // [22]: fatal + // [23]: recov + .alert_tx_o ( alert_tx[23:22] ), + .alert_rx_i ( alert_rx[23:22] ), // Inter-module signals .idle_o(clkmgr_aon_idle[3]), @@ -1959,7 +1963,7 @@ intr_edn1_edn_cmd_req_done, intr_edn0_edn_fifo_err, intr_edn0_edn_cmd_req_done, - intr_csrng_cs_fifo_err, + intr_csrng_cs_fatal_err, intr_csrng_cs_hw_inst_exc, intr_csrng_cs_entropy_req, intr_csrng_cs_cmd_req_done,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c index ac78378..d26536a 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -176,7 +176,7 @@ [kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone] = kTopEarlgreyPlicPeripheralCsrng, [kTopEarlgreyPlicIrqIdCsrngCsEntropyReq] = kTopEarlgreyPlicPeripheralCsrng, [kTopEarlgreyPlicIrqIdCsrngCsHwInstExc] = kTopEarlgreyPlicPeripheralCsrng, - [kTopEarlgreyPlicIrqIdCsrngCsFifoErr] = kTopEarlgreyPlicPeripheralCsrng, + [kTopEarlgreyPlicIrqIdCsrngCsFatalErr] = kTopEarlgreyPlicPeripheralCsrng, [kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone] = kTopEarlgreyPlicPeripheralEdn0, [kTopEarlgreyPlicIrqIdEdn0EdnFifoErr] = kTopEarlgreyPlicPeripheralEdn0, [kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone] = kTopEarlgreyPlicPeripheralEdn1, @@ -194,7 +194,7 @@ * `top_earlgrey_alert_peripheral_t`. */ const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[23] = { + top_earlgrey_alert_for_peripheral[24] = { [kTopEarlgreyAlertIdAesRecovCtrlUpdateErr] = kTopEarlgreyAlertPeripheralAes, [kTopEarlgreyAlertIdAesFatalFault] = kTopEarlgreyAlertPeripheralAes, [kTopEarlgreyAlertIdOtbnFatal] = kTopEarlgreyAlertPeripheralOtbn, @@ -213,6 +213,7 @@ [kTopEarlgreyAlertIdLcCtrlFatalProgError] = kTopEarlgreyAlertPeripheralLcCtrl, [kTopEarlgreyAlertIdLcCtrlFatalStateError] = kTopEarlgreyAlertPeripheralLcCtrl, [kTopEarlgreyAlertIdEntropySrcRecovAlertCountMet] = kTopEarlgreyAlertPeripheralEntropySrc, + [kTopEarlgreyAlertIdCsrngFatalAlert] = kTopEarlgreyAlertPeripheralCsrng, [kTopEarlgreyAlertIdSramCtrlMainFatalParityError] = kTopEarlgreyAlertPeripheralSramCtrlMain, [kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError] = kTopEarlgreyAlertPeripheralSramCtrlRetAon, [kTopEarlgreyAlertIdFlashCtrlRecovErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index 6288447..3b14bcc 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -903,7 +903,7 @@ kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 161, /**< csrng_cs_cmd_req_done */ kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 162, /**< csrng_cs_entropy_req */ kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 163, /**< csrng_cs_hw_inst_exc */ - kTopEarlgreyPlicIrqIdCsrngCsFifoErr = 164, /**< csrng_cs_fifo_err */ + kTopEarlgreyPlicIrqIdCsrngCsFatalErr = 164, /**< csrng_cs_fatal_err */ kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 165, /**< edn0_edn_cmd_req_done */ kTopEarlgreyPlicIrqIdEdn0EdnFifoErr = 166, /**< edn0_edn_fifo_err */ kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 167, /**< edn1_edn_cmd_req_done */ @@ -948,10 +948,11 @@ kTopEarlgreyAlertPeripheralOtpCtrl = 4, /**< otp_ctrl */ kTopEarlgreyAlertPeripheralLcCtrl = 5, /**< lc_ctrl */ kTopEarlgreyAlertPeripheralEntropySrc = 6, /**< entropy_src */ - kTopEarlgreyAlertPeripheralSramCtrlMain = 7, /**< sram_ctrl_main */ - kTopEarlgreyAlertPeripheralSramCtrlRetAon = 8, /**< sram_ctrl_ret_aon */ - kTopEarlgreyAlertPeripheralFlashCtrl = 9, /**< flash_ctrl */ - kTopEarlgreyAlertPeripheralLast = 9, /**< \internal Final Alert peripheral */ + kTopEarlgreyAlertPeripheralCsrng = 7, /**< csrng */ + kTopEarlgreyAlertPeripheralSramCtrlMain = 8, /**< sram_ctrl_main */ + kTopEarlgreyAlertPeripheralSramCtrlRetAon = 9, /**< sram_ctrl_ret_aon */ + kTopEarlgreyAlertPeripheralFlashCtrl = 10, /**< flash_ctrl */ + kTopEarlgreyAlertPeripheralLast = 10, /**< \internal Final Alert peripheral */ } top_earlgrey_alert_peripheral_t; /** @@ -979,12 +980,13 @@ kTopEarlgreyAlertIdLcCtrlFatalProgError = 15, /**< lc_ctrl_fatal_prog_error */ kTopEarlgreyAlertIdLcCtrlFatalStateError = 16, /**< lc_ctrl_fatal_state_error */ kTopEarlgreyAlertIdEntropySrcRecovAlertCountMet = 17, /**< entropy_src_recov_alert_count_met */ - kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 18, /**< sram_ctrl_main_fatal_parity_error */ - kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 19, /**< sram_ctrl_ret_aon_fatal_parity_error */ - kTopEarlgreyAlertIdFlashCtrlRecovErr = 20, /**< flash_ctrl_recov_err */ - kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 21, /**< flash_ctrl_recov_mp_err */ - kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 22, /**< flash_ctrl_recov_ecc_err */ - kTopEarlgreyAlertIdLast = 22, /**< \internal The Last Valid Alert ID. */ + kTopEarlgreyAlertIdCsrngFatalAlert = 18, /**< csrng_fatal_alert */ + kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 19, /**< sram_ctrl_main_fatal_parity_error */ + kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 20, /**< sram_ctrl_ret_aon_fatal_parity_error */ + kTopEarlgreyAlertIdFlashCtrlRecovErr = 21, /**< flash_ctrl_recov_err */ + kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 22, /**< flash_ctrl_recov_mp_err */ + kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 23, /**< flash_ctrl_recov_ecc_err */ + kTopEarlgreyAlertIdLast = 23, /**< \internal The Last Valid Alert ID. */ } top_earlgrey_alert_id_t; /** @@ -994,7 +996,7 @@ * `top_earlgrey_alert_peripheral_t`. */ extern const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[23]; + top_earlgrey_alert_for_peripheral[24]; #define PINMUX_PERIPH_INSEL_IDX_OFFSET 2