[top_earlgrey] Add AES unit to top-level
diff --git a/hw/top_earlgrey/doc/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/doc/autogen/top_earlgrey.gen.hjson index 45cc848..100de00 100644 --- a/hw/top_earlgrey/doc/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/doc/autogen/top_earlgrey.gen.hjson
@@ -309,6 +309,27 @@ scan: "false" } { + name: aes + type: aes + clock_connections: + { + clk_i: main + } + reset_connections: + { + rst_ni: sys + } + base_addr: 0x40110000 + size: 0x1000 + bus_device: tlul + bus_host: none + available_input_list: [] + available_output_list: [] + available_inout_list: [] + interrupt_list: [] + scan: "false" + } + { name: hmac type: hmac clock_connections: @@ -451,6 +472,7 @@ spi_device flash_ctrl rv_timer + aes hmac rv_plic ] @@ -464,6 +486,7 @@ spi_device flash_ctrl rv_timer + aes hmac rv_plic ] @@ -595,6 +618,16 @@ pipeline: "true" } { + name: aes + type: device + clock: main + pipeline_byp: "false" + inst_type: aes + base_addr: 0x40110000 + size_byte: 0x1000 + pipeline: "true" + } + { name: rv_plic type: device clock: main
diff --git a/hw/top_earlgrey/doc/top_earlgrey.hjson b/hw/top_earlgrey/doc/top_earlgrey.hjson index c19ce8e..e7ac8df 100644 --- a/hw/top_earlgrey/doc/top_earlgrey.hjson +++ b/hw/top_earlgrey/doc/top_earlgrey.hjson
@@ -71,6 +71,12 @@ reset_connections: {rst_ni: "sys"}, base_addr: "0x40080000", }, + { name: "aes", + type: "aes", + clock_connections: {clk_i: "main"}, + reset_connections: {rst_ni: "sys"}, + base_addr: "0x40110000", + }, { name: "hmac", type: "hmac", clock_connections: {clk_i: "main"},
diff --git a/hw/top_earlgrey/doc/xbar_main.hjson b/hw/top_earlgrey/doc/xbar_main.hjson index 64c8a6b..b4ac39a 100644 --- a/hw/top_earlgrey/doc/xbar_main.hjson +++ b/hw/top_earlgrey/doc/xbar_main.hjson
@@ -76,6 +76,11 @@ clock: "main" pipeline_byp: "false" }, + { name: "aes", + type: "device", + clock: "main" + pipeline_byp: "false" + }, { name: "rv_plic", type: "device", clock: "main", @@ -87,7 +92,7 @@ ], connections: { corei: ["rom", "debug_mem", "ram_main", "eflash"], - cored: ["rom", "debug_mem", "ram_main", "eflash", "uart", "gpio", "spi_device", "flash_ctrl", "rv_timer", "hmac", "rv_plic"], - dm_sba: ["rom", "ram_main", "eflash", "uart", "gpio", "spi_device", "flash_ctrl", "rv_timer", "hmac", "rv_plic"], + cored: ["rom", "debug_mem", "ram_main", "eflash", "uart", "gpio", "spi_device", "flash_ctrl", "rv_timer", "aes", "hmac", "rv_plic"], + dm_sba: ["rom", "ram_main", "eflash", "uart", "gpio", "spi_device", "flash_ctrl", "rv_timer", "aes", "hmac", "rv_plic"], }, }
diff --git a/hw/top_earlgrey/ip/xbar/doc/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar/doc/autogen/xbar_main.gen.hjson index 955fe76..3538267 100644 --- a/hw/top_earlgrey/ip/xbar/doc/autogen/xbar_main.gen.hjson +++ b/hw/top_earlgrey/ip/xbar/doc/autogen/xbar_main.gen.hjson
@@ -37,6 +37,7 @@ spi_device flash_ctrl rv_timer + aes hmac rv_plic ] @@ -50,6 +51,7 @@ spi_device flash_ctrl rv_timer + aes hmac rv_plic ] @@ -181,6 +183,16 @@ pipeline: "true" } { + name: aes + type: device + clock: main + pipeline_byp: "false" + inst_type: aes + base_addr: 0x40110000 + size_byte: 0x1000 + pipeline: "true" + } + { name: rv_plic type: device clock: main
diff --git a/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv b/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv index e3dc26b..42a772b 100644 --- a/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv +++ b/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv
@@ -86,6 +86,12 @@ .h2d (tl_hmac_o), .d2h (tl_hmac_i) ); + bind xbar_main tlul_assert tlul_assert_device_aes ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_aes_o), + .d2h (tl_aes_i) + ); bind xbar_main tlul_assert tlul_assert_device_rv_plic ( .clk_i (clk_main_i), .rst_ni (rst_main_ni),
diff --git a/hw/top_earlgrey/ip/xbar/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar/rtl/autogen/tl_main_pkg.sv index 1784335..06205c1 100644 --- a/hw/top_earlgrey/ip/xbar/rtl/autogen/tl_main_pkg.sv +++ b/hw/top_earlgrey/ip/xbar/rtl/autogen/tl_main_pkg.sv
@@ -16,6 +16,7 @@ localparam logic [31:0] ADDR_SPACE_FLASH_CTRL = 32'h 40030000; localparam logic [31:0] ADDR_SPACE_RV_TIMER = 32'h 40080000; localparam logic [31:0] ADDR_SPACE_HMAC = 32'h 40120000; + localparam logic [31:0] ADDR_SPACE_AES = 32'h 40110000; localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 40090000; localparam logic [31:0] ADDR_MASK_ROM = 32'h 00001fff; @@ -28,10 +29,11 @@ localparam logic [31:0] ADDR_MASK_FLASH_CTRL = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_RV_TIMER = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_HMAC = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_AES = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_RV_PLIC = 32'h 00000fff; localparam int N_HOST = 3; - localparam int N_DEVICE = 11; + localparam int N_DEVICE = 12; typedef enum int { TlRom = 0, @@ -44,7 +46,8 @@ TlFlashCtrl = 7, TlRvTimer = 8, TlHmac = 9, - TlRvPlic = 10 + TlAes = 10, + TlRvPlic = 11 } tl_device_e; typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv index 5287824..2ccd8ab 100644 --- a/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv +++ b/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv
@@ -7,60 +7,64 @@ // // Interconnect // corei -// -> s1n_14 -// -> sm1_15 -// -> rom +// -> s1n_15 // -> sm1_16 -// -> debug_mem +// -> rom // -> sm1_17 -// -> ram_main +// -> debug_mem // -> sm1_18 +// -> ram_main +// -> sm1_19 // -> eflash // cored -// -> s1n_19 -// -> sm1_15 -// -> rom +// -> s1n_20 // -> sm1_16 -// -> debug_mem +// -> rom // -> sm1_17 -// -> ram_main +// -> debug_mem // -> sm1_18 +// -> ram_main +// -> sm1_19 // -> eflash -// -> sm1_20 -// -> uart // -> sm1_21 -// -> gpio +// -> uart // -> sm1_22 -// -> spi_device +// -> gpio // -> sm1_23 -// -> flash_ctrl +// -> spi_device // -> sm1_24 -// -> rv_timer +// -> flash_ctrl // -> sm1_25 -// -> hmac +// -> rv_timer // -> sm1_26 +// -> aes +// -> sm1_27 +// -> hmac +// -> sm1_28 // -> rv_plic // dm_sba -// -> s1n_27 -// -> sm1_15 +// -> s1n_29 +// -> sm1_16 // -> rom -// -> sm1_17 -// -> ram_main // -> sm1_18 +// -> ram_main +// -> sm1_19 // -> eflash -// -> sm1_20 -// -> uart // -> sm1_21 -// -> gpio +// -> uart // -> sm1_22 -// -> spi_device +// -> gpio // -> sm1_23 -// -> flash_ctrl +// -> spi_device // -> sm1_24 -// -> rv_timer +// -> flash_ctrl // -> sm1_25 -// -> hmac +// -> rv_timer // -> sm1_26 +// -> aes +// -> sm1_27 +// -> hmac +// -> sm1_28 // -> rv_plic module xbar_main ( @@ -96,6 +100,8 @@ input tlul_pkg::tl_d2h_t tl_rv_timer_i, output tlul_pkg::tl_h2d_t tl_hmac_o, input tlul_pkg::tl_d2h_t tl_hmac_i, + output tlul_pkg::tl_h2d_t tl_aes_o, + input tlul_pkg::tl_d2h_t tl_aes_i, output tlul_pkg::tl_h2d_t tl_rv_plic_o, input tlul_pkg::tl_d2h_t tl_rv_plic_i, @@ -105,33 +111,26 @@ import tlul_pkg::*; import tl_main_pkg::*; - tl_h2d_t tl_s1n_14_us_h2d ; - tl_d2h_t tl_s1n_14_us_d2h ; + tl_h2d_t tl_s1n_15_us_h2d ; + tl_d2h_t tl_s1n_15_us_d2h ; - tl_h2d_t tl_s1n_14_ds_h2d [4]; - tl_d2h_t tl_s1n_14_ds_d2h [4]; + tl_h2d_t tl_s1n_15_ds_h2d [4]; + tl_d2h_t tl_s1n_15_ds_d2h [4]; // Create steering signal - logic [2:0] dev_sel_s1n_14; + logic [2:0] dev_sel_s1n_15; - tl_h2d_t tl_sm1_15_us_h2d [3]; - tl_d2h_t tl_sm1_15_us_d2h [3]; - - tl_h2d_t tl_sm1_15_ds_h2d ; - tl_d2h_t tl_sm1_15_ds_d2h ; - - - tl_h2d_t tl_sm1_16_us_h2d [2]; - tl_d2h_t tl_sm1_16_us_d2h [2]; + tl_h2d_t tl_sm1_16_us_h2d [3]; + tl_d2h_t tl_sm1_16_us_d2h [3]; tl_h2d_t tl_sm1_16_ds_h2d ; tl_d2h_t tl_sm1_16_ds_d2h ; - tl_h2d_t tl_sm1_17_us_h2d [3]; - tl_d2h_t tl_sm1_17_us_d2h [3]; + tl_h2d_t tl_sm1_17_us_h2d [2]; + tl_d2h_t tl_sm1_17_us_d2h [2]; tl_h2d_t tl_sm1_17_ds_h2d ; tl_d2h_t tl_sm1_17_ds_d2h ; @@ -143,22 +142,22 @@ tl_h2d_t tl_sm1_18_ds_h2d ; tl_d2h_t tl_sm1_18_ds_d2h ; - tl_h2d_t tl_s1n_19_us_h2d ; - tl_d2h_t tl_s1n_19_us_d2h ; + + tl_h2d_t tl_sm1_19_us_h2d [3]; + tl_d2h_t tl_sm1_19_us_d2h [3]; + + tl_h2d_t tl_sm1_19_ds_h2d ; + tl_d2h_t tl_sm1_19_ds_d2h ; + + tl_h2d_t tl_s1n_20_us_h2d ; + tl_d2h_t tl_s1n_20_us_d2h ; - tl_h2d_t tl_s1n_19_ds_h2d [11]; - tl_d2h_t tl_s1n_19_ds_d2h [11]; + tl_h2d_t tl_s1n_20_ds_h2d [12]; + tl_d2h_t tl_s1n_20_ds_d2h [12]; // Create steering signal - logic [3:0] dev_sel_s1n_19; - - - tl_h2d_t tl_sm1_20_us_h2d [2]; - tl_d2h_t tl_sm1_20_us_d2h [2]; - - tl_h2d_t tl_sm1_20_ds_h2d ; - tl_d2h_t tl_sm1_20_ds_d2h ; + logic [3:0] dev_sel_s1n_20; tl_h2d_t tl_sm1_21_us_h2d [2]; @@ -202,200 +201,227 @@ tl_h2d_t tl_sm1_26_ds_h2d ; tl_d2h_t tl_sm1_26_ds_d2h ; - tl_h2d_t tl_s1n_27_us_h2d ; - tl_d2h_t tl_s1n_27_us_d2h ; + + tl_h2d_t tl_sm1_27_us_h2d [2]; + tl_d2h_t tl_sm1_27_us_d2h [2]; + + tl_h2d_t tl_sm1_27_ds_h2d ; + tl_d2h_t tl_sm1_27_ds_d2h ; - tl_h2d_t tl_s1n_27_ds_h2d [10]; - tl_d2h_t tl_s1n_27_ds_d2h [10]; + tl_h2d_t tl_sm1_28_us_h2d [2]; + tl_d2h_t tl_sm1_28_us_d2h [2]; + + tl_h2d_t tl_sm1_28_ds_h2d ; + tl_d2h_t tl_sm1_28_ds_d2h ; + + tl_h2d_t tl_s1n_29_us_h2d ; + tl_d2h_t tl_s1n_29_us_d2h ; + + + tl_h2d_t tl_s1n_29_ds_h2d [11]; + tl_d2h_t tl_s1n_29_ds_d2h [11]; // Create steering signal - logic [3:0] dev_sel_s1n_27; + logic [3:0] dev_sel_s1n_29; - assign tl_sm1_15_us_h2d[0] = tl_s1n_14_ds_h2d[0]; - assign tl_s1n_14_ds_d2h[0] = tl_sm1_15_us_d2h[0]; + assign tl_sm1_16_us_h2d[0] = tl_s1n_15_ds_h2d[0]; + assign tl_s1n_15_ds_d2h[0] = tl_sm1_16_us_d2h[0]; - assign tl_sm1_16_us_h2d[0] = tl_s1n_14_ds_h2d[1]; - assign tl_s1n_14_ds_d2h[1] = tl_sm1_16_us_d2h[0]; + assign tl_sm1_17_us_h2d[0] = tl_s1n_15_ds_h2d[1]; + assign tl_s1n_15_ds_d2h[1] = tl_sm1_17_us_d2h[0]; - assign tl_sm1_17_us_h2d[0] = tl_s1n_14_ds_h2d[2]; - assign tl_s1n_14_ds_d2h[2] = tl_sm1_17_us_d2h[0]; + assign tl_sm1_18_us_h2d[0] = tl_s1n_15_ds_h2d[2]; + assign tl_s1n_15_ds_d2h[2] = tl_sm1_18_us_d2h[0]; - assign tl_sm1_18_us_h2d[0] = tl_s1n_14_ds_h2d[3]; - assign tl_s1n_14_ds_d2h[3] = tl_sm1_18_us_d2h[0]; + assign tl_sm1_19_us_h2d[0] = tl_s1n_15_ds_h2d[3]; + assign tl_s1n_15_ds_d2h[3] = tl_sm1_19_us_d2h[0]; - assign tl_sm1_15_us_h2d[1] = tl_s1n_19_ds_h2d[0]; - assign tl_s1n_19_ds_d2h[0] = tl_sm1_15_us_d2h[1]; + assign tl_sm1_16_us_h2d[1] = tl_s1n_20_ds_h2d[0]; + assign tl_s1n_20_ds_d2h[0] = tl_sm1_16_us_d2h[1]; - assign tl_sm1_16_us_h2d[1] = tl_s1n_19_ds_h2d[1]; - assign tl_s1n_19_ds_d2h[1] = tl_sm1_16_us_d2h[1]; + assign tl_sm1_17_us_h2d[1] = tl_s1n_20_ds_h2d[1]; + assign tl_s1n_20_ds_d2h[1] = tl_sm1_17_us_d2h[1]; - assign tl_sm1_17_us_h2d[1] = tl_s1n_19_ds_h2d[2]; - assign tl_s1n_19_ds_d2h[2] = tl_sm1_17_us_d2h[1]; + assign tl_sm1_18_us_h2d[1] = tl_s1n_20_ds_h2d[2]; + assign tl_s1n_20_ds_d2h[2] = tl_sm1_18_us_d2h[1]; - assign tl_sm1_18_us_h2d[1] = tl_s1n_19_ds_h2d[3]; - assign tl_s1n_19_ds_d2h[3] = tl_sm1_18_us_d2h[1]; + assign tl_sm1_19_us_h2d[1] = tl_s1n_20_ds_h2d[3]; + assign tl_s1n_20_ds_d2h[3] = tl_sm1_19_us_d2h[1]; - assign tl_sm1_20_us_h2d[0] = tl_s1n_19_ds_h2d[4]; - assign tl_s1n_19_ds_d2h[4] = tl_sm1_20_us_d2h[0]; + assign tl_sm1_21_us_h2d[0] = tl_s1n_20_ds_h2d[4]; + assign tl_s1n_20_ds_d2h[4] = tl_sm1_21_us_d2h[0]; - assign tl_sm1_21_us_h2d[0] = tl_s1n_19_ds_h2d[5]; - assign tl_s1n_19_ds_d2h[5] = tl_sm1_21_us_d2h[0]; + assign tl_sm1_22_us_h2d[0] = tl_s1n_20_ds_h2d[5]; + assign tl_s1n_20_ds_d2h[5] = tl_sm1_22_us_d2h[0]; - assign tl_sm1_22_us_h2d[0] = tl_s1n_19_ds_h2d[6]; - assign tl_s1n_19_ds_d2h[6] = tl_sm1_22_us_d2h[0]; + assign tl_sm1_23_us_h2d[0] = tl_s1n_20_ds_h2d[6]; + assign tl_s1n_20_ds_d2h[6] = tl_sm1_23_us_d2h[0]; - assign tl_sm1_23_us_h2d[0] = tl_s1n_19_ds_h2d[7]; - assign tl_s1n_19_ds_d2h[7] = tl_sm1_23_us_d2h[0]; + assign tl_sm1_24_us_h2d[0] = tl_s1n_20_ds_h2d[7]; + assign tl_s1n_20_ds_d2h[7] = tl_sm1_24_us_d2h[0]; - assign tl_sm1_24_us_h2d[0] = tl_s1n_19_ds_h2d[8]; - assign tl_s1n_19_ds_d2h[8] = tl_sm1_24_us_d2h[0]; + assign tl_sm1_25_us_h2d[0] = tl_s1n_20_ds_h2d[8]; + assign tl_s1n_20_ds_d2h[8] = tl_sm1_25_us_d2h[0]; - assign tl_sm1_25_us_h2d[0] = tl_s1n_19_ds_h2d[9]; - assign tl_s1n_19_ds_d2h[9] = tl_sm1_25_us_d2h[0]; + assign tl_sm1_26_us_h2d[0] = tl_s1n_20_ds_h2d[9]; + assign tl_s1n_20_ds_d2h[9] = tl_sm1_26_us_d2h[0]; - assign tl_sm1_26_us_h2d[0] = tl_s1n_19_ds_h2d[10]; - assign tl_s1n_19_ds_d2h[10] = tl_sm1_26_us_d2h[0]; + assign tl_sm1_27_us_h2d[0] = tl_s1n_20_ds_h2d[10]; + assign tl_s1n_20_ds_d2h[10] = tl_sm1_27_us_d2h[0]; - assign tl_sm1_15_us_h2d[2] = tl_s1n_27_ds_h2d[0]; - assign tl_s1n_27_ds_d2h[0] = tl_sm1_15_us_d2h[2]; + assign tl_sm1_28_us_h2d[0] = tl_s1n_20_ds_h2d[11]; + assign tl_s1n_20_ds_d2h[11] = tl_sm1_28_us_d2h[0]; - assign tl_sm1_17_us_h2d[2] = tl_s1n_27_ds_h2d[1]; - assign tl_s1n_27_ds_d2h[1] = tl_sm1_17_us_d2h[2]; + assign tl_sm1_16_us_h2d[2] = tl_s1n_29_ds_h2d[0]; + assign tl_s1n_29_ds_d2h[0] = tl_sm1_16_us_d2h[2]; - assign tl_sm1_18_us_h2d[2] = tl_s1n_27_ds_h2d[2]; - assign tl_s1n_27_ds_d2h[2] = tl_sm1_18_us_d2h[2]; + assign tl_sm1_18_us_h2d[2] = tl_s1n_29_ds_h2d[1]; + assign tl_s1n_29_ds_d2h[1] = tl_sm1_18_us_d2h[2]; - assign tl_sm1_20_us_h2d[1] = tl_s1n_27_ds_h2d[3]; - assign tl_s1n_27_ds_d2h[3] = tl_sm1_20_us_d2h[1]; + assign tl_sm1_19_us_h2d[2] = tl_s1n_29_ds_h2d[2]; + assign tl_s1n_29_ds_d2h[2] = tl_sm1_19_us_d2h[2]; - assign tl_sm1_21_us_h2d[1] = tl_s1n_27_ds_h2d[4]; - assign tl_s1n_27_ds_d2h[4] = tl_sm1_21_us_d2h[1]; + assign tl_sm1_21_us_h2d[1] = tl_s1n_29_ds_h2d[3]; + assign tl_s1n_29_ds_d2h[3] = tl_sm1_21_us_d2h[1]; - assign tl_sm1_22_us_h2d[1] = tl_s1n_27_ds_h2d[5]; - assign tl_s1n_27_ds_d2h[5] = tl_sm1_22_us_d2h[1]; + assign tl_sm1_22_us_h2d[1] = tl_s1n_29_ds_h2d[4]; + assign tl_s1n_29_ds_d2h[4] = tl_sm1_22_us_d2h[1]; - assign tl_sm1_23_us_h2d[1] = tl_s1n_27_ds_h2d[6]; - assign tl_s1n_27_ds_d2h[6] = tl_sm1_23_us_d2h[1]; + assign tl_sm1_23_us_h2d[1] = tl_s1n_29_ds_h2d[5]; + assign tl_s1n_29_ds_d2h[5] = tl_sm1_23_us_d2h[1]; - assign tl_sm1_24_us_h2d[1] = tl_s1n_27_ds_h2d[7]; - assign tl_s1n_27_ds_d2h[7] = tl_sm1_24_us_d2h[1]; + assign tl_sm1_24_us_h2d[1] = tl_s1n_29_ds_h2d[6]; + assign tl_s1n_29_ds_d2h[6] = tl_sm1_24_us_d2h[1]; - assign tl_sm1_25_us_h2d[1] = tl_s1n_27_ds_h2d[8]; - assign tl_s1n_27_ds_d2h[8] = tl_sm1_25_us_d2h[1]; + assign tl_sm1_25_us_h2d[1] = tl_s1n_29_ds_h2d[7]; + assign tl_s1n_29_ds_d2h[7] = tl_sm1_25_us_d2h[1]; - assign tl_sm1_26_us_h2d[1] = tl_s1n_27_ds_h2d[9]; - assign tl_s1n_27_ds_d2h[9] = tl_sm1_26_us_d2h[1]; + assign tl_sm1_26_us_h2d[1] = tl_s1n_29_ds_h2d[8]; + assign tl_s1n_29_ds_d2h[8] = tl_sm1_26_us_d2h[1]; - assign tl_s1n_14_us_h2d = tl_corei_i; - assign tl_corei_o = tl_s1n_14_us_d2h; + assign tl_sm1_27_us_h2d[1] = tl_s1n_29_ds_h2d[9]; + assign tl_s1n_29_ds_d2h[9] = tl_sm1_27_us_d2h[1]; - assign tl_rom_o = tl_sm1_15_ds_h2d; - assign tl_sm1_15_ds_d2h = tl_rom_i; + assign tl_sm1_28_us_h2d[1] = tl_s1n_29_ds_h2d[10]; + assign tl_s1n_29_ds_d2h[10] = tl_sm1_28_us_d2h[1]; - assign tl_debug_mem_o = tl_sm1_16_ds_h2d; - assign tl_sm1_16_ds_d2h = tl_debug_mem_i; + assign tl_s1n_15_us_h2d = tl_corei_i; + assign tl_corei_o = tl_s1n_15_us_d2h; - assign tl_ram_main_o = tl_sm1_17_ds_h2d; - assign tl_sm1_17_ds_d2h = tl_ram_main_i; + assign tl_rom_o = tl_sm1_16_ds_h2d; + assign tl_sm1_16_ds_d2h = tl_rom_i; - assign tl_eflash_o = tl_sm1_18_ds_h2d; - assign tl_sm1_18_ds_d2h = tl_eflash_i; + assign tl_debug_mem_o = tl_sm1_17_ds_h2d; + assign tl_sm1_17_ds_d2h = tl_debug_mem_i; - assign tl_s1n_19_us_h2d = tl_cored_i; - assign tl_cored_o = tl_s1n_19_us_d2h; + assign tl_ram_main_o = tl_sm1_18_ds_h2d; + assign tl_sm1_18_ds_d2h = tl_ram_main_i; - assign tl_uart_o = tl_sm1_20_ds_h2d; - assign tl_sm1_20_ds_d2h = tl_uart_i; + assign tl_eflash_o = tl_sm1_19_ds_h2d; + assign tl_sm1_19_ds_d2h = tl_eflash_i; - assign tl_gpio_o = tl_sm1_21_ds_h2d; - assign tl_sm1_21_ds_d2h = tl_gpio_i; + assign tl_s1n_20_us_h2d = tl_cored_i; + assign tl_cored_o = tl_s1n_20_us_d2h; - assign tl_spi_device_o = tl_sm1_22_ds_h2d; - assign tl_sm1_22_ds_d2h = tl_spi_device_i; + assign tl_uart_o = tl_sm1_21_ds_h2d; + assign tl_sm1_21_ds_d2h = tl_uart_i; - assign tl_flash_ctrl_o = tl_sm1_23_ds_h2d; - assign tl_sm1_23_ds_d2h = tl_flash_ctrl_i; + assign tl_gpio_o = tl_sm1_22_ds_h2d; + assign tl_sm1_22_ds_d2h = tl_gpio_i; - assign tl_rv_timer_o = tl_sm1_24_ds_h2d; - assign tl_sm1_24_ds_d2h = tl_rv_timer_i; + assign tl_spi_device_o = tl_sm1_23_ds_h2d; + assign tl_sm1_23_ds_d2h = tl_spi_device_i; - assign tl_hmac_o = tl_sm1_25_ds_h2d; - assign tl_sm1_25_ds_d2h = tl_hmac_i; + assign tl_flash_ctrl_o = tl_sm1_24_ds_h2d; + assign tl_sm1_24_ds_d2h = tl_flash_ctrl_i; - assign tl_rv_plic_o = tl_sm1_26_ds_h2d; - assign tl_sm1_26_ds_d2h = tl_rv_plic_i; + assign tl_rv_timer_o = tl_sm1_25_ds_h2d; + assign tl_sm1_25_ds_d2h = tl_rv_timer_i; - assign tl_s1n_27_us_h2d = tl_dm_sba_i; - assign tl_dm_sba_o = tl_s1n_27_us_d2h; + assign tl_aes_o = tl_sm1_26_ds_h2d; + assign tl_sm1_26_ds_d2h = tl_aes_i; + + assign tl_hmac_o = tl_sm1_27_ds_h2d; + assign tl_sm1_27_ds_d2h = tl_hmac_i; + + assign tl_rv_plic_o = tl_sm1_28_ds_h2d; + assign tl_sm1_28_ds_d2h = tl_rv_plic_i; + + assign tl_s1n_29_us_h2d = tl_dm_sba_i; + assign tl_dm_sba_o = tl_s1n_29_us_d2h; always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_14 = 3'd4; - if ((tl_s1n_14_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin - dev_sel_s1n_14 = 3'd0; - end else if ((tl_s1n_14_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin - dev_sel_s1n_14 = 3'd1; - end else if ((tl_s1n_14_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin - dev_sel_s1n_14 = 3'd2; - end else if ((tl_s1n_14_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin - dev_sel_s1n_14 = 3'd3; + dev_sel_s1n_15 = 3'd4; + if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin + dev_sel_s1n_15 = 3'd0; + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin + dev_sel_s1n_15 = 3'd1; + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin + dev_sel_s1n_15 = 3'd2; + end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin + dev_sel_s1n_15 = 3'd3; end end always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_19 = 4'd11; - if ((tl_s1n_19_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin - dev_sel_s1n_19 = 4'd0; - end else if ((tl_s1n_19_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin - dev_sel_s1n_19 = 4'd1; - end else if ((tl_s1n_19_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin - dev_sel_s1n_19 = 4'd2; - end else if ((tl_s1n_19_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin - dev_sel_s1n_19 = 4'd3; - end else if ((tl_s1n_19_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin - dev_sel_s1n_19 = 4'd4; - end else if ((tl_s1n_19_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin - dev_sel_s1n_19 = 4'd5; - end else if ((tl_s1n_19_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin - dev_sel_s1n_19 = 4'd6; - end else if ((tl_s1n_19_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin - dev_sel_s1n_19 = 4'd7; - end else if ((tl_s1n_19_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin - dev_sel_s1n_19 = 4'd8; - end else if ((tl_s1n_19_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin - dev_sel_s1n_19 = 4'd9; - end else if ((tl_s1n_19_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin - dev_sel_s1n_19 = 4'd10; + dev_sel_s1n_20 = 4'd12; + if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin + dev_sel_s1n_20 = 4'd0; + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin + dev_sel_s1n_20 = 4'd1; + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin + dev_sel_s1n_20 = 4'd2; + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin + dev_sel_s1n_20 = 4'd3; + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin + dev_sel_s1n_20 = 4'd4; + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin + dev_sel_s1n_20 = 4'd5; + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin + dev_sel_s1n_20 = 4'd6; + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin + dev_sel_s1n_20 = 4'd7; + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin + dev_sel_s1n_20 = 4'd8; + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin + dev_sel_s1n_20 = 4'd9; + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin + dev_sel_s1n_20 = 4'd10; + end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin + dev_sel_s1n_20 = 4'd11; end end always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_27 = 4'd10; - if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin - dev_sel_s1n_27 = 4'd0; - end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin - dev_sel_s1n_27 = 4'd1; - end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin - dev_sel_s1n_27 = 4'd2; - end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin - dev_sel_s1n_27 = 4'd3; - end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin - dev_sel_s1n_27 = 4'd4; - end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin - dev_sel_s1n_27 = 4'd5; - end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin - dev_sel_s1n_27 = 4'd6; - end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin - dev_sel_s1n_27 = 4'd7; - end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin - dev_sel_s1n_27 = 4'd8; - end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin - dev_sel_s1n_27 = 4'd9; + dev_sel_s1n_29 = 4'd11; + if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin + dev_sel_s1n_29 = 4'd0; + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin + dev_sel_s1n_29 = 4'd1; + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin + dev_sel_s1n_29 = 4'd2; + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin + dev_sel_s1n_29 = 4'd3; + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin + dev_sel_s1n_29 = 4'd4; + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin + dev_sel_s1n_29 = 4'd5; + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin + dev_sel_s1n_29 = 4'd6; + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin + dev_sel_s1n_29 = 4'd7; + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin + dev_sel_s1n_29 = 4'd8; + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin + dev_sel_s1n_29 = 4'd9; + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin + dev_sel_s1n_29 = 4'd10; end end @@ -407,14 +433,14 @@ .DReqDepth ({4{4'h0}}), .DRspDepth ({4{4'h0}}), .N (4) - ) u_s1n_14 ( + ) u_s1n_15 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_14_us_h2d), - .tl_h_o (tl_s1n_14_us_d2h), - .tl_d_o (tl_s1n_14_ds_h2d), - .tl_d_i (tl_s1n_14_ds_d2h), - .dev_select (dev_sel_s1n_14) + .tl_h_i (tl_s1n_15_us_h2d), + .tl_h_o (tl_s1n_15_us_d2h), + .tl_d_o (tl_s1n_15_ds_h2d), + .tl_d_i (tl_s1n_15_ds_d2h), + .dev_select (dev_sel_s1n_15) ); tlul_socket_m1 #( .HReqDepth ({3{4'h0}}), @@ -422,20 +448,6 @@ .DReqDepth (4'h0), .DRspDepth (4'h0), .M (3) - ) u_sm1_15 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_15_us_h2d), - .tl_h_o (tl_sm1_15_us_d2h), - .tl_d_o (tl_sm1_15_ds_h2d), - .tl_d_i (tl_sm1_15_ds_d2h) - ); - tlul_socket_m1 #( - .HReqPass (2'h0), - .HRspPass (2'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) ) u_sm1_16 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), @@ -445,11 +457,11 @@ .tl_d_i (tl_sm1_16_ds_d2h) ); tlul_socket_m1 #( - .HReqDepth ({3{4'h0}}), - .HRspDepth ({3{4'h0}}), - .DReqDepth (4'h0), - .DRspDepth (4'h0), - .M (3) + .HReqPass (2'h0), + .HRspPass (2'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) ) u_sm1_17 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), @@ -472,34 +484,34 @@ .tl_d_o (tl_sm1_18_ds_h2d), .tl_d_i (tl_sm1_18_ds_d2h) ); + tlul_socket_m1 #( + .HReqDepth ({3{4'h0}}), + .HRspDepth ({3{4'h0}}), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (3) + ) u_sm1_19 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_19_us_h2d), + .tl_h_o (tl_sm1_19_us_d2h), + .tl_d_o (tl_sm1_19_ds_h2d), + .tl_d_i (tl_sm1_19_ds_d2h) + ); tlul_socket_1n #( .HReqDepth (4'h0), .HRspDepth (4'h0), - .DReqDepth ({11{4'h0}}), - .DRspDepth ({11{4'h0}}), - .N (11) - ) u_s1n_19 ( + .DReqDepth ({12{4'h0}}), + .DRspDepth ({12{4'h0}}), + .N (12) + ) u_s1n_20 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_19_us_h2d), - .tl_h_o (tl_s1n_19_us_d2h), - .tl_d_o (tl_s1n_19_ds_h2d), - .tl_d_i (tl_s1n_19_ds_d2h), - .dev_select (dev_sel_s1n_19) - ); - tlul_socket_m1 #( - .HReqPass (2'h0), - .HRspPass (2'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_20 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_20_us_h2d), - .tl_h_o (tl_sm1_20_us_d2h), - .tl_d_o (tl_sm1_20_ds_h2d), - .tl_d_i (tl_sm1_20_ds_d2h) + .tl_h_i (tl_s1n_20_us_h2d), + .tl_h_o (tl_s1n_20_us_d2h), + .tl_d_o (tl_s1n_20_ds_h2d), + .tl_d_i (tl_s1n_20_ds_d2h), + .dev_select (dev_sel_s1n_20) ); tlul_socket_m1 #( .HReqPass (2'h0), @@ -585,20 +597,48 @@ .tl_d_o (tl_sm1_26_ds_h2d), .tl_d_i (tl_sm1_26_ds_d2h) ); + tlul_socket_m1 #( + .HReqPass (2'h0), + .HRspPass (2'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_27 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_27_us_h2d), + .tl_h_o (tl_sm1_27_us_d2h), + .tl_d_o (tl_sm1_27_ds_h2d), + .tl_d_i (tl_sm1_27_ds_d2h) + ); + tlul_socket_m1 #( + .HReqPass (2'h0), + .HRspPass (2'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_28 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_28_us_h2d), + .tl_h_o (tl_sm1_28_us_d2h), + .tl_d_o (tl_sm1_28_ds_h2d), + .tl_d_i (tl_sm1_28_ds_d2h) + ); tlul_socket_1n #( .HReqPass (1'b0), .HRspPass (1'b0), - .DReqPass (10'h0), - .DRspPass (10'h0), - .N (10) - ) u_s1n_27 ( + .DReqPass (11'h0), + .DRspPass (11'h0), + .N (11) + ) u_s1n_29 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_27_us_h2d), - .tl_h_o (tl_s1n_27_us_d2h), - .tl_d_o (tl_s1n_27_ds_h2d), - .tl_d_i (tl_s1n_27_ds_d2h), - .dev_select (dev_sel_s1n_27) + .tl_h_i (tl_s1n_29_us_h2d), + .tl_h_o (tl_s1n_29_us_d2h), + .tl_d_o (tl_s1n_29_ds_h2d), + .tl_d_i (tl_s1n_29_ds_d2h), + .dev_select (dev_sel_s1n_29) ); endmodule
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 5800ec7..c46d0b7 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -32,6 +32,7 @@ output cio_spi_device_miso_en_d2p_o, // flash_ctrl // rv_timer + // aes // hmac // rv_plic @@ -65,6 +66,8 @@ tl_d2h_t tl_flash_ctrl_d_d2h; tl_h2d_t tl_rv_timer_d_h2d; tl_d2h_t tl_rv_timer_d_d2h; + tl_h2d_t tl_aes_d_h2d; + tl_d2h_t tl_aes_d_d2h; tl_h2d_t tl_hmac_d_h2d; tl_d2h_t tl_hmac_d_d2h; tl_h2d_t tl_rv_plic_d_h2d; @@ -428,6 +431,14 @@ .rst_ni (sys_rst_n) ); + aes aes ( + .tl_i (tl_aes_d_h2d), + .tl_o (tl_aes_d_d2h), + + .clk_i (main_clk), + .rst_ni (sys_rst_n) + ); + hmac hmac ( .tl_i (tl_hmac_d_h2d), .tl_o (tl_hmac_d_d2h), @@ -511,6 +522,8 @@ .tl_rv_timer_i (tl_rv_timer_d_d2h), .tl_hmac_o (tl_hmac_d_h2d), .tl_hmac_i (tl_hmac_d_d2h), + .tl_aes_o (tl_aes_d_h2d), + .tl_aes_i (tl_aes_d_d2h), .tl_rv_plic_o (tl_rv_plic_d_h2d), .tl_rv_plic_i (tl_rv_plic_d_d2h),
diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core index 5905d78..85ca60c 100644 --- a/hw/top_earlgrey/top_earlgrey.core +++ b/hw/top_earlgrey/top_earlgrey.core
@@ -15,6 +15,7 @@ - lowrisc:ip:rv_timer - lowrisc:ip:tlul - lowrisc:ip:spi_device + - lowrisc:ip:aes - lowrisc:ip:hmac - lowrisc:prim:ram_1p - lowrisc:prim:rom