[xbar/dv] Update xbar for new regression flow Signed-off-by: Weicai Yang <weicai@google.com>
diff --git a/hw/ip/tlul/data/tlul_testplan.hjson b/hw/ip/tlul/data/tlul_testplan.hjson index 87e5f93..fe85048 100644 --- a/hw/ip/tlul/data/tlul_testplan.hjson +++ b/hw/ip/tlul/data/tlul_testplan.hjson
@@ -73,7 +73,7 @@ stress seq and then start a new stress seq - Run a few iteration to ensure reset doesn't break the design''' milestone: V2 - tests: ["xbar_stress_all_with_reset", "xbar_stress_all_with_reset_error"] + tests: ["xbar_stress_all_with_rand_reset", "xbar_stress_all_with_reset_error"] } ] }
diff --git a/hw/ip/tlul/generic_dv/env/seq_lib/xbar_stress_all_with_reset_vseq.sv b/hw/ip/tlul/generic_dv/env/seq_lib/xbar_stress_all_with_rand_reset_vseq.sv similarity index 94% rename from hw/ip/tlul/generic_dv/env/seq_lib/xbar_stress_all_with_reset_vseq.sv rename to hw/ip/tlul/generic_dv/env/seq_lib/xbar_stress_all_with_rand_reset_vseq.sv index 991974f..f2a2593 100644 --- a/hw/ip/tlul/generic_dv/env/seq_lib/xbar_stress_all_with_reset_vseq.sv +++ b/hw/ip/tlul/generic_dv/env/seq_lib/xbar_stress_all_with_rand_reset_vseq.sv
@@ -4,8 +4,8 @@ // one thread running the hmac_stress_all sequence // another thread randomly insert reset -class xbar_stress_all_with_reset_vseq extends xbar_base_vseq; - `uvm_object_utils(xbar_stress_all_with_reset_vseq) +class xbar_stress_all_with_rand_reset_vseq extends xbar_base_vseq; + `uvm_object_utils(xbar_stress_all_with_rand_reset_vseq) rand uint delay;
diff --git a/hw/ip/tlul/generic_dv/env/seq_lib/xbar_vseq_list.sv b/hw/ip/tlul/generic_dv/env/seq_lib/xbar_vseq_list.sv index aef1331..83abdd3 100644 --- a/hw/ip/tlul/generic_dv/env/seq_lib/xbar_vseq_list.sv +++ b/hw/ip/tlul/generic_dv/env/seq_lib/xbar_vseq_list.sv
@@ -11,4 +11,4 @@ `include "xbar_same_source_vseq.sv" `include "xbar_unmapped_addr_vseq.sv" `include "xbar_stress_all_vseq.sv" -`include "xbar_stress_all_with_reset_vseq.sv" +`include "xbar_stress_all_with_rand_reset_vseq.sv"
diff --git a/hw/ip/tlul/generic_dv/env/xbar_env.core b/hw/ip/tlul/generic_dv/env/xbar_env.core index 83c3cec..0953fed 100644 --- a/hw/ip/tlul/generic_dv/env/xbar_env.core +++ b/hw/ip/tlul/generic_dv/env/xbar_env.core
@@ -27,7 +27,7 @@ - seq_lib/xbar_same_source_vseq.sv: {is_include_file: true} - seq_lib/xbar_unmapped_addr_vseq.sv: {is_include_file: true} - seq_lib/xbar_stress_all_vseq.sv: {is_include_file: true} - - seq_lib/xbar_stress_all_with_reset_vseq.sv: {is_include_file: true} + - seq_lib/xbar_stress_all_with_rand_reset_vseq.sv: {is_include_file: true} file_type: systemVerilogSource targets:
diff --git a/hw/ip/tlul/generic_dv/xbar.mk b/hw/ip/tlul/generic_dv/xbar.mk index ebb951d..632a05a 100644 --- a/hw/ip/tlul/generic_dv/xbar.mk +++ b/hw/ip/tlul/generic_dv/xbar.mk
@@ -113,13 +113,13 @@ UVM_TEST_SEQ = xbar_stress_all_vseq endif -ifeq (${TEST_NAME},xbar_stress_all_with_reset) - UVM_TEST_SEQ = xbar_stress_all_with_reset_vseq +ifeq (${TEST_NAME},xbar_stress_all_with_rand_reset) + UVM_TEST_SEQ = xbar_stress_all_with_rand_reset_vseq endif ifeq (${TEST_NAME},xbar_stress_all_with_reset_error) UVM_TEST = xbar_error_test - UVM_TEST_SEQ = xbar_stress_all_with_reset_vseq + UVM_TEST_SEQ = xbar_stress_all_with_rand_reset_vseq endif ####################################################################################################
diff --git a/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson b/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson new file mode 100644 index 0000000..d60d629 --- /dev/null +++ b/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson
@@ -0,0 +1,168 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: xbar + + // Top level testbench name (sv module). + tb: tb + + // dut is set in the autogenerated sim_cfg hjson file as following + // dut: xbar_main + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:dv:{dut}_sim:0.1 + + // Testplan hjson file. + testplan: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson" + + // no reg in xbar. This is a make variable in hw/dv/data/sim.mk. Set it to skip make target (RAL) + exports: [ + skip_gen_ral_pkg: 1 + ] + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/data/common_sim_cfg.hjson"] + + // Add additional tops for simulation. + sim_tops: ["-top {dut}_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // Default UVM test and seq class name. + uvm_test: xbar_base_test + uvm_test_seq: xbar_base_vseq + + // Add xbar specific exclusion files. + vcs_cov_excl_files: ["{proj_root}/hw/top_earlgrey/ip/{dut}/dv/autogen/cov/xbar_cov_excl.el"] + + // List of test specifications. + tests: [ + { + name: xbar_sanity + uvm_test_seq: xbar_sanity_vseq + } + + { + name: xbar_sanity_zero_delays + uvm_test_seq: xbar_sanity_vseq + run_opts: ["+zero_delays=1"] + } + + { + name: xbar_sanity_large_delays + uvm_test_seq: xbar_sanity_vseq + run_opts: ["+max_host_req_delay=1000", + "+max_host_rsp_delay=1000", + "+max_device_req_delay=1000", + "+max_device_rsp_delay=1000"] + } + + { + name: xbar_sanity_slow_rsp + uvm_test_seq: xbar_sanity_vseq + run_opts: ["+max_host_req_delay=10", + "+max_host_rsp_delay=1000", + "+max_device_req_delay=1000", + "+max_device_rsp_delay=10"] + } + + { + name: xbar_random + uvm_test_seq: xbar_random_vseq + } + + { + name: xbar_random_zero_delays + uvm_test_seq: xbar_random_vseq + run_opts: ["+zero_delays=1"] + } + + { + name: xbar_random_large_delays + uvm_test_seq: xbar_random_vseq + run_opts: ["+max_host_req_delay=1000", + "+max_host_rsp_delay=1000", + "+max_device_req_delay=1000", + "+max_device_rsp_delay=1000"] + } + + { + name: xbar_random_slow_rsp + uvm_test_seq: xbar_random_vseq + run_opts: ["+max_host_req_delay=10", + "+max_host_rsp_delay=1000", + "+max_device_req_delay=1000", + "+max_device_rsp_delay=10"] + } + + { + name: xbar_access_same_device + uvm_test_seq: xbar_access_same_device_vseq + } + + { + name: xbar_access_same_device_slow_rsp + uvm_test_seq: xbar_access_same_device_vseq + run_opts: ["+max_host_req_delay=10", + "+max_host_rsp_delay=1000", + "+max_device_req_delay=1000", + "+max_device_rsp_delay=10"] + } + + { + name: xbar_same_source + uvm_test_seq: xbar_same_source_vseq + } + + { + name: xbar_error_random + uvm_test: xbar_error_test + uvm_test_seq: xbar_random_vseq + } + + { + name: xbar_unmapped_addr + uvm_test_seq: xbar_unmapped_addr_vseq + } + + { + name: xbar_error_and_unmapped_addr + uvm_test: xbar_error_test + uvm_test_seq: xbar_unmapped_addr_vseq + } + + { + name: xbar_stress_all + uvm_test_seq: xbar_stress_all_vseq + } + + { + name: xbar_stress_all_with_rand_reset + uvm_test_seq: xbar_stress_all_with_rand_reset_vseq + } + + { + name: xbar_stress_all_with_error + uvm_test: xbar_error_test + uvm_test_seq: xbar_stress_all_vseq + } + + { + name: xbar_stress_all_with_reset_error + uvm_test: xbar_error_test + uvm_test_seq: xbar_stress_all_with_rand_reset_vseq + } + ] + + // List of regressions. + regressions: [ + { + name: sanity + tests: ["xbar_sanity"] + } + ] +}
diff --git a/hw/top_earlgrey/data/top_earlgrey_sim_cfgs_list.hjson b/hw/top_earlgrey/data/top_earlgrey_sim_cfgs_list.hjson index be7109c..f153899 100644 --- a/hw/top_earlgrey/data/top_earlgrey_sim_cfgs_list.hjson +++ b/hw/top_earlgrey/data/top_earlgrey_sim_cfgs_list.hjson
@@ -14,7 +14,9 @@ "{proj_root}/hw/ip/rv_timer/dv/rv_timer_sim_cfg.hjson", "{proj_root}/hw/ip/spi_device/dv/spi_device_sim_cfg.hjson", "{proj_root}/hw/ip/uart/dv/uart_sim_cfg.hjson", - "{proj_root}/hw/ip/usbdev/dv/usbdev_sim_cfg.hjson"] + "{proj_root}/hw/ip/usbdev/dv/usbdev_sim_cfg.hjson", + "{proj_root}/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson", + "{proj_root}/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson"] // TODO: #1467 chip DV is WIP - uncomment when sims are passing. // "{proj_root}/hw/top_earlgrey/dv/chip_sim_cfg.hjson"] }
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson new file mode 100644 index 0000000..20b8ba9 --- /dev/null +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson
@@ -0,0 +1,14 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_main_sim_cfg.hjson file generated by `tlgen.py` tool +{ + // Top level dut name (sv module). + dut: xbar_main + + // Import additional common sim cfg files. + import_cfgs: [// xbar common sim cfg file + "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"] + +}
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson new file mode 100644 index 0000000..e7685df --- /dev/null +++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson
@@ -0,0 +1,14 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri_sim_cfg.hjson file generated by `tlgen.py` tool +{ + // Top level dut name (sv module). + dut: xbar_peri + + // Import additional common sim cfg files. + import_cfgs: [// xbar common sim cfg file + "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"] + +}
diff --git a/util/tlgen/generate_tb.py b/util/tlgen/generate_tb.py index 91e41f2..446f5f4 100644 --- a/util/tlgen/generate_tb.py +++ b/util/tlgen/generate_tb.py
@@ -16,7 +16,7 @@ # list all the generate files for TB tb_files = [ "xbar_env_pkg__params.sv", "tb__xbar_connect.sv", "xbar.sim.core", - "xbar.bind.sv", "Makefile" + "xbar.bind.sv", "Makefile", "xbar.sim_cfg.hjson" ] for fname in tb_files: @@ -27,6 +27,8 @@ fname = "xbar_%s_sim.core" % (xbar.name) elif fname == "xbar.bind.sv": fname = "xbar_%s_bind.sv" % (xbar.name) + elif fname == "xbar.sim_cfg.hjson": + fname = "xbar_%s_sim_cfg.hjson" % (xbar.name) dv_filepath = dv_path / fname with dv_filepath.open(mode='w', encoding='UTF-8') as fout:
diff --git a/util/tlgen/xbar.sim_cfg.hjson.tpl b/util/tlgen/xbar.sim_cfg.hjson.tpl new file mode 100644 index 0000000..243035d --- /dev/null +++ b/util/tlgen/xbar.sim_cfg.hjson.tpl
@@ -0,0 +1,14 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_${xbar.name}_sim_cfg.hjson file generated by `tlgen.py` tool +{ + // Top level dut name (sv module). + dut: xbar_${xbar.name} + + // Import additional common sim cfg files. + import_cfgs: [// xbar common sim cfg file + "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"] + +}