|  | // Copyright lowRISC contributors. | 
|  | // Licensed under the Apache License, Version 2.0, see LICENSE for details. | 
|  | // SPDX-License-Identifier: Apache-2.0 | 
|  | { | 
|  | // Name of the sim cfg - typically same as the name of the DUT. | 
|  | name: pattgen | 
|  |  | 
|  | // Top level dut name (sv module). | 
|  | dut: pattgen | 
|  |  | 
|  | // Top level testbench name (sv module). | 
|  | tb: tb | 
|  |  | 
|  | // Simulator used to sign off this block | 
|  | tool: xcelium | 
|  |  | 
|  | // Fusesoc core file used for building the file list. | 
|  | fusesoc_core: lowrisc:dv:pattgen_sim:0.1 | 
|  |  | 
|  | // Testplan hjson file. | 
|  | testplan: "{proj_root}/hw/ip/pattgen/data/pattgen_testplan.hjson" | 
|  |  | 
|  | // RAL spec - used to generate the RAL model. | 
|  | ral_spec: "{proj_root}/hw/ip/pattgen/data/pattgen.hjson" | 
|  |  | 
|  | // Import additional common sim cfg files. | 
|  | // TODO: remove imported cfgs that do not apply. | 
|  | import_cfgs: [// Project wide common sim cfg file | 
|  | "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", | 
|  | // Common CIP test lists | 
|  | "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", | 
|  | "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", | 
|  | "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", | 
|  | "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson", | 
|  | "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", | 
|  | "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"] | 
|  |  | 
|  | // Default iterations for all tests - each test entry can override this. | 
|  | reseed: 50 | 
|  |  | 
|  | // Default UVM test and seq class name. | 
|  | uvm_test: pattgen_base_test | 
|  | uvm_test_seq: pattgen_base_vseq, | 
|  |  | 
|  | // additional top for coverage | 
|  | sim_tops: [ "pattgen_bind", "pattgen_cov_bind", "sec_cm_prim_onehot_check_bind"] | 
|  |  | 
|  | // Pattgen coverage exclusion | 
|  | xcelium_cov_refine_files: ["{proj_root}/hw/ip/pattgen/dv/cov/pattgen_cov.vRefine"] | 
|  |  | 
|  | run_opts: ["+cdc_instrumentation_enabled=1"] | 
|  |  | 
|  | // List of test specifications. | 
|  | tests: [ | 
|  | { | 
|  | name: pattgen_smoke | 
|  | uvm_test_seq: pattgen_smoke_vseq | 
|  | } | 
|  |  | 
|  | { | 
|  | name: pattgen_perf | 
|  | uvm_test_seq: pattgen_perf_vseq | 
|  | } | 
|  |  | 
|  | { | 
|  | name: pattgen_error | 
|  | uvm_test_seq: pattgen_error_vseq | 
|  | } | 
|  |  | 
|  | { | 
|  | name: cnt_rollover | 
|  | uvm_test_seq: pattgen_cnt_rollover_vseq | 
|  | } | 
|  | ] | 
|  |  | 
|  | // List of regressions. | 
|  | regressions: [ | 
|  | { | 
|  | name: smoke | 
|  | tests: ["pattgen_smoke"] | 
|  | } | 
|  | ] | 
|  | } |