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opensecura / 3p / lowrisc / opentitan / d2e920a57653d7b8165fde33a75e5d5ec95e7c3b / . / hw / ip / pwm / rtl / pwm_reg_top.sv
blob: 3d023cb973dc63af4fc1cac0f99406e4a3094149 [file] [log] [blame]
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `reggen`
`include "prim_assert.sv"
module pwm_reg_top (
input clk_i,
input rst_ni,
input clk_core_i,
input rst_core_ni,
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
// To HW
output pwm_reg_pkg::pwm_reg2hw_t reg2hw, // Write
// Integrity check errors
output logic intg_err_o,
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
import pwm_reg_pkg::* ;
localparam int AW = 7;
localparam int DW = 32;
localparam int DBW = DW/8; // Byte Width
// register signals
logic reg_we;
logic reg_re;
logic [AW-1:0] reg_addr;
logic [DW-1:0] reg_wdata;
logic [DBW-1:0] reg_be;
logic [DW-1:0] reg_rdata;
logic reg_error;
logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
logic reg_busy;
tlul_pkg::tl_h2d_t tl_reg_h2d;
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
logic intg_err;
tlul_cmd_intg_chk u_chk (
.tl_i(tl_i),
.err_o(intg_err)
);
// also check for spurious write enables
logic reg_we_err;
logic [22:0] reg_we_check;
prim_reg_we_check #(
.OneHotWidth(23)
) u_prim_reg_we_check (
.clk_i(clk_i),
.rst_ni(rst_ni),
.oh_i (reg_we_check),
.en_i (reg_we && !addrmiss),
.err_o (reg_we_err)
);
logic err_q;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
err_q <= '0;
end else if (intg_err || reg_we_err) begin
err_q <= 1'b1;
end
end
// integrity error output is permanent and should be used for alert generation
// register errors are transactional
assign intg_err_o = err_q | intg_err | reg_we_err;
// outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
tlul_rsp_intg_gen #(
.EnableRspIntgGen(1),
.EnableDataIntgGen(1)
) u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o(tl_o)
);
assign tl_reg_h2d = tl_i;
assign tl_o_pre = tl_reg_d2h;
tlul_adapter_reg #(
.RegAw(AW),
.RegDw(DW),
.EnableDataIntgGen(0)
) u_reg_if (
.clk_i (clk_i),
.rst_ni (rst_ni),
.tl_i (tl_reg_h2d),
.tl_o (tl_reg_d2h),
.en_ifetch_i(prim_mubi_pkg::MuBi4False),
.intg_error_o(),
.we_o (reg_we),
.re_o (reg_re),
.addr_o (reg_addr),
.wdata_o (reg_wdata),
.be_o (reg_be),
.busy_i (reg_busy),
.rdata_i (reg_rdata),
.error_i (reg_error)
);
// cdc oversampling signals
assign reg_rdata = reg_rdata_next ;
assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
logic alert_test_we;
logic alert_test_wd;
logic regwen_we;
logic regwen_qs;
logic regwen_wd;
logic cfg_we;
logic [31:0] cfg_qs;
logic cfg_busy;
logic pwm_en_we;
logic [5:0] pwm_en_qs;
logic pwm_en_busy;
logic invert_we;
logic [5:0] invert_qs;
logic invert_busy;
logic pwm_param_0_we;
logic [31:0] pwm_param_0_qs;
logic pwm_param_0_busy;
logic pwm_param_1_we;
logic [31:0] pwm_param_1_qs;
logic pwm_param_1_busy;
logic pwm_param_2_we;
logic [31:0] pwm_param_2_qs;
logic pwm_param_2_busy;
logic pwm_param_3_we;
logic [31:0] pwm_param_3_qs;
logic pwm_param_3_busy;
logic pwm_param_4_we;
logic [31:0] pwm_param_4_qs;
logic pwm_param_4_busy;
logic pwm_param_5_we;
logic [31:0] pwm_param_5_qs;
logic pwm_param_5_busy;
logic duty_cycle_0_we;
logic [31:0] duty_cycle_0_qs;
logic duty_cycle_0_busy;
logic duty_cycle_1_we;
logic [31:0] duty_cycle_1_qs;
logic duty_cycle_1_busy;
logic duty_cycle_2_we;
logic [31:0] duty_cycle_2_qs;
logic duty_cycle_2_busy;
logic duty_cycle_3_we;
logic [31:0] duty_cycle_3_qs;
logic duty_cycle_3_busy;
logic duty_cycle_4_we;
logic [31:0] duty_cycle_4_qs;
logic duty_cycle_4_busy;
logic duty_cycle_5_we;
logic [31:0] duty_cycle_5_qs;
logic duty_cycle_5_busy;
logic blink_param_0_we;
logic [31:0] blink_param_0_qs;
logic blink_param_0_busy;
logic blink_param_1_we;
logic [31:0] blink_param_1_qs;
logic blink_param_1_busy;
logic blink_param_2_we;
logic [31:0] blink_param_2_qs;
logic blink_param_2_busy;
logic blink_param_3_we;
logic [31:0] blink_param_3_qs;
logic blink_param_3_busy;
logic blink_param_4_we;
logic [31:0] blink_param_4_qs;
logic blink_param_4_busy;
logic blink_param_5_we;
logic [31:0] blink_param_5_qs;
logic blink_param_5_busy;
// Define register CDC handling.
// CDC handling is done on a per-reg instead of per-field boundary.
logic [26:0] core_cfg_clk_div_qs_int;
logic [3:0] core_cfg_dc_resn_qs_int;
logic core_cfg_cntr_en_qs_int;
logic [31:0] core_cfg_qs;
logic [31:0] core_cfg_wdata;
logic core_cfg_we;
logic unused_core_cfg_wdata;
logic core_cfg_regwen;
always_comb begin
core_cfg_qs = 32'h38008000;
core_cfg_qs[26:0] = core_cfg_clk_div_qs_int;
core_cfg_qs[30:27] = core_cfg_dc_resn_qs_int;
core_cfg_qs[31] = core_cfg_cntr_en_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h38008000),
.BitMask(32'hffffffff),
.DstWrReq(0)
) u_cfg_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (cfg_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (cfg_busy),
.src_qs_o (cfg_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_cfg_qs),
.dst_we_o (core_cfg_we),
.dst_re_o (),
.dst_regwen_o (core_cfg_regwen),
.dst_wd_o (core_cfg_wdata)
);
assign unused_core_cfg_wdata =
^core_cfg_wdata;
logic core_pwm_en_en_0_qs_int;
logic core_pwm_en_en_1_qs_int;
logic core_pwm_en_en_2_qs_int;
logic core_pwm_en_en_3_qs_int;
logic core_pwm_en_en_4_qs_int;
logic core_pwm_en_en_5_qs_int;
logic [5:0] core_pwm_en_qs;
logic [5:0] core_pwm_en_wdata;
logic core_pwm_en_we;
logic unused_core_pwm_en_wdata;
logic core_pwm_en_regwen;
always_comb begin
core_pwm_en_qs = 6'h0;
core_pwm_en_qs[0] = core_pwm_en_en_0_qs_int;
core_pwm_en_qs[1] = core_pwm_en_en_1_qs_int;
core_pwm_en_qs[2] = core_pwm_en_en_2_qs_int;
core_pwm_en_qs[3] = core_pwm_en_en_3_qs_int;
core_pwm_en_qs[4] = core_pwm_en_en_4_qs_int;
core_pwm_en_qs[5] = core_pwm_en_en_5_qs_int;
end
prim_reg_cdc #(
.DataWidth(6),
.ResetVal(6'h0),
.BitMask(6'h3f),
.DstWrReq(0)
) u_pwm_en_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (pwm_en_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[5:0]),
.src_busy_o (pwm_en_busy),
.src_qs_o (pwm_en_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_pwm_en_qs),
.dst_we_o (core_pwm_en_we),
.dst_re_o (),
.dst_regwen_o (core_pwm_en_regwen),
.dst_wd_o (core_pwm_en_wdata)
);
assign unused_core_pwm_en_wdata =
^core_pwm_en_wdata;
logic core_invert_invert_0_qs_int;
logic core_invert_invert_1_qs_int;
logic core_invert_invert_2_qs_int;
logic core_invert_invert_3_qs_int;
logic core_invert_invert_4_qs_int;
logic core_invert_invert_5_qs_int;
logic [5:0] core_invert_qs;
logic [5:0] core_invert_wdata;
logic core_invert_we;
logic unused_core_invert_wdata;
logic core_invert_regwen;
always_comb begin
core_invert_qs = 6'h0;
core_invert_qs[0] = core_invert_invert_0_qs_int;
core_invert_qs[1] = core_invert_invert_1_qs_int;
core_invert_qs[2] = core_invert_invert_2_qs_int;
core_invert_qs[3] = core_invert_invert_3_qs_int;
core_invert_qs[4] = core_invert_invert_4_qs_int;
core_invert_qs[5] = core_invert_invert_5_qs_int;
end
prim_reg_cdc #(
.DataWidth(6),
.ResetVal(6'h0),
.BitMask(6'h3f),
.DstWrReq(0)
) u_invert_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (invert_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[5:0]),
.src_busy_o (invert_busy),
.src_qs_o (invert_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_invert_qs),
.dst_we_o (core_invert_we),
.dst_re_o (),
.dst_regwen_o (core_invert_regwen),
.dst_wd_o (core_invert_wdata)
);
assign unused_core_invert_wdata =
^core_invert_wdata;
logic [15:0] core_pwm_param_0_phase_delay_0_qs_int;
logic core_pwm_param_0_htbt_en_0_qs_int;
logic core_pwm_param_0_blink_en_0_qs_int;
logic [31:0] core_pwm_param_0_qs;
logic [31:0] core_pwm_param_0_wdata;
logic core_pwm_param_0_we;
logic unused_core_pwm_param_0_wdata;
logic core_pwm_param_0_regwen;
always_comb begin
core_pwm_param_0_qs = 32'h0;
core_pwm_param_0_qs[15:0] = core_pwm_param_0_phase_delay_0_qs_int;
core_pwm_param_0_qs[30] = core_pwm_param_0_htbt_en_0_qs_int;
core_pwm_param_0_qs[31] = core_pwm_param_0_blink_en_0_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h0),
.BitMask(32'hc000ffff),
.DstWrReq(0)
) u_pwm_param_0_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (pwm_param_0_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (pwm_param_0_busy),
.src_qs_o (pwm_param_0_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_pwm_param_0_qs),
.dst_we_o (core_pwm_param_0_we),
.dst_re_o (),
.dst_regwen_o (core_pwm_param_0_regwen),
.dst_wd_o (core_pwm_param_0_wdata)
);
assign unused_core_pwm_param_0_wdata =
^core_pwm_param_0_wdata;
logic [15:0] core_pwm_param_1_phase_delay_1_qs_int;
logic core_pwm_param_1_htbt_en_1_qs_int;
logic core_pwm_param_1_blink_en_1_qs_int;
logic [31:0] core_pwm_param_1_qs;
logic [31:0] core_pwm_param_1_wdata;
logic core_pwm_param_1_we;
logic unused_core_pwm_param_1_wdata;
logic core_pwm_param_1_regwen;
always_comb begin
core_pwm_param_1_qs = 32'h0;
core_pwm_param_1_qs[15:0] = core_pwm_param_1_phase_delay_1_qs_int;
core_pwm_param_1_qs[30] = core_pwm_param_1_htbt_en_1_qs_int;
core_pwm_param_1_qs[31] = core_pwm_param_1_blink_en_1_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h0),
.BitMask(32'hc000ffff),
.DstWrReq(0)
) u_pwm_param_1_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (pwm_param_1_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (pwm_param_1_busy),
.src_qs_o (pwm_param_1_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_pwm_param_1_qs),
.dst_we_o (core_pwm_param_1_we),
.dst_re_o (),
.dst_regwen_o (core_pwm_param_1_regwen),
.dst_wd_o (core_pwm_param_1_wdata)
);
assign unused_core_pwm_param_1_wdata =
^core_pwm_param_1_wdata;
logic [15:0] core_pwm_param_2_phase_delay_2_qs_int;
logic core_pwm_param_2_htbt_en_2_qs_int;
logic core_pwm_param_2_blink_en_2_qs_int;
logic [31:0] core_pwm_param_2_qs;
logic [31:0] core_pwm_param_2_wdata;
logic core_pwm_param_2_we;
logic unused_core_pwm_param_2_wdata;
logic core_pwm_param_2_regwen;
always_comb begin
core_pwm_param_2_qs = 32'h0;
core_pwm_param_2_qs[15:0] = core_pwm_param_2_phase_delay_2_qs_int;
core_pwm_param_2_qs[30] = core_pwm_param_2_htbt_en_2_qs_int;
core_pwm_param_2_qs[31] = core_pwm_param_2_blink_en_2_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h0),
.BitMask(32'hc000ffff),
.DstWrReq(0)
) u_pwm_param_2_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (pwm_param_2_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (pwm_param_2_busy),
.src_qs_o (pwm_param_2_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_pwm_param_2_qs),
.dst_we_o (core_pwm_param_2_we),
.dst_re_o (),
.dst_regwen_o (core_pwm_param_2_regwen),
.dst_wd_o (core_pwm_param_2_wdata)
);
assign unused_core_pwm_param_2_wdata =
^core_pwm_param_2_wdata;
logic [15:0] core_pwm_param_3_phase_delay_3_qs_int;
logic core_pwm_param_3_htbt_en_3_qs_int;
logic core_pwm_param_3_blink_en_3_qs_int;
logic [31:0] core_pwm_param_3_qs;
logic [31:0] core_pwm_param_3_wdata;
logic core_pwm_param_3_we;
logic unused_core_pwm_param_3_wdata;
logic core_pwm_param_3_regwen;
always_comb begin
core_pwm_param_3_qs = 32'h0;
core_pwm_param_3_qs[15:0] = core_pwm_param_3_phase_delay_3_qs_int;
core_pwm_param_3_qs[30] = core_pwm_param_3_htbt_en_3_qs_int;
core_pwm_param_3_qs[31] = core_pwm_param_3_blink_en_3_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h0),
.BitMask(32'hc000ffff),
.DstWrReq(0)
) u_pwm_param_3_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (pwm_param_3_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (pwm_param_3_busy),
.src_qs_o (pwm_param_3_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_pwm_param_3_qs),
.dst_we_o (core_pwm_param_3_we),
.dst_re_o (),
.dst_regwen_o (core_pwm_param_3_regwen),
.dst_wd_o (core_pwm_param_3_wdata)
);
assign unused_core_pwm_param_3_wdata =
^core_pwm_param_3_wdata;
logic [15:0] core_pwm_param_4_phase_delay_4_qs_int;
logic core_pwm_param_4_htbt_en_4_qs_int;
logic core_pwm_param_4_blink_en_4_qs_int;
logic [31:0] core_pwm_param_4_qs;
logic [31:0] core_pwm_param_4_wdata;
logic core_pwm_param_4_we;
logic unused_core_pwm_param_4_wdata;
logic core_pwm_param_4_regwen;
always_comb begin
core_pwm_param_4_qs = 32'h0;
core_pwm_param_4_qs[15:0] = core_pwm_param_4_phase_delay_4_qs_int;
core_pwm_param_4_qs[30] = core_pwm_param_4_htbt_en_4_qs_int;
core_pwm_param_4_qs[31] = core_pwm_param_4_blink_en_4_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h0),
.BitMask(32'hc000ffff),
.DstWrReq(0)
) u_pwm_param_4_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (pwm_param_4_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (pwm_param_4_busy),
.src_qs_o (pwm_param_4_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_pwm_param_4_qs),
.dst_we_o (core_pwm_param_4_we),
.dst_re_o (),
.dst_regwen_o (core_pwm_param_4_regwen),
.dst_wd_o (core_pwm_param_4_wdata)
);
assign unused_core_pwm_param_4_wdata =
^core_pwm_param_4_wdata;
logic [15:0] core_pwm_param_5_phase_delay_5_qs_int;
logic core_pwm_param_5_htbt_en_5_qs_int;
logic core_pwm_param_5_blink_en_5_qs_int;
logic [31:0] core_pwm_param_5_qs;
logic [31:0] core_pwm_param_5_wdata;
logic core_pwm_param_5_we;
logic unused_core_pwm_param_5_wdata;
logic core_pwm_param_5_regwen;
always_comb begin
core_pwm_param_5_qs = 32'h0;
core_pwm_param_5_qs[15:0] = core_pwm_param_5_phase_delay_5_qs_int;
core_pwm_param_5_qs[30] = core_pwm_param_5_htbt_en_5_qs_int;
core_pwm_param_5_qs[31] = core_pwm_param_5_blink_en_5_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h0),
.BitMask(32'hc000ffff),
.DstWrReq(0)
) u_pwm_param_5_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (pwm_param_5_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (pwm_param_5_busy),
.src_qs_o (pwm_param_5_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_pwm_param_5_qs),
.dst_we_o (core_pwm_param_5_we),
.dst_re_o (),
.dst_regwen_o (core_pwm_param_5_regwen),
.dst_wd_o (core_pwm_param_5_wdata)
);
assign unused_core_pwm_param_5_wdata =
^core_pwm_param_5_wdata;
logic [15:0] core_duty_cycle_0_a_0_qs_int;
logic [15:0] core_duty_cycle_0_b_0_qs_int;
logic [31:0] core_duty_cycle_0_qs;
logic [31:0] core_duty_cycle_0_wdata;
logic core_duty_cycle_0_we;
logic unused_core_duty_cycle_0_wdata;
logic core_duty_cycle_0_regwen;
always_comb begin
core_duty_cycle_0_qs = 32'h7fff7fff;
core_duty_cycle_0_qs[15:0] = core_duty_cycle_0_a_0_qs_int;
core_duty_cycle_0_qs[31:16] = core_duty_cycle_0_b_0_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h7fff7fff),
.BitMask(32'hffffffff),
.DstWrReq(0)
) u_duty_cycle_0_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (duty_cycle_0_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (duty_cycle_0_busy),
.src_qs_o (duty_cycle_0_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_duty_cycle_0_qs),
.dst_we_o (core_duty_cycle_0_we),
.dst_re_o (),
.dst_regwen_o (core_duty_cycle_0_regwen),
.dst_wd_o (core_duty_cycle_0_wdata)
);
assign unused_core_duty_cycle_0_wdata =
^core_duty_cycle_0_wdata;
logic [15:0] core_duty_cycle_1_a_1_qs_int;
logic [15:0] core_duty_cycle_1_b_1_qs_int;
logic [31:0] core_duty_cycle_1_qs;
logic [31:0] core_duty_cycle_1_wdata;
logic core_duty_cycle_1_we;
logic unused_core_duty_cycle_1_wdata;
logic core_duty_cycle_1_regwen;
always_comb begin
core_duty_cycle_1_qs = 32'h7fff7fff;
core_duty_cycle_1_qs[15:0] = core_duty_cycle_1_a_1_qs_int;
core_duty_cycle_1_qs[31:16] = core_duty_cycle_1_b_1_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h7fff7fff),
.BitMask(32'hffffffff),
.DstWrReq(0)
) u_duty_cycle_1_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (duty_cycle_1_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (duty_cycle_1_busy),
.src_qs_o (duty_cycle_1_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_duty_cycle_1_qs),
.dst_we_o (core_duty_cycle_1_we),
.dst_re_o (),
.dst_regwen_o (core_duty_cycle_1_regwen),
.dst_wd_o (core_duty_cycle_1_wdata)
);
assign unused_core_duty_cycle_1_wdata =
^core_duty_cycle_1_wdata;
logic [15:0] core_duty_cycle_2_a_2_qs_int;
logic [15:0] core_duty_cycle_2_b_2_qs_int;
logic [31:0] core_duty_cycle_2_qs;
logic [31:0] core_duty_cycle_2_wdata;
logic core_duty_cycle_2_we;
logic unused_core_duty_cycle_2_wdata;
logic core_duty_cycle_2_regwen;
always_comb begin
core_duty_cycle_2_qs = 32'h7fff7fff;
core_duty_cycle_2_qs[15:0] = core_duty_cycle_2_a_2_qs_int;
core_duty_cycle_2_qs[31:16] = core_duty_cycle_2_b_2_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h7fff7fff),
.BitMask(32'hffffffff),
.DstWrReq(0)
) u_duty_cycle_2_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (duty_cycle_2_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (duty_cycle_2_busy),
.src_qs_o (duty_cycle_2_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_duty_cycle_2_qs),
.dst_we_o (core_duty_cycle_2_we),
.dst_re_o (),
.dst_regwen_o (core_duty_cycle_2_regwen),
.dst_wd_o (core_duty_cycle_2_wdata)
);
assign unused_core_duty_cycle_2_wdata =
^core_duty_cycle_2_wdata;
logic [15:0] core_duty_cycle_3_a_3_qs_int;
logic [15:0] core_duty_cycle_3_b_3_qs_int;
logic [31:0] core_duty_cycle_3_qs;
logic [31:0] core_duty_cycle_3_wdata;
logic core_duty_cycle_3_we;
logic unused_core_duty_cycle_3_wdata;
logic core_duty_cycle_3_regwen;
always_comb begin
core_duty_cycle_3_qs = 32'h7fff7fff;
core_duty_cycle_3_qs[15:0] = core_duty_cycle_3_a_3_qs_int;
core_duty_cycle_3_qs[31:16] = core_duty_cycle_3_b_3_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h7fff7fff),
.BitMask(32'hffffffff),
.DstWrReq(0)
) u_duty_cycle_3_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (duty_cycle_3_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (duty_cycle_3_busy),
.src_qs_o (duty_cycle_3_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_duty_cycle_3_qs),
.dst_we_o (core_duty_cycle_3_we),
.dst_re_o (),
.dst_regwen_o (core_duty_cycle_3_regwen),
.dst_wd_o (core_duty_cycle_3_wdata)
);
assign unused_core_duty_cycle_3_wdata =
^core_duty_cycle_3_wdata;
logic [15:0] core_duty_cycle_4_a_4_qs_int;
logic [15:0] core_duty_cycle_4_b_4_qs_int;
logic [31:0] core_duty_cycle_4_qs;
logic [31:0] core_duty_cycle_4_wdata;
logic core_duty_cycle_4_we;
logic unused_core_duty_cycle_4_wdata;
logic core_duty_cycle_4_regwen;
always_comb begin
core_duty_cycle_4_qs = 32'h7fff7fff;
core_duty_cycle_4_qs[15:0] = core_duty_cycle_4_a_4_qs_int;
core_duty_cycle_4_qs[31:16] = core_duty_cycle_4_b_4_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h7fff7fff),
.BitMask(32'hffffffff),
.DstWrReq(0)
) u_duty_cycle_4_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (duty_cycle_4_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (duty_cycle_4_busy),
.src_qs_o (duty_cycle_4_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_duty_cycle_4_qs),
.dst_we_o (core_duty_cycle_4_we),
.dst_re_o (),
.dst_regwen_o (core_duty_cycle_4_regwen),
.dst_wd_o (core_duty_cycle_4_wdata)
);
assign unused_core_duty_cycle_4_wdata =
^core_duty_cycle_4_wdata;
logic [15:0] core_duty_cycle_5_a_5_qs_int;
logic [15:0] core_duty_cycle_5_b_5_qs_int;
logic [31:0] core_duty_cycle_5_qs;
logic [31:0] core_duty_cycle_5_wdata;
logic core_duty_cycle_5_we;
logic unused_core_duty_cycle_5_wdata;
logic core_duty_cycle_5_regwen;
always_comb begin
core_duty_cycle_5_qs = 32'h7fff7fff;
core_duty_cycle_5_qs[15:0] = core_duty_cycle_5_a_5_qs_int;
core_duty_cycle_5_qs[31:16] = core_duty_cycle_5_b_5_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h7fff7fff),
.BitMask(32'hffffffff),
.DstWrReq(0)
) u_duty_cycle_5_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (duty_cycle_5_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (duty_cycle_5_busy),
.src_qs_o (duty_cycle_5_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_duty_cycle_5_qs),
.dst_we_o (core_duty_cycle_5_we),
.dst_re_o (),
.dst_regwen_o (core_duty_cycle_5_regwen),
.dst_wd_o (core_duty_cycle_5_wdata)
);
assign unused_core_duty_cycle_5_wdata =
^core_duty_cycle_5_wdata;
logic [15:0] core_blink_param_0_x_0_qs_int;
logic [15:0] core_blink_param_0_y_0_qs_int;
logic [31:0] core_blink_param_0_qs;
logic [31:0] core_blink_param_0_wdata;
logic core_blink_param_0_we;
logic unused_core_blink_param_0_wdata;
logic core_blink_param_0_regwen;
always_comb begin
core_blink_param_0_qs = 32'h0;
core_blink_param_0_qs[15:0] = core_blink_param_0_x_0_qs_int;
core_blink_param_0_qs[31:16] = core_blink_param_0_y_0_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h0),
.BitMask(32'hffffffff),
.DstWrReq(0)
) u_blink_param_0_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (blink_param_0_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (blink_param_0_busy),
.src_qs_o (blink_param_0_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_blink_param_0_qs),
.dst_we_o (core_blink_param_0_we),
.dst_re_o (),
.dst_regwen_o (core_blink_param_0_regwen),
.dst_wd_o (core_blink_param_0_wdata)
);
assign unused_core_blink_param_0_wdata =
^core_blink_param_0_wdata;
logic [15:0] core_blink_param_1_x_1_qs_int;
logic [15:0] core_blink_param_1_y_1_qs_int;
logic [31:0] core_blink_param_1_qs;
logic [31:0] core_blink_param_1_wdata;
logic core_blink_param_1_we;
logic unused_core_blink_param_1_wdata;
logic core_blink_param_1_regwen;
always_comb begin
core_blink_param_1_qs = 32'h0;
core_blink_param_1_qs[15:0] = core_blink_param_1_x_1_qs_int;
core_blink_param_1_qs[31:16] = core_blink_param_1_y_1_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h0),
.BitMask(32'hffffffff),
.DstWrReq(0)
) u_blink_param_1_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (blink_param_1_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (blink_param_1_busy),
.src_qs_o (blink_param_1_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_blink_param_1_qs),
.dst_we_o (core_blink_param_1_we),
.dst_re_o (),
.dst_regwen_o (core_blink_param_1_regwen),
.dst_wd_o (core_blink_param_1_wdata)
);
assign unused_core_blink_param_1_wdata =
^core_blink_param_1_wdata;
logic [15:0] core_blink_param_2_x_2_qs_int;
logic [15:0] core_blink_param_2_y_2_qs_int;
logic [31:0] core_blink_param_2_qs;
logic [31:0] core_blink_param_2_wdata;
logic core_blink_param_2_we;
logic unused_core_blink_param_2_wdata;
logic core_blink_param_2_regwen;
always_comb begin
core_blink_param_2_qs = 32'h0;
core_blink_param_2_qs[15:0] = core_blink_param_2_x_2_qs_int;
core_blink_param_2_qs[31:16] = core_blink_param_2_y_2_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h0),
.BitMask(32'hffffffff),
.DstWrReq(0)
) u_blink_param_2_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (blink_param_2_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (blink_param_2_busy),
.src_qs_o (blink_param_2_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_blink_param_2_qs),
.dst_we_o (core_blink_param_2_we),
.dst_re_o (),
.dst_regwen_o (core_blink_param_2_regwen),
.dst_wd_o (core_blink_param_2_wdata)
);
assign unused_core_blink_param_2_wdata =
^core_blink_param_2_wdata;
logic [15:0] core_blink_param_3_x_3_qs_int;
logic [15:0] core_blink_param_3_y_3_qs_int;
logic [31:0] core_blink_param_3_qs;
logic [31:0] core_blink_param_3_wdata;
logic core_blink_param_3_we;
logic unused_core_blink_param_3_wdata;
logic core_blink_param_3_regwen;
always_comb begin
core_blink_param_3_qs = 32'h0;
core_blink_param_3_qs[15:0] = core_blink_param_3_x_3_qs_int;
core_blink_param_3_qs[31:16] = core_blink_param_3_y_3_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h0),
.BitMask(32'hffffffff),
.DstWrReq(0)
) u_blink_param_3_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (blink_param_3_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (blink_param_3_busy),
.src_qs_o (blink_param_3_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_blink_param_3_qs),
.dst_we_o (core_blink_param_3_we),
.dst_re_o (),
.dst_regwen_o (core_blink_param_3_regwen),
.dst_wd_o (core_blink_param_3_wdata)
);
assign unused_core_blink_param_3_wdata =
^core_blink_param_3_wdata;
logic [15:0] core_blink_param_4_x_4_qs_int;
logic [15:0] core_blink_param_4_y_4_qs_int;
logic [31:0] core_blink_param_4_qs;
logic [31:0] core_blink_param_4_wdata;
logic core_blink_param_4_we;
logic unused_core_blink_param_4_wdata;
logic core_blink_param_4_regwen;
always_comb begin
core_blink_param_4_qs = 32'h0;
core_blink_param_4_qs[15:0] = core_blink_param_4_x_4_qs_int;
core_blink_param_4_qs[31:16] = core_blink_param_4_y_4_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h0),
.BitMask(32'hffffffff),
.DstWrReq(0)
) u_blink_param_4_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (blink_param_4_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (blink_param_4_busy),
.src_qs_o (blink_param_4_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_blink_param_4_qs),
.dst_we_o (core_blink_param_4_we),
.dst_re_o (),
.dst_regwen_o (core_blink_param_4_regwen),
.dst_wd_o (core_blink_param_4_wdata)
);
assign unused_core_blink_param_4_wdata =
^core_blink_param_4_wdata;
logic [15:0] core_blink_param_5_x_5_qs_int;
logic [15:0] core_blink_param_5_y_5_qs_int;
logic [31:0] core_blink_param_5_qs;
logic [31:0] core_blink_param_5_wdata;
logic core_blink_param_5_we;
logic unused_core_blink_param_5_wdata;
logic core_blink_param_5_regwen;
always_comb begin
core_blink_param_5_qs = 32'h0;
core_blink_param_5_qs[15:0] = core_blink_param_5_x_5_qs_int;
core_blink_param_5_qs[31:16] = core_blink_param_5_y_5_qs_int;
end
prim_reg_cdc #(
.DataWidth(32),
.ResetVal(32'h0),
.BitMask(32'hffffffff),
.DstWrReq(0)
) u_blink_param_5_cdc (
.clk_src_i (clk_i),
.rst_src_ni (rst_ni),
.clk_dst_i (clk_core_i),
.rst_dst_ni (rst_core_ni),
.src_regwen_i (regwen_qs),
.src_we_i (blink_param_5_we),
.src_re_i ('0),
.src_wd_i (reg_wdata[31:0]),
.src_busy_o (blink_param_5_busy),
.src_qs_o (blink_param_5_qs), // for software read back
.dst_update_i ('0),
.dst_ds_i ('0),
.dst_qs_i (core_blink_param_5_qs),
.dst_we_o (core_blink_param_5_we),
.dst_re_o (),
.dst_regwen_o (core_blink_param_5_regwen),
.dst_wd_o (core_blink_param_5_wdata)
);
assign unused_core_blink_param_5_wdata =
^core_blink_param_5_wdata;
// Register instances
// R[alert_test]: V(True)
logic alert_test_qe;
logic [0:0] alert_test_flds_we;
assign alert_test_qe = &alert_test_flds_we;
prim_subreg_ext #(
.DW (1)
) u_alert_test (
.re (1'b0),
.we (alert_test_we),
.wd (alert_test_wd),
.d ('0),
.qre (),
.qe (alert_test_flds_we[0]),
.q (reg2hw.alert_test.q),
.ds (),
.qs ()
);
assign reg2hw.alert_test.qe = alert_test_qe;
// R[regwen]: V(False)
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW0C),
.RESVAL (1'h1)
) u_regwen (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (regwen_we),
.wd (regwen_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (),
.q (),
.ds (),
// to register interface (read)
.qs (regwen_qs)
);
// R[cfg]: V(False)
logic cfg_qe;
logic [2:0] cfg_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_cfg0_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&cfg_flds_we),
.q_o(cfg_qe)
);
// Create REGWEN-gated WE signal
logic core_cfg_gated_we;
assign core_cfg_gated_we = core_cfg_we & core_cfg_regwen;
// F[clk_div]: 26:0
prim_subreg #(
.DW (27),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (27'h8000)
) u_cfg_clk_div (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_cfg_gated_we),
.wd (core_cfg_wdata[26:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (cfg_flds_we[0]),
.q (reg2hw.cfg.clk_div.q),
.ds (),
// to register interface (read)
.qs (core_cfg_clk_div_qs_int)
);
assign reg2hw.cfg.clk_div.qe = cfg_qe;
// F[dc_resn]: 30:27
prim_subreg #(
.DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (4'h7)
) u_cfg_dc_resn (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_cfg_gated_we),
.wd (core_cfg_wdata[30:27]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (cfg_flds_we[1]),
.q (reg2hw.cfg.dc_resn.q),
.ds (),
// to register interface (read)
.qs (core_cfg_dc_resn_qs_int)
);
assign reg2hw.cfg.dc_resn.qe = cfg_qe;
// F[cntr_en]: 31:31
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_cfg_cntr_en (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_cfg_gated_we),
.wd (core_cfg_wdata[31]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (cfg_flds_we[2]),
.q (reg2hw.cfg.cntr_en.q),
.ds (),
// to register interface (read)
.qs (core_cfg_cntr_en_qs_int)
);
assign reg2hw.cfg.cntr_en.qe = cfg_qe;
// Subregister 0 of Multireg pwm_en
// R[pwm_en]: V(False)
logic pwm_en_qe;
logic [5:0] pwm_en_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_pwm_en0_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&pwm_en_flds_we),
.q_o(pwm_en_qe)
);
// Create REGWEN-gated WE signal
logic core_pwm_en_gated_we;
assign core_pwm_en_gated_we = core_pwm_en_we & core_pwm_en_regwen;
// F[en_0]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_en_en_0 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_en_gated_we),
.wd (core_pwm_en_wdata[0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_en_flds_we[0]),
.q (reg2hw.pwm_en[0].q),
.ds (),
// to register interface (read)
.qs (core_pwm_en_en_0_qs_int)
);
assign reg2hw.pwm_en[0].qe = pwm_en_qe;
// F[en_1]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_en_en_1 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_en_gated_we),
.wd (core_pwm_en_wdata[1]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_en_flds_we[1]),
.q (reg2hw.pwm_en[1].q),
.ds (),
// to register interface (read)
.qs (core_pwm_en_en_1_qs_int)
);
assign reg2hw.pwm_en[1].qe = pwm_en_qe;
// F[en_2]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_en_en_2 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_en_gated_we),
.wd (core_pwm_en_wdata[2]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_en_flds_we[2]),
.q (reg2hw.pwm_en[2].q),
.ds (),
// to register interface (read)
.qs (core_pwm_en_en_2_qs_int)
);
assign reg2hw.pwm_en[2].qe = pwm_en_qe;
// F[en_3]: 3:3
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_en_en_3 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_en_gated_we),
.wd (core_pwm_en_wdata[3]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_en_flds_we[3]),
.q (reg2hw.pwm_en[3].q),
.ds (),
// to register interface (read)
.qs (core_pwm_en_en_3_qs_int)
);
assign reg2hw.pwm_en[3].qe = pwm_en_qe;
// F[en_4]: 4:4
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_en_en_4 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_en_gated_we),
.wd (core_pwm_en_wdata[4]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_en_flds_we[4]),
.q (reg2hw.pwm_en[4].q),
.ds (),
// to register interface (read)
.qs (core_pwm_en_en_4_qs_int)
);
assign reg2hw.pwm_en[4].qe = pwm_en_qe;
// F[en_5]: 5:5
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_en_en_5 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_en_gated_we),
.wd (core_pwm_en_wdata[5]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_en_flds_we[5]),
.q (reg2hw.pwm_en[5].q),
.ds (),
// to register interface (read)
.qs (core_pwm_en_en_5_qs_int)
);
assign reg2hw.pwm_en[5].qe = pwm_en_qe;
// Subregister 0 of Multireg invert
// R[invert]: V(False)
logic invert_qe;
logic [5:0] invert_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_invert0_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&invert_flds_we),
.q_o(invert_qe)
);
// Create REGWEN-gated WE signal
logic core_invert_gated_we;
assign core_invert_gated_we = core_invert_we & core_invert_regwen;
// F[invert_0]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_invert_invert_0 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_invert_gated_we),
.wd (core_invert_wdata[0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (invert_flds_we[0]),
.q (reg2hw.invert[0].q),
.ds (),
// to register interface (read)
.qs (core_invert_invert_0_qs_int)
);
assign reg2hw.invert[0].qe = invert_qe;
// F[invert_1]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_invert_invert_1 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_invert_gated_we),
.wd (core_invert_wdata[1]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (invert_flds_we[1]),
.q (reg2hw.invert[1].q),
.ds (),
// to register interface (read)
.qs (core_invert_invert_1_qs_int)
);
assign reg2hw.invert[1].qe = invert_qe;
// F[invert_2]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_invert_invert_2 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_invert_gated_we),
.wd (core_invert_wdata[2]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (invert_flds_we[2]),
.q (reg2hw.invert[2].q),
.ds (),
// to register interface (read)
.qs (core_invert_invert_2_qs_int)
);
assign reg2hw.invert[2].qe = invert_qe;
// F[invert_3]: 3:3
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_invert_invert_3 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_invert_gated_we),
.wd (core_invert_wdata[3]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (invert_flds_we[3]),
.q (reg2hw.invert[3].q),
.ds (),
// to register interface (read)
.qs (core_invert_invert_3_qs_int)
);
assign reg2hw.invert[3].qe = invert_qe;
// F[invert_4]: 4:4
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_invert_invert_4 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_invert_gated_we),
.wd (core_invert_wdata[4]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (invert_flds_we[4]),
.q (reg2hw.invert[4].q),
.ds (),
// to register interface (read)
.qs (core_invert_invert_4_qs_int)
);
assign reg2hw.invert[4].qe = invert_qe;
// F[invert_5]: 5:5
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_invert_invert_5 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_invert_gated_we),
.wd (core_invert_wdata[5]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (invert_flds_we[5]),
.q (reg2hw.invert[5].q),
.ds (),
// to register interface (read)
.qs (core_invert_invert_5_qs_int)
);
assign reg2hw.invert[5].qe = invert_qe;
// Subregister 0 of Multireg pwm_param
// R[pwm_param_0]: V(False)
logic pwm_param_0_qe;
logic [2:0] pwm_param_0_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_pwm_param0_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&pwm_param_0_flds_we),
.q_o(pwm_param_0_qe)
);
// Create REGWEN-gated WE signal
logic core_pwm_param_0_gated_we;
assign core_pwm_param_0_gated_we = core_pwm_param_0_we & core_pwm_param_0_regwen;
// F[phase_delay_0]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_pwm_param_0_phase_delay_0 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_0_gated_we),
.wd (core_pwm_param_0_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_0_flds_we[0]),
.q (reg2hw.pwm_param[0].phase_delay.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_0_phase_delay_0_qs_int)
);
assign reg2hw.pwm_param[0].phase_delay.qe = pwm_param_0_qe;
// F[htbt_en_0]: 30:30
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_param_0_htbt_en_0 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_0_gated_we),
.wd (core_pwm_param_0_wdata[30]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_0_flds_we[1]),
.q (reg2hw.pwm_param[0].htbt_en.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_0_htbt_en_0_qs_int)
);
assign reg2hw.pwm_param[0].htbt_en.qe = pwm_param_0_qe;
// F[blink_en_0]: 31:31
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_param_0_blink_en_0 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_0_gated_we),
.wd (core_pwm_param_0_wdata[31]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_0_flds_we[2]),
.q (reg2hw.pwm_param[0].blink_en.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_0_blink_en_0_qs_int)
);
assign reg2hw.pwm_param[0].blink_en.qe = pwm_param_0_qe;
// Subregister 1 of Multireg pwm_param
// R[pwm_param_1]: V(False)
logic pwm_param_1_qe;
logic [2:0] pwm_param_1_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_pwm_param1_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&pwm_param_1_flds_we),
.q_o(pwm_param_1_qe)
);
// Create REGWEN-gated WE signal
logic core_pwm_param_1_gated_we;
assign core_pwm_param_1_gated_we = core_pwm_param_1_we & core_pwm_param_1_regwen;
// F[phase_delay_1]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_pwm_param_1_phase_delay_1 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_1_gated_we),
.wd (core_pwm_param_1_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_1_flds_we[0]),
.q (reg2hw.pwm_param[1].phase_delay.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_1_phase_delay_1_qs_int)
);
assign reg2hw.pwm_param[1].phase_delay.qe = pwm_param_1_qe;
// F[htbt_en_1]: 30:30
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_param_1_htbt_en_1 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_1_gated_we),
.wd (core_pwm_param_1_wdata[30]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_1_flds_we[1]),
.q (reg2hw.pwm_param[1].htbt_en.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_1_htbt_en_1_qs_int)
);
assign reg2hw.pwm_param[1].htbt_en.qe = pwm_param_1_qe;
// F[blink_en_1]: 31:31
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_param_1_blink_en_1 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_1_gated_we),
.wd (core_pwm_param_1_wdata[31]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_1_flds_we[2]),
.q (reg2hw.pwm_param[1].blink_en.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_1_blink_en_1_qs_int)
);
assign reg2hw.pwm_param[1].blink_en.qe = pwm_param_1_qe;
// Subregister 2 of Multireg pwm_param
// R[pwm_param_2]: V(False)
logic pwm_param_2_qe;
logic [2:0] pwm_param_2_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_pwm_param2_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&pwm_param_2_flds_we),
.q_o(pwm_param_2_qe)
);
// Create REGWEN-gated WE signal
logic core_pwm_param_2_gated_we;
assign core_pwm_param_2_gated_we = core_pwm_param_2_we & core_pwm_param_2_regwen;
// F[phase_delay_2]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_pwm_param_2_phase_delay_2 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_2_gated_we),
.wd (core_pwm_param_2_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_2_flds_we[0]),
.q (reg2hw.pwm_param[2].phase_delay.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_2_phase_delay_2_qs_int)
);
assign reg2hw.pwm_param[2].phase_delay.qe = pwm_param_2_qe;
// F[htbt_en_2]: 30:30
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_param_2_htbt_en_2 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_2_gated_we),
.wd (core_pwm_param_2_wdata[30]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_2_flds_we[1]),
.q (reg2hw.pwm_param[2].htbt_en.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_2_htbt_en_2_qs_int)
);
assign reg2hw.pwm_param[2].htbt_en.qe = pwm_param_2_qe;
// F[blink_en_2]: 31:31
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_param_2_blink_en_2 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_2_gated_we),
.wd (core_pwm_param_2_wdata[31]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_2_flds_we[2]),
.q (reg2hw.pwm_param[2].blink_en.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_2_blink_en_2_qs_int)
);
assign reg2hw.pwm_param[2].blink_en.qe = pwm_param_2_qe;
// Subregister 3 of Multireg pwm_param
// R[pwm_param_3]: V(False)
logic pwm_param_3_qe;
logic [2:0] pwm_param_3_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_pwm_param3_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&pwm_param_3_flds_we),
.q_o(pwm_param_3_qe)
);
// Create REGWEN-gated WE signal
logic core_pwm_param_3_gated_we;
assign core_pwm_param_3_gated_we = core_pwm_param_3_we & core_pwm_param_3_regwen;
// F[phase_delay_3]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_pwm_param_3_phase_delay_3 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_3_gated_we),
.wd (core_pwm_param_3_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_3_flds_we[0]),
.q (reg2hw.pwm_param[3].phase_delay.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_3_phase_delay_3_qs_int)
);
assign reg2hw.pwm_param[3].phase_delay.qe = pwm_param_3_qe;
// F[htbt_en_3]: 30:30
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_param_3_htbt_en_3 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_3_gated_we),
.wd (core_pwm_param_3_wdata[30]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_3_flds_we[1]),
.q (reg2hw.pwm_param[3].htbt_en.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_3_htbt_en_3_qs_int)
);
assign reg2hw.pwm_param[3].htbt_en.qe = pwm_param_3_qe;
// F[blink_en_3]: 31:31
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_param_3_blink_en_3 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_3_gated_we),
.wd (core_pwm_param_3_wdata[31]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_3_flds_we[2]),
.q (reg2hw.pwm_param[3].blink_en.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_3_blink_en_3_qs_int)
);
assign reg2hw.pwm_param[3].blink_en.qe = pwm_param_3_qe;
// Subregister 4 of Multireg pwm_param
// R[pwm_param_4]: V(False)
logic pwm_param_4_qe;
logic [2:0] pwm_param_4_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_pwm_param4_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&pwm_param_4_flds_we),
.q_o(pwm_param_4_qe)
);
// Create REGWEN-gated WE signal
logic core_pwm_param_4_gated_we;
assign core_pwm_param_4_gated_we = core_pwm_param_4_we & core_pwm_param_4_regwen;
// F[phase_delay_4]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_pwm_param_4_phase_delay_4 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_4_gated_we),
.wd (core_pwm_param_4_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_4_flds_we[0]),
.q (reg2hw.pwm_param[4].phase_delay.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_4_phase_delay_4_qs_int)
);
assign reg2hw.pwm_param[4].phase_delay.qe = pwm_param_4_qe;
// F[htbt_en_4]: 30:30
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_param_4_htbt_en_4 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_4_gated_we),
.wd (core_pwm_param_4_wdata[30]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_4_flds_we[1]),
.q (reg2hw.pwm_param[4].htbt_en.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_4_htbt_en_4_qs_int)
);
assign reg2hw.pwm_param[4].htbt_en.qe = pwm_param_4_qe;
// F[blink_en_4]: 31:31
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_param_4_blink_en_4 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_4_gated_we),
.wd (core_pwm_param_4_wdata[31]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_4_flds_we[2]),
.q (reg2hw.pwm_param[4].blink_en.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_4_blink_en_4_qs_int)
);
assign reg2hw.pwm_param[4].blink_en.qe = pwm_param_4_qe;
// Subregister 5 of Multireg pwm_param
// R[pwm_param_5]: V(False)
logic pwm_param_5_qe;
logic [2:0] pwm_param_5_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_pwm_param5_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&pwm_param_5_flds_we),
.q_o(pwm_param_5_qe)
);
// Create REGWEN-gated WE signal
logic core_pwm_param_5_gated_we;
assign core_pwm_param_5_gated_we = core_pwm_param_5_we & core_pwm_param_5_regwen;
// F[phase_delay_5]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_pwm_param_5_phase_delay_5 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_5_gated_we),
.wd (core_pwm_param_5_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_5_flds_we[0]),
.q (reg2hw.pwm_param[5].phase_delay.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_5_phase_delay_5_qs_int)
);
assign reg2hw.pwm_param[5].phase_delay.qe = pwm_param_5_qe;
// F[htbt_en_5]: 30:30
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_param_5_htbt_en_5 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_5_gated_we),
.wd (core_pwm_param_5_wdata[30]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_5_flds_we[1]),
.q (reg2hw.pwm_param[5].htbt_en.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_5_htbt_en_5_qs_int)
);
assign reg2hw.pwm_param[5].htbt_en.qe = pwm_param_5_qe;
// F[blink_en_5]: 31:31
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
) u_pwm_param_5_blink_en_5 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_pwm_param_5_gated_we),
.wd (core_pwm_param_5_wdata[31]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (pwm_param_5_flds_we[2]),
.q (reg2hw.pwm_param[5].blink_en.q),
.ds (),
// to register interface (read)
.qs (core_pwm_param_5_blink_en_5_qs_int)
);
assign reg2hw.pwm_param[5].blink_en.qe = pwm_param_5_qe;
// Subregister 0 of Multireg duty_cycle
// R[duty_cycle_0]: V(False)
logic duty_cycle_0_qe;
logic [1:0] duty_cycle_0_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_duty_cycle0_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&duty_cycle_0_flds_we),
.q_o(duty_cycle_0_qe)
);
// Create REGWEN-gated WE signal
logic core_duty_cycle_0_gated_we;
assign core_duty_cycle_0_gated_we = core_duty_cycle_0_we & core_duty_cycle_0_regwen;
// F[a_0]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h7fff)
) u_duty_cycle_0_a_0 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_duty_cycle_0_gated_we),
.wd (core_duty_cycle_0_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (duty_cycle_0_flds_we[0]),
.q (reg2hw.duty_cycle[0].a.q),
.ds (),
// to register interface (read)
.qs (core_duty_cycle_0_a_0_qs_int)
);
assign reg2hw.duty_cycle[0].a.qe = duty_cycle_0_qe;
// F[b_0]: 31:16
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h7fff)
) u_duty_cycle_0_b_0 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_duty_cycle_0_gated_we),
.wd (core_duty_cycle_0_wdata[31:16]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (duty_cycle_0_flds_we[1]),
.q (reg2hw.duty_cycle[0].b.q),
.ds (),
// to register interface (read)
.qs (core_duty_cycle_0_b_0_qs_int)
);
assign reg2hw.duty_cycle[0].b.qe = duty_cycle_0_qe;
// Subregister 1 of Multireg duty_cycle
// R[duty_cycle_1]: V(False)
logic duty_cycle_1_qe;
logic [1:0] duty_cycle_1_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_duty_cycle1_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&duty_cycle_1_flds_we),
.q_o(duty_cycle_1_qe)
);
// Create REGWEN-gated WE signal
logic core_duty_cycle_1_gated_we;
assign core_duty_cycle_1_gated_we = core_duty_cycle_1_we & core_duty_cycle_1_regwen;
// F[a_1]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h7fff)
) u_duty_cycle_1_a_1 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_duty_cycle_1_gated_we),
.wd (core_duty_cycle_1_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (duty_cycle_1_flds_we[0]),
.q (reg2hw.duty_cycle[1].a.q),
.ds (),
// to register interface (read)
.qs (core_duty_cycle_1_a_1_qs_int)
);
assign reg2hw.duty_cycle[1].a.qe = duty_cycle_1_qe;
// F[b_1]: 31:16
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h7fff)
) u_duty_cycle_1_b_1 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_duty_cycle_1_gated_we),
.wd (core_duty_cycle_1_wdata[31:16]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (duty_cycle_1_flds_we[1]),
.q (reg2hw.duty_cycle[1].b.q),
.ds (),
// to register interface (read)
.qs (core_duty_cycle_1_b_1_qs_int)
);
assign reg2hw.duty_cycle[1].b.qe = duty_cycle_1_qe;
// Subregister 2 of Multireg duty_cycle
// R[duty_cycle_2]: V(False)
logic duty_cycle_2_qe;
logic [1:0] duty_cycle_2_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_duty_cycle2_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&duty_cycle_2_flds_we),
.q_o(duty_cycle_2_qe)
);
// Create REGWEN-gated WE signal
logic core_duty_cycle_2_gated_we;
assign core_duty_cycle_2_gated_we = core_duty_cycle_2_we & core_duty_cycle_2_regwen;
// F[a_2]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h7fff)
) u_duty_cycle_2_a_2 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_duty_cycle_2_gated_we),
.wd (core_duty_cycle_2_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (duty_cycle_2_flds_we[0]),
.q (reg2hw.duty_cycle[2].a.q),
.ds (),
// to register interface (read)
.qs (core_duty_cycle_2_a_2_qs_int)
);
assign reg2hw.duty_cycle[2].a.qe = duty_cycle_2_qe;
// F[b_2]: 31:16
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h7fff)
) u_duty_cycle_2_b_2 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_duty_cycle_2_gated_we),
.wd (core_duty_cycle_2_wdata[31:16]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (duty_cycle_2_flds_we[1]),
.q (reg2hw.duty_cycle[2].b.q),
.ds (),
// to register interface (read)
.qs (core_duty_cycle_2_b_2_qs_int)
);
assign reg2hw.duty_cycle[2].b.qe = duty_cycle_2_qe;
// Subregister 3 of Multireg duty_cycle
// R[duty_cycle_3]: V(False)
logic duty_cycle_3_qe;
logic [1:0] duty_cycle_3_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_duty_cycle3_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&duty_cycle_3_flds_we),
.q_o(duty_cycle_3_qe)
);
// Create REGWEN-gated WE signal
logic core_duty_cycle_3_gated_we;
assign core_duty_cycle_3_gated_we = core_duty_cycle_3_we & core_duty_cycle_3_regwen;
// F[a_3]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h7fff)
) u_duty_cycle_3_a_3 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_duty_cycle_3_gated_we),
.wd (core_duty_cycle_3_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (duty_cycle_3_flds_we[0]),
.q (reg2hw.duty_cycle[3].a.q),
.ds (),
// to register interface (read)
.qs (core_duty_cycle_3_a_3_qs_int)
);
assign reg2hw.duty_cycle[3].a.qe = duty_cycle_3_qe;
// F[b_3]: 31:16
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h7fff)
) u_duty_cycle_3_b_3 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_duty_cycle_3_gated_we),
.wd (core_duty_cycle_3_wdata[31:16]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (duty_cycle_3_flds_we[1]),
.q (reg2hw.duty_cycle[3].b.q),
.ds (),
// to register interface (read)
.qs (core_duty_cycle_3_b_3_qs_int)
);
assign reg2hw.duty_cycle[3].b.qe = duty_cycle_3_qe;
// Subregister 4 of Multireg duty_cycle
// R[duty_cycle_4]: V(False)
logic duty_cycle_4_qe;
logic [1:0] duty_cycle_4_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_duty_cycle4_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&duty_cycle_4_flds_we),
.q_o(duty_cycle_4_qe)
);
// Create REGWEN-gated WE signal
logic core_duty_cycle_4_gated_we;
assign core_duty_cycle_4_gated_we = core_duty_cycle_4_we & core_duty_cycle_4_regwen;
// F[a_4]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h7fff)
) u_duty_cycle_4_a_4 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_duty_cycle_4_gated_we),
.wd (core_duty_cycle_4_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (duty_cycle_4_flds_we[0]),
.q (reg2hw.duty_cycle[4].a.q),
.ds (),
// to register interface (read)
.qs (core_duty_cycle_4_a_4_qs_int)
);
assign reg2hw.duty_cycle[4].a.qe = duty_cycle_4_qe;
// F[b_4]: 31:16
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h7fff)
) u_duty_cycle_4_b_4 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_duty_cycle_4_gated_we),
.wd (core_duty_cycle_4_wdata[31:16]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (duty_cycle_4_flds_we[1]),
.q (reg2hw.duty_cycle[4].b.q),
.ds (),
// to register interface (read)
.qs (core_duty_cycle_4_b_4_qs_int)
);
assign reg2hw.duty_cycle[4].b.qe = duty_cycle_4_qe;
// Subregister 5 of Multireg duty_cycle
// R[duty_cycle_5]: V(False)
logic duty_cycle_5_qe;
logic [1:0] duty_cycle_5_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_duty_cycle5_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&duty_cycle_5_flds_we),
.q_o(duty_cycle_5_qe)
);
// Create REGWEN-gated WE signal
logic core_duty_cycle_5_gated_we;
assign core_duty_cycle_5_gated_we = core_duty_cycle_5_we & core_duty_cycle_5_regwen;
// F[a_5]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h7fff)
) u_duty_cycle_5_a_5 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_duty_cycle_5_gated_we),
.wd (core_duty_cycle_5_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (duty_cycle_5_flds_we[0]),
.q (reg2hw.duty_cycle[5].a.q),
.ds (),
// to register interface (read)
.qs (core_duty_cycle_5_a_5_qs_int)
);
assign reg2hw.duty_cycle[5].a.qe = duty_cycle_5_qe;
// F[b_5]: 31:16
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h7fff)
) u_duty_cycle_5_b_5 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_duty_cycle_5_gated_we),
.wd (core_duty_cycle_5_wdata[31:16]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (duty_cycle_5_flds_we[1]),
.q (reg2hw.duty_cycle[5].b.q),
.ds (),
// to register interface (read)
.qs (core_duty_cycle_5_b_5_qs_int)
);
assign reg2hw.duty_cycle[5].b.qe = duty_cycle_5_qe;
// Subregister 0 of Multireg blink_param
// R[blink_param_0]: V(False)
logic blink_param_0_qe;
logic [1:0] blink_param_0_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_blink_param0_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&blink_param_0_flds_we),
.q_o(blink_param_0_qe)
);
// Create REGWEN-gated WE signal
logic core_blink_param_0_gated_we;
assign core_blink_param_0_gated_we = core_blink_param_0_we & core_blink_param_0_regwen;
// F[x_0]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_blink_param_0_x_0 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_blink_param_0_gated_we),
.wd (core_blink_param_0_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (blink_param_0_flds_we[0]),
.q (reg2hw.blink_param[0].x.q),
.ds (),
// to register interface (read)
.qs (core_blink_param_0_x_0_qs_int)
);
assign reg2hw.blink_param[0].x.qe = blink_param_0_qe;
// F[y_0]: 31:16
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_blink_param_0_y_0 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_blink_param_0_gated_we),
.wd (core_blink_param_0_wdata[31:16]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (blink_param_0_flds_we[1]),
.q (reg2hw.blink_param[0].y.q),
.ds (),
// to register interface (read)
.qs (core_blink_param_0_y_0_qs_int)
);
assign reg2hw.blink_param[0].y.qe = blink_param_0_qe;
// Subregister 1 of Multireg blink_param
// R[blink_param_1]: V(False)
logic blink_param_1_qe;
logic [1:0] blink_param_1_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_blink_param1_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&blink_param_1_flds_we),
.q_o(blink_param_1_qe)
);
// Create REGWEN-gated WE signal
logic core_blink_param_1_gated_we;
assign core_blink_param_1_gated_we = core_blink_param_1_we & core_blink_param_1_regwen;
// F[x_1]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_blink_param_1_x_1 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_blink_param_1_gated_we),
.wd (core_blink_param_1_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (blink_param_1_flds_we[0]),
.q (reg2hw.blink_param[1].x.q),
.ds (),
// to register interface (read)
.qs (core_blink_param_1_x_1_qs_int)
);
assign reg2hw.blink_param[1].x.qe = blink_param_1_qe;
// F[y_1]: 31:16
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_blink_param_1_y_1 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_blink_param_1_gated_we),
.wd (core_blink_param_1_wdata[31:16]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (blink_param_1_flds_we[1]),
.q (reg2hw.blink_param[1].y.q),
.ds (),
// to register interface (read)
.qs (core_blink_param_1_y_1_qs_int)
);
assign reg2hw.blink_param[1].y.qe = blink_param_1_qe;
// Subregister 2 of Multireg blink_param
// R[blink_param_2]: V(False)
logic blink_param_2_qe;
logic [1:0] blink_param_2_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_blink_param2_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&blink_param_2_flds_we),
.q_o(blink_param_2_qe)
);
// Create REGWEN-gated WE signal
logic core_blink_param_2_gated_we;
assign core_blink_param_2_gated_we = core_blink_param_2_we & core_blink_param_2_regwen;
// F[x_2]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_blink_param_2_x_2 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_blink_param_2_gated_we),
.wd (core_blink_param_2_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (blink_param_2_flds_we[0]),
.q (reg2hw.blink_param[2].x.q),
.ds (),
// to register interface (read)
.qs (core_blink_param_2_x_2_qs_int)
);
assign reg2hw.blink_param[2].x.qe = blink_param_2_qe;
// F[y_2]: 31:16
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_blink_param_2_y_2 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_blink_param_2_gated_we),
.wd (core_blink_param_2_wdata[31:16]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (blink_param_2_flds_we[1]),
.q (reg2hw.blink_param[2].y.q),
.ds (),
// to register interface (read)
.qs (core_blink_param_2_y_2_qs_int)
);
assign reg2hw.blink_param[2].y.qe = blink_param_2_qe;
// Subregister 3 of Multireg blink_param
// R[blink_param_3]: V(False)
logic blink_param_3_qe;
logic [1:0] blink_param_3_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_blink_param3_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&blink_param_3_flds_we),
.q_o(blink_param_3_qe)
);
// Create REGWEN-gated WE signal
logic core_blink_param_3_gated_we;
assign core_blink_param_3_gated_we = core_blink_param_3_we & core_blink_param_3_regwen;
// F[x_3]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_blink_param_3_x_3 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_blink_param_3_gated_we),
.wd (core_blink_param_3_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (blink_param_3_flds_we[0]),
.q (reg2hw.blink_param[3].x.q),
.ds (),
// to register interface (read)
.qs (core_blink_param_3_x_3_qs_int)
);
assign reg2hw.blink_param[3].x.qe = blink_param_3_qe;
// F[y_3]: 31:16
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_blink_param_3_y_3 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_blink_param_3_gated_we),
.wd (core_blink_param_3_wdata[31:16]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (blink_param_3_flds_we[1]),
.q (reg2hw.blink_param[3].y.q),
.ds (),
// to register interface (read)
.qs (core_blink_param_3_y_3_qs_int)
);
assign reg2hw.blink_param[3].y.qe = blink_param_3_qe;
// Subregister 4 of Multireg blink_param
// R[blink_param_4]: V(False)
logic blink_param_4_qe;
logic [1:0] blink_param_4_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_blink_param4_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&blink_param_4_flds_we),
.q_o(blink_param_4_qe)
);
// Create REGWEN-gated WE signal
logic core_blink_param_4_gated_we;
assign core_blink_param_4_gated_we = core_blink_param_4_we & core_blink_param_4_regwen;
// F[x_4]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_blink_param_4_x_4 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_blink_param_4_gated_we),
.wd (core_blink_param_4_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (blink_param_4_flds_we[0]),
.q (reg2hw.blink_param[4].x.q),
.ds (),
// to register interface (read)
.qs (core_blink_param_4_x_4_qs_int)
);
assign reg2hw.blink_param[4].x.qe = blink_param_4_qe;
// F[y_4]: 31:16
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_blink_param_4_y_4 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_blink_param_4_gated_we),
.wd (core_blink_param_4_wdata[31:16]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (blink_param_4_flds_we[1]),
.q (reg2hw.blink_param[4].y.q),
.ds (),
// to register interface (read)
.qs (core_blink_param_4_y_4_qs_int)
);
assign reg2hw.blink_param[4].y.qe = blink_param_4_qe;
// Subregister 5 of Multireg blink_param
// R[blink_param_5]: V(False)
logic blink_param_5_qe;
logic [1:0] blink_param_5_flds_we;
prim_flop #(
.Width(1),
.ResetValue(0)
) u_blink_param5_qe (
.clk_i(clk_core_i),
.rst_ni(rst_core_ni),
.d_i(&blink_param_5_flds_we),
.q_o(blink_param_5_qe)
);
// Create REGWEN-gated WE signal
logic core_blink_param_5_gated_we;
assign core_blink_param_5_gated_we = core_blink_param_5_we & core_blink_param_5_regwen;
// F[x_5]: 15:0
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_blink_param_5_x_5 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_blink_param_5_gated_we),
.wd (core_blink_param_5_wdata[15:0]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (blink_param_5_flds_we[0]),
.q (reg2hw.blink_param[5].x.q),
.ds (),
// to register interface (read)
.qs (core_blink_param_5_x_5_qs_int)
);
assign reg2hw.blink_param[5].x.qe = blink_param_5_qe;
// F[y_5]: 31:16
prim_subreg #(
.DW (16),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (16'h0)
) u_blink_param_5_y_5 (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
// from register interface
.we (core_blink_param_5_gated_we),
.wd (core_blink_param_5_wdata[31:16]),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
.qe (blink_param_5_flds_we[1]),
.q (reg2hw.blink_param[5].y.q),
.ds (),
// to register interface (read)
.qs (core_blink_param_5_y_5_qs_int)
);
assign reg2hw.blink_param[5].y.qe = blink_param_5_qe;
logic [22:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == PWM_ALERT_TEST_OFFSET);
addr_hit[ 1] = (reg_addr == PWM_REGWEN_OFFSET);
addr_hit[ 2] = (reg_addr == PWM_CFG_OFFSET);
addr_hit[ 3] = (reg_addr == PWM_PWM_EN_OFFSET);
addr_hit[ 4] = (reg_addr == PWM_INVERT_OFFSET);
addr_hit[ 5] = (reg_addr == PWM_PWM_PARAM_0_OFFSET);
addr_hit[ 6] = (reg_addr == PWM_PWM_PARAM_1_OFFSET);
addr_hit[ 7] = (reg_addr == PWM_PWM_PARAM_2_OFFSET);
addr_hit[ 8] = (reg_addr == PWM_PWM_PARAM_3_OFFSET);
addr_hit[ 9] = (reg_addr == PWM_PWM_PARAM_4_OFFSET);
addr_hit[10] = (reg_addr == PWM_PWM_PARAM_5_OFFSET);
addr_hit[11] = (reg_addr == PWM_DUTY_CYCLE_0_OFFSET);
addr_hit[12] = (reg_addr == PWM_DUTY_CYCLE_1_OFFSET);
addr_hit[13] = (reg_addr == PWM_DUTY_CYCLE_2_OFFSET);
addr_hit[14] = (reg_addr == PWM_DUTY_CYCLE_3_OFFSET);
addr_hit[15] = (reg_addr == PWM_DUTY_CYCLE_4_OFFSET);
addr_hit[16] = (reg_addr == PWM_DUTY_CYCLE_5_OFFSET);
addr_hit[17] = (reg_addr == PWM_BLINK_PARAM_0_OFFSET);
addr_hit[18] = (reg_addr == PWM_BLINK_PARAM_1_OFFSET);
addr_hit[19] = (reg_addr == PWM_BLINK_PARAM_2_OFFSET);
addr_hit[20] = (reg_addr == PWM_BLINK_PARAM_3_OFFSET);
addr_hit[21] = (reg_addr == PWM_BLINK_PARAM_4_OFFSET);
addr_hit[22] = (reg_addr == PWM_BLINK_PARAM_5_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
// Check sub-word write is permitted
always_comb begin
wr_err = (reg_we &
((addr_hit[ 0] & (|(PWM_PERMIT[ 0] & ~reg_be))) |
(addr_hit[ 1] & (|(PWM_PERMIT[ 1] & ~reg_be))) |
(addr_hit[ 2] & (|(PWM_PERMIT[ 2] & ~reg_be))) |
(addr_hit[ 3] & (|(PWM_PERMIT[ 3] & ~reg_be))) |
(addr_hit[ 4] & (|(PWM_PERMIT[ 4] & ~reg_be))) |
(addr_hit[ 5] & (|(PWM_PERMIT[ 5] & ~reg_be))) |
(addr_hit[ 6] & (|(PWM_PERMIT[ 6] & ~reg_be))) |
(addr_hit[ 7] & (|(PWM_PERMIT[ 7] & ~reg_be))) |
(addr_hit[ 8] & (|(PWM_PERMIT[ 8] & ~reg_be))) |
(addr_hit[ 9] & (|(PWM_PERMIT[ 9] & ~reg_be))) |
(addr_hit[10] & (|(PWM_PERMIT[10] & ~reg_be))) |
(addr_hit[11] & (|(PWM_PERMIT[11] & ~reg_be))) |
(addr_hit[12] & (|(PWM_PERMIT[12] & ~reg_be))) |
(addr_hit[13] & (|(PWM_PERMIT[13] & ~reg_be))) |
(addr_hit[14] & (|(PWM_PERMIT[14] & ~reg_be))) |
(addr_hit[15] & (|(PWM_PERMIT[15] & ~reg_be))) |
(addr_hit[16] & (|(PWM_PERMIT[16] & ~reg_be))) |
(addr_hit[17] & (|(PWM_PERMIT[17] & ~reg_be))) |
(addr_hit[18] & (|(PWM_PERMIT[18] & ~reg_be))) |
(addr_hit[19] & (|(PWM_PERMIT[19] & ~reg_be))) |
(addr_hit[20] & (|(PWM_PERMIT[20] & ~reg_be))) |
(addr_hit[21] & (|(PWM_PERMIT[21] & ~reg_be))) |
(addr_hit[22] & (|(PWM_PERMIT[22] & ~reg_be)))));
end
// Generate write-enables
assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
assign alert_test_wd = reg_wdata[0];
assign regwen_we = addr_hit[1] & reg_we & !reg_error;
assign regwen_wd = reg_wdata[0];
assign cfg_we = addr_hit[2] & reg_we & !reg_error;
assign pwm_en_we = addr_hit[3] & reg_we & !reg_error;
assign invert_we = addr_hit[4] & reg_we & !reg_error;
assign pwm_param_0_we = addr_hit[5] & reg_we & !reg_error;
assign pwm_param_1_we = addr_hit[6] & reg_we & !reg_error;
assign pwm_param_2_we = addr_hit[7] & reg_we & !reg_error;
assign pwm_param_3_we = addr_hit[8] & reg_we & !reg_error;
assign pwm_param_4_we = addr_hit[9] & reg_we & !reg_error;
assign pwm_param_5_we = addr_hit[10] & reg_we & !reg_error;
assign duty_cycle_0_we = addr_hit[11] & reg_we & !reg_error;
assign duty_cycle_1_we = addr_hit[12] & reg_we & !reg_error;
assign duty_cycle_2_we = addr_hit[13] & reg_we & !reg_error;
assign duty_cycle_3_we = addr_hit[14] & reg_we & !reg_error;
assign duty_cycle_4_we = addr_hit[15] & reg_we & !reg_error;
assign duty_cycle_5_we = addr_hit[16] & reg_we & !reg_error;
assign blink_param_0_we = addr_hit[17] & reg_we & !reg_error;
assign blink_param_1_we = addr_hit[18] & reg_we & !reg_error;
assign blink_param_2_we = addr_hit[19] & reg_we & !reg_error;
assign blink_param_3_we = addr_hit[20] & reg_we & !reg_error;
assign blink_param_4_we = addr_hit[21] & reg_we & !reg_error;
assign blink_param_5_we = addr_hit[22] & reg_we & !reg_error;
// Assign write-enables to checker logic vector.
always_comb begin
reg_we_check = '0;
reg_we_check[0] = alert_test_we;
reg_we_check[1] = regwen_we;
reg_we_check[2] = cfg_we;
reg_we_check[3] = pwm_en_we;
reg_we_check[4] = invert_we;
reg_we_check[5] = pwm_param_0_we;
reg_we_check[6] = pwm_param_1_we;
reg_we_check[7] = pwm_param_2_we;
reg_we_check[8] = pwm_param_3_we;
reg_we_check[9] = pwm_param_4_we;
reg_we_check[10] = pwm_param_5_we;
reg_we_check[11] = duty_cycle_0_we;
reg_we_check[12] = duty_cycle_1_we;
reg_we_check[13] = duty_cycle_2_we;
reg_we_check[14] = duty_cycle_3_we;
reg_we_check[15] = duty_cycle_4_we;
reg_we_check[16] = duty_cycle_5_we;
reg_we_check[17] = blink_param_0_we;
reg_we_check[18] = blink_param_1_we;
reg_we_check[19] = blink_param_2_we;
reg_we_check[20] = blink_param_3_we;
reg_we_check[21] = blink_param_4_we;
reg_we_check[22] = blink_param_5_we;
end
// Read data return
always_comb begin
reg_rdata_next = '0;
unique case (1'b1)
addr_hit[0]: begin
reg_rdata_next[0] = '0;
end
addr_hit[1]: begin
reg_rdata_next[0] = regwen_qs;
end
addr_hit[2]: begin
reg_rdata_next = DW'(cfg_qs);
end
addr_hit[3]: begin
reg_rdata_next = DW'(pwm_en_qs);
end
addr_hit[4]: begin
reg_rdata_next = DW'(invert_qs);
end
addr_hit[5]: begin
reg_rdata_next = DW'(pwm_param_0_qs);
end
addr_hit[6]: begin
reg_rdata_next = DW'(pwm_param_1_qs);
end
addr_hit[7]: begin
reg_rdata_next = DW'(pwm_param_2_qs);
end
addr_hit[8]: begin
reg_rdata_next = DW'(pwm_param_3_qs);
end
addr_hit[9]: begin
reg_rdata_next = DW'(pwm_param_4_qs);
end
addr_hit[10]: begin
reg_rdata_next = DW'(pwm_param_5_qs);
end
addr_hit[11]: begin
reg_rdata_next = DW'(duty_cycle_0_qs);
end
addr_hit[12]: begin
reg_rdata_next = DW'(duty_cycle_1_qs);
end
addr_hit[13]: begin
reg_rdata_next = DW'(duty_cycle_2_qs);
end
addr_hit[14]: begin
reg_rdata_next = DW'(duty_cycle_3_qs);
end
addr_hit[15]: begin
reg_rdata_next = DW'(duty_cycle_4_qs);
end
addr_hit[16]: begin
reg_rdata_next = DW'(duty_cycle_5_qs);
end
addr_hit[17]: begin
reg_rdata_next = DW'(blink_param_0_qs);
end
addr_hit[18]: begin
reg_rdata_next = DW'(blink_param_1_qs);
end
addr_hit[19]: begin
reg_rdata_next = DW'(blink_param_2_qs);
end
addr_hit[20]: begin
reg_rdata_next = DW'(blink_param_3_qs);
end
addr_hit[21]: begin
reg_rdata_next = DW'(blink_param_4_qs);
end
addr_hit[22]: begin
reg_rdata_next = DW'(blink_param_5_qs);
end
default: begin
reg_rdata_next = '1;
end
endcase
end
// shadow busy
logic shadow_busy;
assign shadow_busy = 1'b0;
// register busy
logic reg_busy_sel;
assign reg_busy = reg_busy_sel | shadow_busy;
always_comb begin
reg_busy_sel = '0;
unique case (1'b1)
addr_hit[2]: begin
reg_busy_sel = cfg_busy;
end
addr_hit[3]: begin
reg_busy_sel = pwm_en_busy;
end
addr_hit[4]: begin
reg_busy_sel = invert_busy;
end
addr_hit[5]: begin
reg_busy_sel = pwm_param_0_busy;
end
addr_hit[6]: begin
reg_busy_sel = pwm_param_1_busy;
end
addr_hit[7]: begin
reg_busy_sel = pwm_param_2_busy;
end
addr_hit[8]: begin
reg_busy_sel = pwm_param_3_busy;
end
addr_hit[9]: begin
reg_busy_sel = pwm_param_4_busy;
end
addr_hit[10]: begin
reg_busy_sel = pwm_param_5_busy;
end
addr_hit[11]: begin
reg_busy_sel = duty_cycle_0_busy;
end
addr_hit[12]: begin
reg_busy_sel = duty_cycle_1_busy;
end
addr_hit[13]: begin
reg_busy_sel = duty_cycle_2_busy;
end
addr_hit[14]: begin
reg_busy_sel = duty_cycle_3_busy;
end
addr_hit[15]: begin
reg_busy_sel = duty_cycle_4_busy;
end
addr_hit[16]: begin
reg_busy_sel = duty_cycle_5_busy;
end
addr_hit[17]: begin
reg_busy_sel = blink_param_0_busy;
end
addr_hit[18]: begin
reg_busy_sel = blink_param_1_busy;
end
addr_hit[19]: begin
reg_busy_sel = blink_param_2_busy;
end
addr_hit[20]: begin
reg_busy_sel = blink_param_3_busy;
end
addr_hit[21]: begin
reg_busy_sel = blink_param_4_busy;
end
addr_hit[22]: begin
reg_busy_sel = blink_param_5_busy;
end
default: begin
reg_busy_sel = '0;
end
endcase
end
// Unused signal tieoff
// wdata / byte enable are not always fully used
// add a blanket unused statement to handle lint waivers
logic unused_wdata;
logic unused_be;
assign unused_wdata = ^reg_wdata;
assign unused_be = ^reg_be;
// Assertions for Register Interface
`ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
`ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
`ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
`ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
// this is formulated as an assumption such that the FPV testbenches do disprove this
// property by mistake
//`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
endmodule