| commit | d2341c28cc4ee4f559dd6086897bbb8e8a0b1d87 | [log] [tgz] |
|---|---|---|
| author | Srikrishna Iyer <sriyer@google.com> | Mon Jan 11 22:31:18 2021 -0800 |
| committer | Srikrishna Iyer <46467186+sriyerg@users.noreply.github.com> | Wed Jan 13 10:18:04 2021 -0800 |
| tree | 5049ffa02900dcdaf89292255cd3cb100a708af4 | |
| parent | 23f31729ac05973f1c5d1613bae1da8ebd8bdf13 [diff] |
[reggen, dv] Add ability to set DV register prefix This came out of a discussion with Nuvoton to add support for generating UVM reg models that are extended not from `dv_base_reg*` classes but from custom classes that add Nuvoton-specific functionality on top of `dv_base_reg*` classes. With this PR, this can be achieved by setting the switch `--dv-base-class-prefix foo`. This approach assumes that the following exist, given the arg value of `foo`: - A fusesoc core with the name `lowrisc:dv:foo_reg` that sources the following files at minimum: - `foo_reg_pkg.sv`: includes the `foo` reg classes below. - `foo_reg.sv`: register class - `foo_reg_field.sv`: field class abstraction - `foo_reg_block.sv`: register block class abstraction - `foo_mem.sv`: memory abstraction - These are required to derive from their corresponding `dv_base_reg*` classes. - If any of these specialized abstractions is not needed, they need to be typedef'ed to the `dv_baes_reg*` one in the pkg. Signed-off-by: Srikrishna Iyer <sriyer@google.com>
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