)]}'
{
  "commit": "d2341c28cc4ee4f559dd6086897bbb8e8a0b1d87",
  "tree": "5049ffa02900dcdaf89292255cd3cb100a708af4",
  "parents": [
    "23f31729ac05973f1c5d1613bae1da8ebd8bdf13"
  ],
  "author": {
    "name": "Srikrishna Iyer",
    "email": "sriyer@google.com",
    "time": "Mon Jan 11 22:31:18 2021 -0800"
  },
  "committer": {
    "name": "Srikrishna Iyer",
    "email": "46467186+sriyerg@users.noreply.github.com",
    "time": "Wed Jan 13 10:18:04 2021 -0800"
  },
  "message": "[reggen, dv] Add ability to set DV register prefix\n\nThis came out of a discussion with Nuvoton to add support for generating\nUVM reg models that are extended not from `dv_base_reg*` classes\nbut from custom classes that add Nuvoton-specific functionality on top of\n`dv_base_reg*` classes. With this PR, this can be achieved by setting\nthe switch `--dv-base-class-prefix foo`. This approach assumes that the\nfollowing exist, given the arg value of `foo`:\n\n- A fusesoc core with the name `lowrisc:dv:foo_reg` that sources the\nfollowing files at minimum:\n  - `foo_reg_pkg.sv`: includes the `foo` reg classes below.\n  - `foo_reg.sv`: register class\n  - `foo_reg_field.sv`: field class abstraction\n  - `foo_reg_block.sv`: register block class abstraction\n  - `foo_mem.sv`: memory abstraction\n- These are required to derive from their corresponding `dv_base_reg*`\nclasses.\n- If any of these specialized abstractions is not needed, they need to\nbe typedef\u0027ed to the `dv_baes_reg*` one in the pkg.\n\nSigned-off-by: Srikrishna Iyer \u003csriyer@google.com\u003e\n",
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