[otp_ctrl/top] Add external voltage pad for otp_ctrl Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/ip/otp_ctrl/dv/tb.sv b/hw/ip/otp_ctrl/dv/tb.sv index fcf3f00..d962200 100644 --- a/hw/ip/otp_ctrl/dv/tb.sv +++ b/hw/ip/otp_ctrl/dv/tb.sv
@@ -57,6 +57,9 @@ assign otp_ctrl_if.lc_prog_req = lc_prog_if.req; assign otp_ctrl_if.lc_prog_err = lc_prog_if.d_data; + // leave this unconnected for now. + wire otp_ext_voltage_h; + // dut otp_ctrl dut ( .clk_i (clk ), @@ -104,7 +107,8 @@ .otbn_otp_key_i (otbn_req), .otbn_otp_key_o (otbn_rsp), - .otp_hw_cfg_o (otp_ctrl_if.otp_hw_cfg_o) + .otp_hw_cfg_o (otp_ctrl_if.otp_hw_cfg_o), + .otp_ext_voltage_h_io (otp_ext_voltage_h) ); for (genvar i = 0; i < NumSramKeyReqSlots; i++) begin : gen_sram_pull_if
diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl.sv index 68258a7..2190d2d 100644 --- a/hw/ip/otp_ctrl/rtl/otp_ctrl.sv +++ b/hw/ip/otp_ctrl/rtl/otp_ctrl.sv
@@ -67,7 +67,9 @@ input otbn_otp_key_req_t otbn_otp_key_i, output otbn_otp_key_rsp_t otbn_otp_key_o, // Hardware config bits - output otp_hw_cfg_t otp_hw_cfg_o + output otp_hw_cfg_t otp_hw_cfg_o, + // External voltage for OTP + inout wire otp_ext_voltage_h_io ); import prim_util_pkg::vbits; @@ -674,7 +676,7 @@ .valid_o ( otp_rvalid ), .rdata_o ( part_otp_rdata ), .err_o ( part_otp_err ), - .ext_voltage_io ( unused_ext_voltage_io ), + .ext_voltage_io ( otp_ext_voltage_h_io ), .ext_voltage_en_i ( ext_voltage_en ), .otp_alert_po ( otp_alert_p ), .otp_alert_no ( otp_alert_n ),
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 3c77737..fb8f2ec 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -7845,15 +7845,15 @@ idx: 7 } { - name: SPI_HOST_D0 - type: BidirStd - bank: VIOA - connection: direct - desc: SPI host data + name: OTP_EXT_VOLT + type: AnalogIn0 + bank: VCC + connection: manual + desc: OTP external voltage input idx: 8 } { - name: SPI_HOST_D1 + name: SPI_HOST_D0 type: BidirStd bank: VIOA connection: direct @@ -7861,7 +7861,7 @@ idx: 9 } { - name: SPI_HOST_D2 + name: SPI_HOST_D1 type: BidirStd bank: VIOA connection: direct @@ -7869,7 +7869,7 @@ idx: 10 } { - name: SPI_HOST_D3 + name: SPI_HOST_D2 type: BidirStd bank: VIOA connection: direct @@ -7877,12 +7877,20 @@ idx: 11 } { + name: SPI_HOST_D3 + type: BidirStd + bank: VIOA + connection: direct + desc: SPI host data + idx: 12 + } + { name: SPI_HOST_CLK type: BidirStd bank: VIOA connection: direct desc: SPI host clock - idx: 12 + idx: 13 } { name: SPI_HOST_CS_L @@ -7890,7 +7898,7 @@ bank: VIOA connection: direct desc: SPI host chip select - idx: 13 + idx: 14 } { name: SPI_DEV_D0 @@ -7898,7 +7906,7 @@ bank: VIOA connection: direct desc: SPI device data - idx: 14 + idx: 15 } { name: SPI_DEV_D1 @@ -7906,7 +7914,7 @@ bank: VIOA connection: direct desc: SPI device data - idx: 15 + idx: 16 } { name: SPI_DEV_D2 @@ -7914,7 +7922,7 @@ bank: VIOA connection: direct desc: SPI device data - idx: 16 + idx: 17 } { name: SPI_DEV_D3 @@ -7922,7 +7930,7 @@ bank: VIOA connection: direct desc: SPI device data - idx: 17 + idx: 18 } { name: SPI_DEV_CLK @@ -7930,7 +7938,7 @@ bank: VIOA connection: direct desc: SPI device clock - idx: 18 + idx: 19 } { name: SPI_DEV_CS_L @@ -7938,7 +7946,7 @@ bank: VIOA connection: direct desc: SPI device chip select - idx: 19 + idx: 20 } { name: IOA0 @@ -8290,7 +8298,7 @@ bank: VCC connection: direct desc: Dedicated sysrst_ctrl output (ec_rst_l) - idx: 20 + idx: 21 } { name: IOR9 @@ -8298,7 +8306,7 @@ bank: VCC connection: direct desc: Dedicated sysrst_ctrl output (pwrb_out) - idx: 21 + idx: 22 } { name: IOR10 @@ -9817,7 +9825,7 @@ inouts: 11 inputs: 3 outputs: 10 - pads: 22 + pads: 23 } muxed: { @@ -9915,6 +9923,7 @@ SPI_HOST_D2 SPI_HOST_D3 FLASH_TEST_VOLT + OTP_EXT_VOLT FLASH_TEST_MODE0 FLASH_TEST_MODE1 IOB10
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index e211abc..91bbd90 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -448,7 +448,7 @@ clock_reset_export: ["ast"], domain: "Aon", base_addr: "0x40440000" - }, + }, { name: "pwm_aon", type: "pwm", clock_srcs: {clk_i: "io_div4", clk_core_i: "aon"}, @@ -1049,6 +1049,7 @@ { name: 'FLASH_TEST_VOLT' , type: 'AnalogIn0',bank: 'VCC' , connection: 'manual', desc: 'Flash test voltage input'}, { name: 'FLASH_TEST_MODE0', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'}, { name: 'FLASH_TEST_MODE1', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'}, + { name: 'OTP_EXT_VOLT' , type: 'AnalogIn0',bank: 'VCC' , connection: 'manual', desc: 'OTP external voltage input'}, // Dedicated IOs { name: 'SPI_HOST_D0' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'}, { name: 'SPI_HOST_D1' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'}, @@ -1289,7 +1290,7 @@ 'SPI_DEV_D2', 'SPI_DEV_D3' 'SPI_HOST_CLK', 'SPI_HOST_CS_L', 'SPI_HOST_D0', 'SPI_HOST_D1', 'SPI_HOST_D2', 'SPI_HOST_D3', - 'FLASH_TEST_VOLT', + 'FLASH_TEST_VOLT', 'OTP_EXT_VOLT' 'FLASH_TEST_MODE0', 'FLASH_TEST_MODE1', 'IOB10', 'IOB11', 'IOB12', 'IOC0', 'IOC1', 'IOC12',
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv index 198a138..c3754c1 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
@@ -19,6 +19,7 @@ inout FLASH_TEST_VOLT, // Manual Pad inout FLASH_TEST_MODE0, // Manual Pad inout FLASH_TEST_MODE1, // Manual Pad + inout OTP_EXT_VOLT, // Manual Pad inout SPI_HOST_D0, // Dedicated Pad for spi_host0_sd inout SPI_HOST_D1, // Dedicated Pad for spi_host0_sd inout SPI_HOST_D2, // Dedicated Pad for spi_host0_sd @@ -221,6 +222,7 @@ logic manual_in_flash_test_volt, manual_out_flash_test_volt, manual_oe_flash_test_volt; logic manual_in_flash_test_mode0, manual_out_flash_test_mode0, manual_oe_flash_test_mode0; logic manual_in_flash_test_mode1, manual_out_flash_test_mode1, manual_oe_flash_test_mode1; + logic manual_in_otp_ext_volt, manual_out_otp_ext_volt, manual_oe_otp_ext_volt; pad_attr_t manual_attr_por_n; pad_attr_t manual_attr_usb_p; @@ -230,6 +232,7 @@ pad_attr_t manual_attr_flash_test_volt; pad_attr_t manual_attr_flash_test_mode0; pad_attr_t manual_attr_flash_test_mode1; + pad_attr_t manual_attr_otp_ext_volt; ////////////////////// @@ -244,7 +247,7 @@ padring #( // Padring specific counts may differ from pinmux config due // to custom, stubbed or added pads. - .NDioPads(22), + .NDioPads(23), .NMioPads(47), .PhysicalPads(1), .NIoBanks(int'(IoBankCount)), @@ -263,6 +266,7 @@ scan_role_pkg::DioPadSpiHostD2ScanRole, scan_role_pkg::DioPadSpiHostD1ScanRole, scan_role_pkg::DioPadSpiHostD0ScanRole, + scan_role_pkg::DioPadOtpExtVoltScanRole, scan_role_pkg::DioPadFlashTestMode1ScanRole, scan_role_pkg::DioPadFlashTestMode0ScanRole, scan_role_pkg::DioPadFlashTestVoltScanRole, @@ -336,6 +340,7 @@ IoBankVioa, // SPI_HOST_D2 IoBankVioa, // SPI_HOST_D1 IoBankVioa, // SPI_HOST_D0 + IoBankVcc, // OTP_EXT_VOLT IoBankVcc, // FLASH_TEST_MODE1 IoBankVcc, // FLASH_TEST_MODE0 IoBankVcc, // FLASH_TEST_VOLT @@ -409,6 +414,7 @@ BidirStd, // SPI_HOST_D2 BidirStd, // SPI_HOST_D1 BidirStd, // SPI_HOST_D0 + AnalogIn0, // OTP_EXT_VOLT InputStd, // FLASH_TEST_MODE1 InputStd, // FLASH_TEST_MODE0 AnalogIn0, // FLASH_TEST_VOLT @@ -489,6 +495,7 @@ SPI_HOST_D2, SPI_HOST_D1, SPI_HOST_D0, + OTP_EXT_VOLT, FLASH_TEST_MODE1, FLASH_TEST_MODE0, FLASH_TEST_VOLT, @@ -565,6 +572,7 @@ dio_in[DioSpiHost0Sd2], dio_in[DioSpiHost0Sd1], dio_in[DioSpiHost0Sd0], + manual_in_otp_ext_volt, manual_in_flash_test_mode1, manual_in_flash_test_mode0, manual_in_flash_test_volt, @@ -589,6 +597,7 @@ dio_out[DioSpiHost0Sd2], dio_out[DioSpiHost0Sd1], dio_out[DioSpiHost0Sd0], + manual_out_otp_ext_volt, manual_out_flash_test_mode1, manual_out_flash_test_mode0, manual_out_flash_test_volt, @@ -613,6 +622,7 @@ dio_oe[DioSpiHost0Sd2], dio_oe[DioSpiHost0Sd1], dio_oe[DioSpiHost0Sd0], + manual_oe_otp_ext_volt, manual_oe_flash_test_mode1, manual_oe_flash_test_mode0, manual_oe_flash_test_volt, @@ -637,6 +647,7 @@ dio_attr[DioSpiHost0Sd2], dio_attr[DioSpiHost0Sd1], dio_attr[DioSpiHost0Sd0], + manual_attr_otp_ext_volt, manual_attr_flash_test_mode1, manual_attr_flash_test_mode0, manual_attr_flash_test_volt, @@ -675,6 +686,8 @@ assign manual_oe_flash_test_mode1 = 1'b0; assign manual_out_flash_test_volt = 1'b0; assign manual_oe_flash_test_volt = 1'b0; + assign manual_out_otp_ext_volt = 1'b0; + assign manual_oe_otp_ext_volt = 1'b0; // These pad attributes currently tied off permanently (these are all input-only pads). assign manual_attr_por_n = '0; @@ -683,6 +696,7 @@ assign manual_attr_flash_test_mode0 = '0; assign manual_attr_flash_test_mode1 = '0; assign manual_attr_flash_test_volt = '0; + assign manual_attr_otp_ext_volt = '0; logic unused_manual_sigs; assign unused_manual_sigs = ^{ @@ -690,7 +704,8 @@ manual_in_cc1, manual_in_flash_test_volt, manual_in_flash_test_mode0, - manual_in_flash_test_mode1 + manual_in_flash_test_mode1, + manual_in_otp_ext_volt }; /////////////////////////////// @@ -1128,6 +1143,9 @@ FLASH_TEST_MODE0} ), .flash_test_voltage_h_io ( FLASH_TEST_VOLT ), + // OTP external voltage + .otp_ext_voltage_h_io ( OTP_EXT_VOLT ), + // Multiplexed I/O .mio_in_i ( mio_in ), .mio_out_o ( mio_out ),
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv index b435d19..16c3ffb 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
@@ -239,63 +239,63 @@ ///////////////////////// // Only signals going to non-custom pads need to be tied off. - logic [68:0] unused_sig; + logic [69:0] unused_sig; assign dio_in[DioSpiHost0Sd0] = 1'b0; - assign unused_sig[8] = dio_out[DioSpiHost0Sd0] ^ dio_oe[DioSpiHost0Sd0]; + assign unused_sig[9] = dio_out[DioSpiHost0Sd0] ^ dio_oe[DioSpiHost0Sd0]; assign dio_in[DioSpiHost0Sd1] = 1'b0; - assign unused_sig[9] = dio_out[DioSpiHost0Sd1] ^ dio_oe[DioSpiHost0Sd1]; + assign unused_sig[10] = dio_out[DioSpiHost0Sd1] ^ dio_oe[DioSpiHost0Sd1]; assign dio_in[DioSpiHost0Sd2] = 1'b0; - assign unused_sig[10] = dio_out[DioSpiHost0Sd2] ^ dio_oe[DioSpiHost0Sd2]; + assign unused_sig[11] = dio_out[DioSpiHost0Sd2] ^ dio_oe[DioSpiHost0Sd2]; assign dio_in[DioSpiHost0Sd3] = 1'b0; - assign unused_sig[11] = dio_out[DioSpiHost0Sd3] ^ dio_oe[DioSpiHost0Sd3]; + assign unused_sig[12] = dio_out[DioSpiHost0Sd3] ^ dio_oe[DioSpiHost0Sd3]; assign dio_in[DioSpiHost0Sck] = 1'b0; - assign unused_sig[12] = dio_out[DioSpiHost0Sck] ^ dio_oe[DioSpiHost0Sck]; + assign unused_sig[13] = dio_out[DioSpiHost0Sck] ^ dio_oe[DioSpiHost0Sck]; assign dio_in[DioSpiHost0Csb] = 1'b0; - assign unused_sig[13] = dio_out[DioSpiHost0Csb] ^ dio_oe[DioSpiHost0Csb]; + assign unused_sig[14] = dio_out[DioSpiHost0Csb] ^ dio_oe[DioSpiHost0Csb]; assign dio_in[DioSpiDeviceSd2] = 1'b0; - assign unused_sig[16] = dio_out[DioSpiDeviceSd2] ^ dio_oe[DioSpiDeviceSd2]; + assign unused_sig[17] = dio_out[DioSpiDeviceSd2] ^ dio_oe[DioSpiDeviceSd2]; assign dio_in[DioSpiDeviceSd3] = 1'b0; - assign unused_sig[17] = dio_out[DioSpiDeviceSd3] ^ dio_oe[DioSpiDeviceSd3]; + assign unused_sig[18] = dio_out[DioSpiDeviceSd3] ^ dio_oe[DioSpiDeviceSd3]; assign mio_in[19] = 1'b0; - assign unused_sig[39] = mio_out[19] ^ mio_oe[19]; + assign unused_sig[40] = mio_out[19] ^ mio_oe[19]; assign mio_in[20] = 1'b0; - assign unused_sig[40] = mio_out[20] ^ mio_oe[20]; + assign unused_sig[41] = mio_out[20] ^ mio_oe[20]; assign mio_in[21] = 1'b0; - assign unused_sig[41] = mio_out[21] ^ mio_oe[21]; + assign unused_sig[42] = mio_out[21] ^ mio_oe[21]; assign mio_in[22] = 1'b0; - assign unused_sig[42] = mio_out[22] ^ mio_oe[22]; + assign unused_sig[43] = mio_out[22] ^ mio_oe[22]; assign mio_in[23] = 1'b0; - assign unused_sig[43] = mio_out[23] ^ mio_oe[23]; + assign unused_sig[44] = mio_out[23] ^ mio_oe[23]; assign mio_in[34] = 1'b0; - assign unused_sig[54] = mio_out[34] ^ mio_oe[34]; + assign unused_sig[55] = mio_out[34] ^ mio_oe[34]; assign mio_in[35] = 1'b0; - assign unused_sig[55] = mio_out[35] ^ mio_oe[35]; + assign unused_sig[56] = mio_out[35] ^ mio_oe[35]; assign mio_in[36] = 1'b0; - assign unused_sig[56] = mio_out[36] ^ mio_oe[36]; + assign unused_sig[57] = mio_out[36] ^ mio_oe[36]; assign mio_in[37] = 1'b0; - assign unused_sig[57] = mio_out[37] ^ mio_oe[37]; + assign unused_sig[58] = mio_out[37] ^ mio_oe[37]; assign mio_in[38] = 1'b0; - assign unused_sig[58] = mio_out[38] ^ mio_oe[38]; + assign unused_sig[59] = mio_out[38] ^ mio_oe[38]; assign mio_in[39] = 1'b0; - assign unused_sig[59] = mio_out[39] ^ mio_oe[39]; + assign unused_sig[60] = mio_out[39] ^ mio_oe[39]; assign mio_in[40] = 1'b0; - assign unused_sig[60] = mio_out[40] ^ mio_oe[40]; + assign unused_sig[61] = mio_out[40] ^ mio_oe[40]; assign mio_in[41] = 1'b0; - assign unused_sig[61] = mio_out[41] ^ mio_oe[41]; + assign unused_sig[62] = mio_out[41] ^ mio_oe[41]; assign mio_in[42] = 1'b0; - assign unused_sig[62] = mio_out[42] ^ mio_oe[42]; + assign unused_sig[63] = mio_out[42] ^ mio_oe[42]; assign dio_in[DioSysrstCtrlAonEcRstOutL] = 1'b0; - assign unused_sig[63] = dio_out[DioSysrstCtrlAonEcRstOutL] ^ dio_oe[DioSysrstCtrlAonEcRstOutL]; + assign unused_sig[64] = dio_out[DioSysrstCtrlAonEcRstOutL] ^ dio_oe[DioSysrstCtrlAonEcRstOutL]; assign dio_in[DioSysrstCtrlAonPwrbOut] = 1'b0; - assign unused_sig[64] = dio_out[DioSysrstCtrlAonPwrbOut] ^ dio_oe[DioSysrstCtrlAonPwrbOut]; + assign unused_sig[65] = dio_out[DioSysrstCtrlAonPwrbOut] ^ dio_oe[DioSysrstCtrlAonPwrbOut]; assign mio_in[43] = 1'b0; - assign unused_sig[65] = mio_out[43] ^ mio_oe[43]; + assign unused_sig[66] = mio_out[43] ^ mio_oe[43]; assign mio_in[44] = 1'b0; - assign unused_sig[66] = mio_out[44] ^ mio_oe[44]; + assign unused_sig[67] = mio_out[44] ^ mio_oe[44]; assign mio_in[45] = 1'b0; - assign unused_sig[67] = mio_out[45] ^ mio_oe[45]; + assign unused_sig[68] = mio_out[45] ^ mio_oe[45]; assign mio_in[46] = 1'b0; - assign unused_sig[68] = mio_out[46] ^ mio_oe[46]; + assign unused_sig[69] = mio_out[46] ^ mio_oe[46]; ////////////////////// // Padring Instance //
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 9dcdd29..6ca7506 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -91,6 +91,9 @@ inout [1:0] flash_test_mode_a_io, inout flash_test_voltage_h_io, + // OTP specific voltages + inout otp_ext_voltage_h_io, + input scan_rst_ni, // reset used for test mode input scan_en_i, input lc_ctrl_pkg::lc_tx_t scanmode_i // lc_ctrl_pkg::On for Scan @@ -1499,6 +1502,7 @@ .otp_hw_cfg_o(otp_ctrl_otp_hw_cfg), .tl_i(otp_ctrl_tl_req), .tl_o(otp_ctrl_tl_rsp), + .otp_ext_voltage_h_io, // Clock and reset connections .clk_i (clkmgr_aon_clocks.clk_io_div4_timers),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv index eaad56c..2984b72 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -709,20 +709,21 @@ DioPadFlashTestVolt = 5, DioPadFlashTestMode0 = 6, DioPadFlashTestMode1 = 7, - DioPadSpiHostD0 = 8, - DioPadSpiHostD1 = 9, - DioPadSpiHostD2 = 10, - DioPadSpiHostD3 = 11, - DioPadSpiHostClk = 12, - DioPadSpiHostCsL = 13, - DioPadSpiDevD0 = 14, - DioPadSpiDevD1 = 15, - DioPadSpiDevD2 = 16, - DioPadSpiDevD3 = 17, - DioPadSpiDevClk = 18, - DioPadSpiDevCsL = 19, - DioPadIor8 = 20, - DioPadIor9 = 21, + DioPadOtpExtVolt = 8, + DioPadSpiHostD0 = 9, + DioPadSpiHostD1 = 10, + DioPadSpiHostD2 = 11, + DioPadSpiHostD3 = 12, + DioPadSpiHostClk = 13, + DioPadSpiHostCsL = 14, + DioPadSpiDevD0 = 15, + DioPadSpiDevD1 = 16, + DioPadSpiDevD2 = 17, + DioPadSpiDevD3 = 18, + DioPadSpiDevClk = 19, + DioPadSpiDevCsL = 20, + DioPadIor8 = 21, + DioPadIor9 = 22, DioPadCount } dio_pad_e;
diff --git a/hw/top_earlgrey/rtl/scan_role_pkg.sv b/hw/top_earlgrey/rtl/scan_role_pkg.sv index 1e9246a..4a4c656 100644 --- a/hw/top_earlgrey/rtl/scan_role_pkg.sv +++ b/hw/top_earlgrey/rtl/scan_role_pkg.sv
@@ -29,6 +29,7 @@ parameter scan_role_e DioPadFlashTestVoltScanRole = NoScan; parameter scan_role_e DioPadFlashTestMode0ScanRole = NoScan; parameter scan_role_e DioPadFlashTestMode1ScanRole = NoScan; + parameter scan_role_e DioPadOtpExtVoltScanRole = NoScan; parameter scan_role_e DioPadIor8ScanRole = NoScan; parameter scan_role_e DioPadIor9ScanRole = NoScan; parameter scan_role_e MioPadIoa0ScanRole = NoScan;
diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl index a82209c..c7df92e 100644 --- a/util/topgen/templates/chiplevel.sv.tpl +++ b/util/topgen/templates/chiplevel.sv.tpl
@@ -540,6 +540,8 @@ assign manual_oe_flash_test_mode1 = 1'b0; assign manual_out_flash_test_volt = 1'b0; assign manual_oe_flash_test_volt = 1'b0; + assign manual_out_otp_ext_volt = 1'b0; + assign manual_oe_otp_ext_volt = 1'b0; // These pad attributes currently tied off permanently (these are all input-only pads). assign manual_attr_por_n = '0; @@ -548,6 +550,7 @@ assign manual_attr_flash_test_mode0 = '0; assign manual_attr_flash_test_mode1 = '0; assign manual_attr_flash_test_volt = '0; + assign manual_attr_otp_ext_volt = '0; logic unused_manual_sigs; assign unused_manual_sigs = ^{ @@ -555,7 +558,8 @@ manual_in_cc1, manual_in_flash_test_volt, manual_in_flash_test_mode0, - manual_in_flash_test_mode1 + manual_in_flash_test_mode1, + manual_in_otp_ext_volt }; /////////////////////////////// @@ -993,6 +997,9 @@ FLASH_TEST_MODE0} ), .flash_test_voltage_h_io ( FLASH_TEST_VOLT ), + // OTP external voltage + .otp_ext_voltage_h_io ( OTP_EXT_VOLT ), + // Multiplexed I/O .mio_in_i ( mio_in ), .mio_out_o ( mio_out ),
diff --git a/util/topgen/templates/toplevel.sv.tpl b/util/topgen/templates/toplevel.sv.tpl index 636ef1e..dd9ca06 100644 --- a/util/topgen/templates/toplevel.sv.tpl +++ b/util/topgen/templates/toplevel.sv.tpl
@@ -94,6 +94,9 @@ inout [1:0] flash_test_mode_a_io, inout flash_test_voltage_h_io, + // OTP specific voltages + inout otp_ext_voltage_h_io, + % endif input scan_rst_ni, // reset used for test mode input scan_en_i, @@ -694,6 +697,9 @@ .alert_rx_o ( alert_rx ), .alert_tx_i ( alert_tx ), % endif + % if m["type"] == "otp_ctrl": + .otp_ext_voltage_h_io, + % endif % if block.scan: .scanmode_i, % endif