| commit | cbc9335ca1d5ad119a46be5ecc32cb5dc21180aa | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Fri Mar 25 14:39:24 2022 +0000 |
| committer | Michael Schaffner <msf@google.com> | Fri Mar 25 13:49:57 2022 -0700 |
| tree | 6d5e59cf1054830a3744e9d7ab29a4633db7a3aa | |
| parent | 3cfdcc05cfda247d2d5c5f801d0f14f02564e3e6 [diff] |
[prim] Fix a bunch of Verilator lint errors in prim_packer.sv These are all to do with width conversion. Almost all of the changes are just putting explicit widening casts where Verilog was doing it implicitly before. The one awkward place was the expression used to compute shiftl_data / shiftl_mask. The eventual size was wrong (should be ConcatW, not Width). But it's also a bit difficult to cast shifts and the resulting expression was rather noisy, so I've split the expression into two stages, which seems to tidy things up nicely. As a plus, this also gives us a place to add a comment to document the step in the computation. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> Signed-off-by: Michael Schaffner <msf@opentitan.org>
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