)]}'
{
  "commit": "cbc9335ca1d5ad119a46be5ecc32cb5dc21180aa",
  "tree": "6d5e59cf1054830a3744e9d7ab29a4633db7a3aa",
  "parents": [
    "3cfdcc05cfda247d2d5c5f801d0f14f02564e3e6"
  ],
  "author": {
    "name": "Rupert Swarbrick",
    "email": "rswarbrick@lowrisc.org",
    "time": "Fri Mar 25 14:39:24 2022 +0000"
  },
  "committer": {
    "name": "Michael Schaffner",
    "email": "msf@google.com",
    "time": "Fri Mar 25 13:49:57 2022 -0700"
  },
  "message": "[prim] Fix a bunch of Verilator lint errors in prim_packer.sv\n\nThese are all to do with width conversion. Almost all of the changes\nare just putting explicit widening casts where Verilog was doing it\nimplicitly before.\n\nThe one awkward place was the expression used to compute shiftl_data /\nshiftl_mask. The eventual size was wrong (should be ConcatW, not\nWidth). But it\u0027s also a bit difficult to cast shifts and the resulting\nexpression was rather noisy, so I\u0027ve split the expression into two\nstages, which seems to tidy things up nicely. As a plus, this also\ngives us a place to add a comment to document the step in the\ncomputation.\n\nSigned-off-by: Rupert Swarbrick \u003crswarbrick@lowrisc.org\u003e\nSigned-off-by: Michael Schaffner \u003cmsf@opentitan.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c278a39ee1d5549ab154437e5304c90e0fcdeeb1",
      "old_mode": 33188,
      "old_path": "hw/ip/prim/rtl/prim_packer.sv",
      "new_id": "b98d8e81af6cdd6c4e817794676e14f081d8619f",
      "new_mode": 33188,
      "new_path": "hw/ip/prim/rtl/prim_packer.sv"
    }
  ]
}