Google Git
Sign in
opensecura / 3p / lowrisc / opentitan / cb3585cb984eca2a445782f83a2970e242848510 / . / hw / vendor / pulp_riscv_dbg / tb
tree: 38acbad28ddad1be54a2e892ecf8b57bffab4246 [path history] [tgz]
  1. jtag_dmi/
  2. prog/
  3. remote_bitbang/
  4. unused/
  5. .gitignore
  6. boot_rom.sv
  7. dm_compliance_test.cfg
  8. dm_debug.cfg
  9. dm_tb_pkg.sv
  10. dp_ram.sv
  11. LICENSE.Berkeley
  12. LICENSE.SiFive
  13. Makefile
  14. mm_ram.sv
  15. README.md
  16. SimJTAG.sv
  17. tb_test_env.sv
  18. tb_top.sv
  19. tb_top_verilator.cpp
  20. tb_top_verilator.sv
  21. veri-run-openocd.py
  22. vsim_batch.tcl
  23. vsim_gui.tcl
  24. waves.tcl
hw/vendor/pulp_riscv_dbg/tb/README.md

Debug Unit plus RI5CY Testbench

This testbench tests RI5CY together with a v0.13.1 compliant debug unit. There are several tests that can be run, but for now it is just riscv test_compliance of riscv-openocd (see in pulpissimo.cfg) and a not yet scripted run of gdb connecting to openocd, loading and running a hello world program (see prog/test.c).

You need riscv-openocd.

Running the testbench with vsim

Point you environment variable RISCV to your RISC-V toolchain. Call make vsim-run to build the testbench and the program, and run it with vsim. Use VSIM_FLAGS to configure the simulator e.g. make vsim-run VSIM_FLAGS="-gui -debugdb".

Running the testbench with vcs

Point you environment variable RISCV to your RISC-V toolchain. Call make vcs-run. Use VCS_FLAGS and SIMV_FLAGS to configure vcs e.g. make vcs-run VCS_FLAGS="-debug_all".

Running the testbench with verilator

Point you environment variable RISCV to your RISC-V toolchain. Call make veri-run. Use VERI_FLAGS to configure verilator e.g. make firmware-veri-run VERI_FLAGS="+firmware=path_to_firmware +vcd" to use a custom firmware and dump to a vcd file.

Options

A few plusarg options are supported.

  • +verbose to show all memory read and writes and other miscellaneous information.

  • +vcd to produce a vcd file called riscy_tb.vcd. Verilator always produces a vcd file called verilator_tb.vcd.

  • +firmware=path_to_firmware to load a specific firmware. It is a bit tricky to build and link your own program. Look into the prog folder for an example.

Example Run

  1. make veri-run
  2. (in new terminal) export JTAG_VPI_PORT=port_name_from 1.
  3. (in new terminal) openocd -f dm_compliance_test.cfg
  4. Now you can connect with gdb and interact with the testbench