| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// |
| // PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: |
| // |
| // util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson \ |
| // -o hw/top_earlgrey/ \ |
| // --hjson-only \ |
| // --rnd_cnst_seed 4881560218908238235 |
| { |
| name: earlgrey |
| type: top |
| rnd_cnst_seed: 4881560218908238235 |
| datawidth: "32" |
| power: |
| { |
| domains: |
| [ |
| Aon |
| "0" |
| ] |
| default: "0" |
| } |
| clocks: |
| { |
| hier_paths: |
| { |
| top: clkmgr_aon_clocks. |
| ext: "" |
| lpg: clkmgr_aon_cg_en. |
| } |
| srcs: |
| [ |
| { |
| name: main |
| aon: no |
| freq: "100000000" |
| ref: false |
| } |
| { |
| name: io |
| aon: no |
| freq: "96000000" |
| ref: false |
| } |
| { |
| name: usb |
| aon: no |
| freq: "48000000" |
| ref: false |
| } |
| { |
| name: aon |
| aon: yes |
| freq: "200000" |
| ref: true |
| } |
| ] |
| derived_srcs: |
| [ |
| { |
| name: io_div2 |
| aon: no |
| freq: "48000000" |
| ref: false |
| div: "2" |
| src: io |
| } |
| { |
| name: io_div4 |
| aon: no |
| freq: "24000000" |
| ref: false |
| div: "4" |
| src: io |
| } |
| ] |
| groups: |
| [ |
| { |
| name: ast |
| src: ext |
| sw_cg: no |
| unique: no |
| clocks: |
| { |
| clk_main_i: main |
| clk_io_i: io |
| clk_usb_i: usb |
| clk_aon_i: aon |
| } |
| } |
| { |
| name: powerup |
| src: top |
| sw_cg: no |
| unique: no |
| clocks: |
| { |
| clk_io_div4_powerup: io_div4 |
| clk_aon_powerup: aon |
| clk_main_powerup: main |
| clk_io_powerup: io |
| clk_usb_powerup: usb |
| clk_io_div2_powerup: io_div2 |
| } |
| } |
| { |
| name: trans |
| src: top |
| sw_cg: hint |
| unique: yes |
| clocks: |
| { |
| clk_main_aes: main |
| clk_main_hmac: main |
| clk_main_kmac: main |
| clk_main_otbn: main |
| } |
| } |
| { |
| name: infra |
| src: top |
| sw_cg: no |
| unique: no |
| clocks: |
| { |
| clk_io_div4_infra: io_div4 |
| clk_main_infra: main |
| clk_usb_infra: usb |
| clk_io_infra: io |
| clk_io_div2_infra: io_div2 |
| } |
| } |
| { |
| name: secure |
| src: top |
| sw_cg: no |
| unique: no |
| clocks: |
| { |
| clk_io_div4_secure: io_div4 |
| clk_main_secure: main |
| clk_aon_secure: aon |
| } |
| } |
| { |
| name: peri |
| src: top |
| sw_cg: yes |
| unique: no |
| clocks: |
| { |
| clk_io_div4_peri: io_div4 |
| clk_io_div2_peri: io_div2 |
| clk_io_peri: io |
| clk_usb_peri: usb |
| clk_aon_peri: aon |
| } |
| } |
| { |
| name: timers |
| src: top |
| sw_cg: no |
| unique: no |
| clocks: |
| { |
| clk_io_div4_timers: io_div4 |
| clk_aon_timers: aon |
| } |
| } |
| ] |
| } |
| resets: |
| { |
| hier_paths: |
| { |
| top: rstmgr_aon_resets. |
| ext: "" |
| lpg: rstmgr_aon_rst_en. |
| } |
| nodes: |
| [ |
| { |
| name: por_aon |
| gen: false |
| type: top |
| domains: |
| [ |
| "0" |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_por_aon_n |
| clock: aon |
| } |
| { |
| name: lc_src |
| gen: false |
| type: int |
| domains: [] |
| shadowed: false |
| sw: false |
| path: "" |
| clock: io_div4 |
| } |
| { |
| name: sys_src |
| gen: false |
| type: int |
| domains: [] |
| shadowed: false |
| sw: false |
| path: "" |
| clock: io_div4 |
| } |
| { |
| name: por |
| gen: true |
| type: top |
| domains: |
| [ |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_por_n |
| parent: por_aon |
| clock: main |
| } |
| { |
| name: por_io |
| gen: true |
| type: top |
| domains: |
| [ |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_por_io_n |
| parent: por_aon |
| clock: io |
| } |
| { |
| name: por_io_div2 |
| gen: true |
| type: top |
| domains: |
| [ |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_por_io_div2_n |
| parent: por_aon |
| clock: io_div2 |
| } |
| { |
| name: por_io_div4 |
| gen: true |
| type: top |
| domains: |
| [ |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_por_io_div4_n |
| parent: por_aon |
| clock: io_div4 |
| } |
| { |
| name: por_usb |
| gen: true |
| type: top |
| domains: |
| [ |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_por_usb_n |
| parent: por_aon |
| clock: usb |
| } |
| { |
| name: lc |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| Aon |
| ] |
| shadowed: true |
| sw: false |
| path: rstmgr_aon_resets.rst_lc_n |
| parent: lc_src |
| clock: main |
| } |
| { |
| name: lc_aon |
| gen: true |
| type: top |
| domains: |
| [ |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_lc_aon_n |
| parent: lc_src |
| clock: aon |
| } |
| { |
| name: lc_io |
| gen: true |
| type: top |
| domains: |
| [ |
| Aon |
| "0" |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_lc_io_n |
| parent: lc_src |
| clock: io |
| } |
| { |
| name: lc_io_div2 |
| gen: true |
| type: top |
| domains: |
| [ |
| Aon |
| "0" |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_lc_io_div2_n |
| parent: lc_src |
| clock: io_div2 |
| } |
| { |
| name: lc_io_div4 |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| Aon |
| ] |
| shadowed: true |
| sw: false |
| path: rstmgr_aon_resets.rst_lc_io_div4_n |
| parent: lc_src |
| clock: io_div4 |
| } |
| { |
| name: lc_usb |
| gen: true |
| type: top |
| domains: |
| [ |
| Aon |
| "0" |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_lc_usb_n |
| parent: lc_src |
| clock: usb |
| } |
| { |
| name: sys |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_sys_n |
| parent: sys_src |
| clock: main |
| } |
| { |
| name: sys_io_div4 |
| gen: true |
| type: top |
| domains: |
| [ |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_sys_io_div4_n |
| parent: sys_src |
| clock: io_div4 |
| } |
| { |
| name: spi_device |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: true |
| path: rstmgr_aon_resets.rst_spi_device_n |
| parent: lc_src |
| clock: io_div4 |
| } |
| { |
| name: spi_host0 |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: true |
| path: rstmgr_aon_resets.rst_spi_host0_n |
| parent: lc_src |
| clock: io |
| } |
| { |
| name: spi_host1 |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: true |
| path: rstmgr_aon_resets.rst_spi_host1_n |
| parent: lc_src |
| clock: io_div2 |
| } |
| { |
| name: usb |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: true |
| path: rstmgr_aon_resets.rst_usb_n |
| parent: lc_src |
| clock: usb |
| } |
| { |
| name: usb_aon |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: true |
| path: rstmgr_aon_resets.rst_usb_aon_n |
| parent: lc_src |
| clock: aon |
| } |
| { |
| name: i2c0 |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: true |
| path: rstmgr_aon_resets.rst_i2c0_n |
| parent: lc_src |
| clock: io_div4 |
| } |
| { |
| name: i2c1 |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: true |
| path: rstmgr_aon_resets.rst_i2c1_n |
| parent: lc_src |
| clock: io_div4 |
| } |
| { |
| name: i2c2 |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: true |
| path: rstmgr_aon_resets.rst_i2c2_n |
| parent: lc_src |
| clock: io_div4 |
| } |
| ] |
| } |
| num_cores: "1" |
| module: |
| [ |
| { |
| name: uart0 |
| type: uart |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: "0" |
| } |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| } |
| domain: |
| [ |
| "0" |
| ] |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: uart0 |
| default: "" |
| end_idx: -1 |
| top_signame: uart0_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40000000 |
| } |
| } |
| { |
| name: uart1 |
| type: uart |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: "0" |
| } |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| } |
| domain: |
| [ |
| "0" |
| ] |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: uart1 |
| default: "" |
| end_idx: -1 |
| top_signame: uart1_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40010000 |
| } |
| } |
| { |
| name: uart2 |
| type: uart |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: "0" |
| } |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| } |
| domain: |
| [ |
| "0" |
| ] |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: uart2 |
| default: "" |
| end_idx: -1 |
| top_signame: uart2_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40020000 |
| } |
| } |
| { |
| name: uart3 |
| type: uart |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: "0" |
| } |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| } |
| domain: |
| [ |
| "0" |
| ] |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: uart3 |
| default: "" |
| end_idx: -1 |
| top_signame: uart3_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40030000 |
| } |
| } |
| { |
| name: gpio |
| type: gpio |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: "0" |
| } |
| } |
| param_decl: |
| { |
| GpioAsyncOn: "1" |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| } |
| domain: |
| [ |
| "0" |
| ] |
| memory: {} |
| param_list: |
| [ |
| { |
| name: GpioAsyncOn |
| desc: Instantiates 2-flop synchronizers on all GPIO inputs if set to 1. |
| type: bit |
| default: "1" |
| expose: "true" |
| name_top: GpioGpioAsyncOn |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: gpio |
| default: "" |
| end_idx: -1 |
| top_signame: gpio_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40040000 |
| } |
| } |
| { |
| name: spi_device |
| type: spi_device |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| scan_clk_i: io_div2 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: spi_device |
| domain: "0" |
| } |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| scan_clk_i: clkmgr_aon_clocks.clk_io_div2_peri |
| } |
| domain: |
| [ |
| "0" |
| ] |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: ram_cfg |
| struct: ram_2p_cfg |
| package: prim_ram_2p_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: spi_device |
| default: "" |
| top_signame: ast_ram_2p_cfg |
| index: -1 |
| } |
| { |
| name: passthrough |
| struct: passthrough |
| package: spi_device_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: spi_device |
| default: "" |
| end_idx: -1 |
| top_signame: spi_device_passthrough |
| index: -1 |
| } |
| { |
| name: mbist_en |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: spi_device |
| index: -1 |
| } |
| { |
| name: sck_monitor |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: spi_device |
| default: "" |
| package: "" |
| external: true |
| top_signame: sck_monitor |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: spi_device |
| default: "" |
| end_idx: -1 |
| top_signame: spi_device_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40050000 |
| } |
| } |
| { |
| name: i2c0 |
| type: i2c |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: i2c0 |
| domain: "0" |
| } |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| } |
| domain: |
| [ |
| "0" |
| ] |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: i2c0 |
| default: "" |
| end_idx: -1 |
| top_signame: i2c0_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40080000 |
| } |
| } |
| { |
| name: i2c1 |
| type: i2c |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: i2c1 |
| domain: "0" |
| } |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| } |
| domain: |
| [ |
| "0" |
| ] |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: i2c1 |
| default: "" |
| end_idx: -1 |
| top_signame: i2c1_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40090000 |
| } |
| } |
| { |
| name: i2c2 |
| type: i2c |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: i2c2 |
| domain: "0" |
| } |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| } |
| domain: |
| [ |
| "0" |
| ] |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: i2c2 |
| default: "" |
| end_idx: -1 |
| top_signame: i2c2_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x400A0000 |
| } |
| } |
| { |
| name: pattgen |
| type: pattgen |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: "0" |
| } |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| } |
| domain: |
| [ |
| "0" |
| ] |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: pattgen |
| default: "" |
| end_idx: -1 |
| top_signame: pattgen_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x400E0000 |
| } |
| } |
| { |
| name: rv_timer |
| type: rv_timer |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: timers |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: "0" |
| } |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_timers |
| } |
| domain: |
| [ |
| "0" |
| ] |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rv_timer |
| default: "" |
| end_idx: -1 |
| top_signame: rv_timer_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40100000 |
| } |
| } |
| { |
| name: otp_ctrl |
| type: otp_ctrl |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_edn_i: main |
| } |
| clock_group: secure |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: "0" |
| } |
| rst_edn_ni: |
| { |
| name: lc |
| domain: "0" |
| } |
| } |
| base_addrs: |
| { |
| core: 0x40130000 |
| prim: 0x40132000 |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_secure |
| clk_edn_i: clkmgr_aon_clocks.clk_main_secure |
| } |
| domain: |
| [ |
| "0" |
| ] |
| param_decl: {} |
| memory: {} |
| param_list: |
| [ |
| { |
| name: MemInitFile |
| desc: VMEM file to initialize the OTP macro. |
| type: "" |
| default: '''""''' |
| expose: "true" |
| name_top: OtpCtrlMemInitFile |
| } |
| { |
| name: RndCnstLfsrSeed |
| desc: Compile-time random bits for initial LFSR seed |
| type: otp_ctrl_pkg::lfsr_seed_t |
| randcount: 40 |
| randtype: data |
| name_top: RndCnstOtpCtrlLfsrSeed |
| default: 0xcb0157a3ac |
| randwidth: 40 |
| } |
| { |
| name: RndCnstLfsrPerm |
| desc: Compile-time random permutation for LFSR output |
| type: otp_ctrl_pkg::lfsr_perm_t |
| randcount: 40 |
| randtype: perm |
| name_top: RndCnstOtpCtrlLfsrPerm |
| default: 0x3946df8032263d64e474a1a110541e61a55770d0a33110222592c19479d2 |
| randwidth: 240 |
| } |
| { |
| name: RndCnstScrmblKeyInit |
| desc: Compile-time random permutation for scrambling key/nonce register reset value |
| type: otp_ctrl_pkg::scrmbl_key_init_t |
| randcount: 256 |
| randtype: data |
| name_top: RndCnstOtpCtrlScrmblKeyInit |
| default: 0x605fefe9977b00b6fdc21d577a172d047dcf0eebbdd268afd4e2506df1d0603f |
| randwidth: 256 |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: otp_ext_voltage_h |
| struct: "" |
| type: io |
| act: none |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| package: "" |
| external: true |
| top_signame: otp_ext_voltage_h |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: otp_ast_pwr_seq |
| desc: Power sequencing signals to AST (VDD domain). |
| struct: otp_ast_req |
| package: otp_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| external: true |
| top_signame: otp_ctrl_otp_ast_pwr_seq |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: otp_ast_pwr_seq_h |
| desc: Power sequencing signals coming from AST (VCC domain). |
| struct: otp_ast_rsp |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| external: true |
| top_signame: otp_ctrl_otp_ast_pwr_seq_h |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: edn |
| desc: Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation. |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: otp_ctrl |
| default: "" |
| top_signame: edn0_edn |
| index: 1 |
| } |
| { |
| name: pwr_otp |
| desc: Initialization request/acknowledge from/to power manager. |
| struct: pwr_otp |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| top_signame: pwrmgr_aon_pwr_otp |
| index: -1 |
| } |
| { |
| name: lc_otp_vendor_test |
| desc: Vendor test control signals from/to the life cycle TAP. |
| struct: lc_otp_vendor_test |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_otp_vendor_test |
| index: -1 |
| } |
| { |
| name: lc_otp_program |
| desc: Life cycle state transition interface. |
| struct: lc_otp_program |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_otp_program |
| index: -1 |
| } |
| { |
| name: otp_lc_data |
| desc: |
| ''' |
| Life cycle state output holding the current life cycle state, |
| the value of the transition counter and the tokens needed for life cycle transitions. |
| ''' |
| struct: otp_lc_data |
| package: otp_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: otp_ctrl_otp_lc_data |
| index: -1 |
| } |
| { |
| name: lc_escalate_en |
| desc: |
| ''' |
| Life cycle escalation enable coming from life cycle controller. |
| This signal moves all FSMs within OTP into the error state. |
| ''' |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: lc_creator_seed_sw_rw_en |
| desc: |
| ''' |
| Provision enable qualifier coming from life cycle controller. |
| This signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. |
| ''' |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_creator_seed_sw_rw_en |
| index: -1 |
| } |
| { |
| name: lc_seed_hw_rd_en |
| desc: |
| ''' |
| Seed read enable coming from life cycle controller. |
| This signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. |
| ''' |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_seed_hw_rd_en |
| index: -1 |
| } |
| { |
| name: lc_dft_en |
| desc: |
| ''' |
| Test enable qualifier coming from from life cycle controller. |
| This signals enables the TL-UL access port to the proprietary OTP IP. |
| ''' |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_dft_en |
| index: -1 |
| } |
| { |
| name: lc_check_byp_en |
| desc: |
| ''' |
| Life cycle partition check bypass signal. |
| This signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures. |
| ''' |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_check_byp_en |
| index: -1 |
| } |
| { |
| name: otp_keymgr_key |
| desc: Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. |
| struct: otp_keymgr_key |
| package: otp_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: otp_ctrl_otp_keymgr_key |
| index: -1 |
| } |
| { |
| name: flash_otp_key |
| desc: Key derivation interface for FLASH scrambling. |
| struct: flash_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| top_signame: flash_ctrl_otp |
| index: -1 |
| } |
| { |
| name: sram_otp_key |
| desc: Array with key derivation interfaces for SRAM scrambling devices. |
| struct: sram_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: rsp |
| width: 3 |
| default: "'0" |
| inst_name: otp_ctrl |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: otp_ctrl_sram_otp_key |
| index: -1 |
| } |
| { |
| name: otbn_otp_key |
| desc: Key derivation interface for OTBN scrambling devices. |
| struct: otbn_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| end_idx: -1 |
| top_signame: otp_ctrl_otbn_otp_key |
| index: -1 |
| } |
| { |
| name: otp_hw_cfg |
| desc: Output of the HW_CFG partition. |
| struct: otp_hw_cfg |
| package: otp_ctrl_part_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| top_signame: otp_ctrl_otp_hw_cfg |
| index: -1 |
| } |
| { |
| name: obs_ctrl |
| desc: AST observability control signals. |
| struct: ast_obs_ctrl |
| package: ast_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: otp_ctrl |
| default: "" |
| top_signame: ast_obs_ctrl |
| index: -1 |
| } |
| { |
| name: otp_obs |
| desc: AST observability bus. |
| struct: logic |
| type: uni |
| act: req |
| width: 8 |
| inst_name: otp_ctrl |
| default: "" |
| package: "" |
| external: true |
| top_signame: otp_obs |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: core_tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: otp_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: otp_ctrl_core_tl |
| index: -1 |
| } |
| { |
| name: prim_tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: otp_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: otp_ctrl_prim_tl |
| index: -1 |
| } |
| ] |
| } |
| { |
| name: lc_ctrl |
| type: lc_ctrl |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_kmac_i: main |
| } |
| clock_group: secure |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: "0" |
| } |
| rst_kmac_ni: |
| { |
| name: lc |
| domain: "0" |
| } |
| } |
| param_decl: |
| { |
| ChipGen: 16'h 0000 |
| ChipRev: 16'h 0000 |
| IdcodeValue: jtag_id_pkg::JTAG_IDCODE |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_secure |
| clk_kmac_i: clkmgr_aon_clocks.clk_main_secure |
| } |
| domain: |
| [ |
| "0" |
| ] |
| memory: {} |
| param_list: |
| [ |
| { |
| name: RndCnstLcKeymgrDivInvalid |
| desc: Compile-time random bits for lc state group diversification value |
| type: lc_ctrl_pkg::lc_keymgr_div_t |
| randcount: 128 |
| randtype: data |
| name_top: RndCnstLcCtrlLcKeymgrDivInvalid |
| default: 0x9cd62f178adc74d53d8ad0b600e7a1dd |
| randwidth: 128 |
| } |
| { |
| name: RndCnstLcKeymgrDivTestDevRma |
| desc: Compile-time random bits for lc state group diversification value |
| type: lc_ctrl_pkg::lc_keymgr_div_t |
| randcount: 128 |
| randtype: data |
| name_top: RndCnstLcCtrlLcKeymgrDivTestDevRma |
| default: 0x2f1a43c03dd4ff9b887ab7521ca6cbd8 |
| randwidth: 128 |
| } |
| { |
| name: RndCnstLcKeymgrDivProduction |
| desc: Compile-time random bits for lc state group diversification value |
| type: lc_ctrl_pkg::lc_keymgr_div_t |
| randcount: 128 |
| randtype: data |
| name_top: RndCnstLcCtrlLcKeymgrDivProduction |
| default: 0xd7107bab98b075743f7aeba81e1c4ec8 |
| randwidth: 128 |
| } |
| { |
| name: RndCnstInvalidTokens |
| desc: Compile-time random bits used for invalid tokens in the token mux |
| type: lc_ctrl_pkg::lc_token_mux_t |
| randcount: 1024 |
| randtype: data |
| name_top: RndCnstLcCtrlInvalidTokens |
| default: 0xebdeee2911062e039f8c7e1afa78a1d42886cc89ae759cf865b22a5f28de2eca36afc2e8a402302cbdcf2b4819afaa0a11cb68371eef174d98315696c49a8ef53c96f11e4f43ffd421e456b4d6a9d1d2ab4a836f1545ebf50ff87bc3fe8473a3b8a698eb44c3b5821fc5bae3e1bd59723b69b2d7b5330424c30845eb1f7a5eef |
| randwidth: 1024 |
| } |
| { |
| name: ChipGen |
| desc: Chip generation number. |
| type: logic [15:0] |
| default: 16'h 0000 |
| expose: "true" |
| name_top: LcCtrlChipGen |
| } |
| { |
| name: ChipRev |
| desc: Chip revision number. |
| type: logic [15:0] |
| default: 16'h 0000 |
| expose: "true" |
| name_top: LcCtrlChipRev |
| } |
| { |
| name: IdcodeValue |
| desc: JTAG ID code. |
| type: logic [31:0] |
| default: jtag_id_pkg::JTAG_IDCODE |
| expose: "true" |
| name_top: LcCtrlIdcodeValue |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: jtag |
| struct: jtag |
| package: jtag_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: pinmux_aon_lc_jtag |
| index: -1 |
| } |
| { |
| name: esc_scrap_state0_tx |
| struct: esc_tx |
| package: prim_esc_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: alert_handler_esc_tx |
| index: 1 |
| } |
| { |
| name: esc_scrap_state0_rx |
| struct: esc_rx |
| package: prim_esc_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: alert_handler_esc_rx |
| index: 1 |
| } |
| { |
| name: esc_scrap_state1_tx |
| struct: esc_tx |
| package: prim_esc_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: alert_handler_esc_tx |
| index: 2 |
| } |
| { |
| name: esc_scrap_state1_rx |
| struct: esc_rx |
| package: prim_esc_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: alert_handler_esc_rx |
| index: 2 |
| } |
| { |
| name: pwr_lc |
| struct: pwr_lc |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: pwrmgr_aon_pwr_lc |
| index: -1 |
| } |
| { |
| name: lc_otp_vendor_test |
| struct: lc_otp_vendor_test |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_signame: lc_ctrl_lc_otp_vendor_test |
| index: -1 |
| } |
| { |
| name: otp_lc_data |
| struct: otp_lc_data |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: otp_ctrl_pkg::OTP_LC_DATA_DEFAULT |
| inst_name: lc_ctrl |
| top_signame: otp_ctrl_otp_lc_data |
| index: -1 |
| } |
| { |
| name: lc_otp_program |
| struct: lc_otp_program |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_signame: lc_ctrl_lc_otp_program |
| index: -1 |
| } |
| { |
| name: kmac_data |
| struct: app |
| package: kmac_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| top_signame: kmac_app |
| index: 1 |
| } |
| { |
| name: lc_dft_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_dft_en |
| index: -1 |
| } |
| { |
| name: lc_nvm_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_nvm_debug_en |
| index: -1 |
| } |
| { |
| name: lc_hw_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: lc_cpu_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_cpu_en |
| index: -1 |
| } |
| { |
| name: lc_keymgr_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_keymgr_en |
| index: -1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: lc_clk_byp_req |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_clk_byp_req |
| index: -1 |
| } |
| { |
| name: lc_clk_byp_ack |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_clk_byp_ack |
| index: -1 |
| } |
| { |
| name: lc_flash_rma_req |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_flash_rma_req |
| index: -1 |
| } |
| { |
| name: lc_flash_rma_seed |
| struct: lc_flash_rma_seed |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| top_signame: flash_ctrl_rma_seed |
| index: -1 |
| } |
| { |
| name: lc_flash_rma_ack |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| top_signame: otbn_lc_rma_ack |
| index: -1 |
| } |
| { |
| name: lc_check_byp_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_check_byp_en |
| index: -1 |
| } |
| { |
| name: lc_creator_seed_sw_rw_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_creator_seed_sw_rw_en |
| index: -1 |
| } |
| { |
| name: lc_owner_seed_sw_rw_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_owner_seed_sw_rw_en |
| index: -1 |
| } |
| { |
| name: lc_iso_part_sw_rd_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_iso_part_sw_rd_en |
| index: -1 |
| } |
| { |
| name: lc_iso_part_sw_wr_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_iso_part_sw_wr_en |
| index: -1 |
| } |
| { |
| name: lc_seed_hw_rd_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_seed_hw_rd_en |
| index: -1 |
| } |
| { |
| name: lc_keymgr_div |
| struct: lc_keymgr_div |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_keymgr_div |
| index: -1 |
| } |
| { |
| name: otp_device_id |
| struct: otp_device_id |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| top_signame: lc_ctrl_otp_device_id |
| index: -1 |
| } |
| { |
| name: otp_manuf_state |
| struct: otp_manuf_state |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| top_signame: lc_ctrl_otp_manuf_state |
| index: -1 |
| } |
| { |
| name: hw_rev |
| struct: lc_hw_rev |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: lc_ctrl_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40140000 |
| } |
| } |
| { |
| name: alert_handler |
| type: alert_handler |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_edn_i: main |
| } |
| clock_group: secure |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: "0" |
| } |
| rst_edn_ni: |
| { |
| name: lc |
| domain: "0" |
| } |
| } |
| attr: ipgen |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_secure |
| clk_edn_i: clkmgr_aon_clocks.clk_main_secure |
| } |
| domain: |
| [ |
| "0" |
| ] |
| param_decl: {} |
| memory: {} |
| param_list: |
| [ |
| { |
| name: RndCnstLfsrSeed |
| desc: Compile-time random bits for initial LFSR seed |
| type: alert_pkg::lfsr_seed_t |
| randcount: 32 |
| randtype: data |
| name_top: RndCnstAlertHandlerLfsrSeed |
| default: 0x762a1f91 |
| randwidth: 32 |
| } |
| { |
| name: RndCnstLfsrPerm |
| desc: Compile-time random permutation for LFSR output |
| type: alert_pkg::lfsr_perm_t |
| randcount: 32 |
| randtype: perm |
| name_top: RndCnstAlertHandlerLfsrPerm |
| default: 0x375ed89d2a1d32862f7a7785f940950cc1cbdb05 |
| randwidth: 160 |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: crashdump |
| struct: alert_crashdump |
| package: alert_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: alert_handler |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: alert_handler_crashdump |
| index: -1 |
| } |
| { |
| name: edn |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: alert_handler |
| default: "" |
| top_signame: edn0_edn |
| index: 4 |
| } |
| { |
| name: esc_rx |
| struct: esc_rx |
| package: prim_esc_pkg |
| type: uni |
| act: rcv |
| width: 4 |
| inst_name: alert_handler |
| default: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: alert_handler_esc_rx |
| index: -1 |
| } |
| { |
| name: esc_tx |
| struct: esc_tx |
| package: prim_esc_pkg |
| type: uni |
| act: req |
| width: 4 |
| inst_name: alert_handler |
| default: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: alert_handler_esc_tx |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: alert_handler |
| default: "" |
| end_idx: -1 |
| top_signame: alert_handler_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40150000 |
| } |
| } |
| { |
| name: spi_host0 |
| type: spi_host |
| clock_srcs: |
| { |
| clk_i: io |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: spi_host0 |
| domain: "0" |
| } |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_peri |
| } |
| domain: |
| [ |
| "0" |
| ] |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: passthrough |
| struct: passthrough |
| package: spi_device_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: spi_host0 |
| default: "" |
| top_signame: spi_device_passthrough |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: spi_host0 |
| default: "" |
| end_idx: -1 |
| top_signame: spi_host0_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40300000 |
| } |
| } |
| { |
| name: spi_host1 |
| type: spi_host |
| clock_srcs: |
| { |
| clk_i: io_div2 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: spi_host1 |
| domain: "0" |
| } |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div2_peri |
| } |
| domain: |
| [ |
| "0" |
| ] |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: passthrough |
| struct: passthrough |
| package: spi_device_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: spi_host1 |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: spi_host1 |
| default: "" |
| end_idx: -1 |
| top_signame: spi_host1_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40310000 |
| } |
| } |
| { |
| name: usbdev |
| type: usbdev |
| clock_srcs: |
| { |
| clk_i: usb |
| clk_aon_i: aon |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: usb |
| domain: "0" |
| } |
| rst_aon_ni: |
| { |
| name: usb_aon |
| domain: "0" |
| } |
| } |
| param_decl: |
| { |
| RcvrWakeTimeUs: "100" |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_usb_peri |
| clk_aon_i: clkmgr_aon_clocks.clk_aon_peri |
| } |
| domain: |
| [ |
| "0" |
| ] |
| memory: {} |
| param_list: |
| [ |
| { |
| name: Stub |
| desc: Stub out the core of entropy_src logic |
| type: bit |
| default: "0" |
| expose: "true" |
| name_top: UsbdevStub |
| } |
| { |
| name: RcvrWakeTimeUs |
| desc: Maximum number of microseconds for the differential receiver to become operational |
| type: int |
| default: "100" |
| expose: "true" |
| name_top: UsbdevRcvrWakeTimeUs |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: usb_rx_d |
| desc: USB RX data from an external differential receiver, if available |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| external: true |
| top_signame: usbdev_usb_rx_d |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: usb_tx_d |
| desc: USB transmit data value (not used if usb_tx_se0 is set) |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| external: true |
| top_signame: usbdev_usb_tx_d |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: usb_tx_se0 |
| desc: Force transmission of a USB single-ended zero (i.e. both D+ and D- are low) regardless of usb_tx_d |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| external: true |
| top_signame: usbdev_usb_tx_se0 |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: usb_tx_use_d_se0 |
| desc: Use the usb_tx_d and usb_tx_se0 TX interface, instead of usb_dp_o and usb_dn_o |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| external: true |
| top_signame: usbdev_usb_tx_use_d_se0 |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: usb_dp_pullup |
| desc: USB D+ pullup control |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: usbdev_usb_dp_pullup |
| index: -1 |
| } |
| { |
| name: usb_dn_pullup |
| desc: USB D- pullup control |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: usbdev_usb_dn_pullup |
| index: -1 |
| } |
| { |
| name: usb_rx_enable |
| desc: USB differential receiver enable |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| external: true |
| top_signame: usbdev_usb_rx_enable |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: usb_ref_val |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| external: true |
| top_signame: usbdev_usb_ref_val |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: usb_ref_pulse |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| external: true |
| top_signame: usbdev_usb_ref_pulse |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: usb_aon_suspend_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: usbdev_usb_aon_suspend_req |
| index: -1 |
| } |
| { |
| name: usb_aon_wake_ack |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: usbdev_usb_aon_wake_ack |
| index: -1 |
| } |
| { |
| name: usb_aon_bus_reset |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: usbdev_usb_aon_bus_reset |
| index: -1 |
| } |
| { |
| name: usb_aon_sense_lost |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: usbdev_usb_aon_sense_lost |
| index: -1 |
| } |
| { |
| name: usb_aon_wake_detect_active |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| top_signame: pinmux_aon_usbdev_wake_detect_active |
| index: -1 |
| } |
| { |
| name: ram_cfg |
| struct: ram_2p_cfg |
| package: prim_ram_2p_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| top_signame: ast_ram_2p_cfg |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| end_idx: -1 |
| top_signame: usbdev_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40320000 |
| } |
| } |
| { |
| name: pwrmgr_aon |
| type: pwrmgr |
| clock_group: powerup |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_slow_i: aon |
| clk_lc_i: io_div4 |
| clk_esc_i: |
| { |
| clock: io_div4 |
| group: secure |
| } |
| } |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: por_io_div4 |
| domain: Aon |
| } |
| rst_main_ni: |
| { |
| name: por_aon |
| domain: "0" |
| } |
| rst_lc_ni: |
| { |
| name: lc_io_div4 |
| domain: Aon |
| } |
| rst_esc_ni: |
| { |
| name: lc_io_div4 |
| domain: Aon |
| } |
| rst_slow_ni: |
| { |
| name: por_aon |
| domain: Aon |
| } |
| } |
| domain: |
| [ |
| Aon |
| "0" |
| ] |
| attr: templated |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_powerup |
| clk_slow_i: clkmgr_aon_clocks.clk_aon_powerup |
| clk_lc_i: clkmgr_aon_clocks.clk_io_div4_powerup |
| clk_esc_i: clkmgr_aon_clocks.clk_io_div4_secure |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: pwr_ast |
| struct: pwr_ast |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| external: true |
| top_signame: pwrmgr_ast |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: pwr_rst |
| struct: pwr_rst |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwrmgr_aon_pwr_rst |
| index: -1 |
| } |
| { |
| name: pwr_clk |
| struct: pwr_clk |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwrmgr_aon_pwr_clk |
| index: -1 |
| } |
| { |
| name: pwr_otp |
| struct: pwr_otp |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwrmgr_aon_pwr_otp |
| index: -1 |
| } |
| { |
| name: pwr_lc |
| struct: pwr_lc |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwrmgr_aon_pwr_lc |
| index: -1 |
| } |
| { |
| name: pwr_flash |
| struct: pwr_flash |
| package: pwrmgr_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pwrmgr_aon_pwr_flash |
| index: -1 |
| } |
| { |
| name: esc_rst_tx |
| struct: esc_tx |
| package: prim_esc_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| top_signame: alert_handler_esc_tx |
| index: 3 |
| } |
| { |
| name: esc_rst_rx |
| struct: esc_rx |
| package: prim_esc_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| top_signame: alert_handler_esc_rx |
| index: 3 |
| } |
| { |
| name: pwr_cpu |
| struct: pwr_cpu |
| package: pwrmgr_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| top_signame: rv_core_ibex_pwrmgr |
| index: -1 |
| } |
| { |
| name: wakeups |
| struct: logic |
| type: uni |
| act: rcv |
| width: 6 |
| inst_name: pwrmgr_aon |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: pwrmgr_aon_wakeups |
| index: -1 |
| } |
| { |
| name: rstreqs |
| struct: logic |
| type: uni |
| act: rcv |
| width: 2 |
| inst_name: pwrmgr_aon |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: pwrmgr_aon_rstreqs |
| index: -1 |
| } |
| { |
| name: ndmreset_req |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| package: "" |
| top_signame: rv_dm_ndmreset_req |
| index: -1 |
| } |
| { |
| name: strap |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pwrmgr_aon_strap |
| index: -1 |
| } |
| { |
| name: low_power |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pwrmgr_aon_low_power |
| index: -1 |
| } |
| { |
| name: rom_ctrl |
| struct: pwrmgr_data |
| package: rom_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| top_signame: rom_ctrl_pwrmgr_data |
| index: -1 |
| } |
| { |
| name: fetch_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pwrmgr_aon_fetch_en |
| index: -1 |
| } |
| { |
| name: lc_dft_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| top_signame: lc_ctrl_lc_dft_en |
| index: -1 |
| } |
| { |
| name: lc_hw_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: sw_rst_req |
| struct: mubi4 |
| package: prim_mubi_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| top_signame: rstmgr_aon_sw_rst_req |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwrmgr_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40400000 |
| } |
| } |
| { |
| name: rstmgr_aon |
| type: rstmgr |
| clock_srcs: |
| { |
| clk_i: |
| { |
| clock: io_div4 |
| group: powerup |
| } |
| clk_por_i: io_div4 |
| clk_aon_i: aon |
| clk_main_i: main |
| clk_io_i: io |
| clk_usb_i: usb |
| clk_io_div2_i: io_div2 |
| clk_io_div4_i: io_div4 |
| } |
| clock_group: powerup |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: Aon |
| } |
| rst_por_ni: |
| { |
| name: por_io_div4 |
| domain: Aon |
| } |
| } |
| domain: |
| [ |
| Aon |
| "0" |
| ] |
| attr: templated |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_powerup |
| clk_por_i: clkmgr_aon_clocks.clk_io_div4_powerup |
| clk_aon_i: clkmgr_aon_clocks.clk_aon_powerup |
| clk_main_i: clkmgr_aon_clocks.clk_main_powerup |
| clk_io_i: clkmgr_aon_clocks.clk_io_powerup |
| clk_usb_i: clkmgr_aon_clocks.clk_usb_powerup |
| clk_io_div2_i: clkmgr_aon_clocks.clk_io_div2_powerup |
| clk_io_div4_i: clkmgr_aon_clocks.clk_io_div4_powerup |
| } |
| param_decl: {} |
| memory: {} |
| param_list: |
| [ |
| { |
| name: SecCheck |
| desc: |
| ''' |
| When 1, enable rstmgr reset consistency checks. |
| When 0, there are no consistency checks. |
| ''' |
| type: bit |
| default: 1'b1 |
| expose: "true" |
| name_top: SecRstmgrAonCheck |
| } |
| { |
| name: SecMaxSyncDelay |
| desc: The maximum synchronization delay for parent / child reset checks. |
| type: int |
| default: "2" |
| expose: "true" |
| name_top: SecRstmgrAonMaxSyncDelay |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: por_n |
| desc: |
| ''' |
| Root power on reset signals from ast. |
| There is one root reset signal for each core power domain. |
| ''' |
| struct: logic |
| type: uni |
| act: rcv |
| width: 2 |
| inst_name: rstmgr_aon |
| default: "" |
| package: "" |
| external: true |
| top_signame: por_n |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: pwr |
| desc: |
| ''' |
| Reset request signals from power manager. |
| Power manager can request for specific domains of the lc/sys reset tree to assert. |
| ''' |
| struct: pwr_rst |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| package: pwrmgr_pkg |
| top_signame: pwrmgr_aon_pwr_rst |
| index: -1 |
| } |
| { |
| name: resets |
| desc: Leaf resets fed to the system. |
| struct: rstmgr_out |
| package: rstmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| top_signame: rstmgr_aon_resets |
| index: -1 |
| } |
| { |
| name: rst_en |
| desc: Low-power-group outputs used by alert handler. |
| struct: rstmgr_rst_en |
| package: rstmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| top_signame: rstmgr_aon_rst_en |
| index: -1 |
| } |
| { |
| name: alert_dump |
| desc: Alert handler crash dump information. |
| struct: alert_crashdump |
| package: alert_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| top_signame: alert_handler_crashdump |
| index: -1 |
| } |
| { |
| name: cpu_dump |
| desc: Main processing element crash dump information. |
| struct: cpu_crash_dump |
| package: rv_core_ibex_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| top_signame: rv_core_ibex_crash_dump |
| index: -1 |
| } |
| { |
| name: sw_rst_req |
| desc: Software requested system reset to pwrmgr. |
| struct: mubi4 |
| package: prim_mubi_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rstmgr_aon_sw_rst_req |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: rstmgr_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40410000 |
| } |
| } |
| { |
| name: clkmgr_aon |
| type: clkmgr |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_main_i: |
| { |
| group: ast |
| clock: main |
| } |
| clk_io_i: |
| { |
| group: ast |
| clock: io |
| } |
| clk_usb_i: |
| { |
| group: ast |
| clock: usb |
| } |
| clk_aon_i: |
| { |
| group: ast |
| clock: aon |
| } |
| } |
| clock_group: powerup |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: Aon |
| } |
| rst_aon_ni: |
| { |
| name: lc_aon |
| domain: Aon |
| } |
| rst_io_ni: |
| { |
| name: lc_io |
| domain: Aon |
| } |
| rst_io_div2_ni: |
| { |
| name: lc_io_div2 |
| domain: Aon |
| } |
| rst_io_div4_ni: |
| { |
| name: lc_io_div4 |
| domain: Aon |
| } |
| rst_main_ni: |
| { |
| name: lc |
| domain: Aon |
| } |
| rst_usb_ni: |
| { |
| name: lc_usb |
| domain: Aon |
| } |
| rst_root_ni: |
| { |
| name: por_io_div4 |
| domain: Aon |
| } |
| rst_root_io_ni: |
| { |
| name: por_io |
| domain: Aon |
| } |
| rst_root_io_div2_ni: |
| { |
| name: por_io_div2 |
| domain: Aon |
| } |
| rst_root_io_div4_ni: |
| { |
| name: por_io_div4 |
| domain: Aon |
| } |
| rst_root_main_ni: |
| { |
| name: por |
| domain: Aon |
| } |
| rst_root_usb_ni: |
| { |
| name: por_usb |
| domain: Aon |
| } |
| } |
| domain: |
| [ |
| Aon |
| ] |
| attr: templated |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_powerup |
| clk_main_i: clk_main_i |
| clk_io_i: clk_io_i |
| clk_usb_i: clk_usb_i |
| clk_aon_i: clk_aon_i |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: clocks |
| struct: clkmgr_out |
| package: clkmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| top_signame: clkmgr_aon_clocks |
| index: -1 |
| } |
| { |
| name: cg_en |
| struct: clkmgr_cg_en |
| package: clkmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| top_signame: clkmgr_aon_cg_en |
| index: -1 |
| } |
| { |
| name: lc_hw_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: io_clk_byp_req |
| struct: mubi4 |
| package: prim_mubi_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| external: true |
| top_signame: io_clk_byp_req |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: io_clk_byp_ack |
| struct: mubi4 |
| package: prim_mubi_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| external: true |
| top_signame: io_clk_byp_ack |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: all_clk_byp_req |
| struct: mubi4 |
| package: prim_mubi_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| external: true |
| top_signame: all_clk_byp_req |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: all_clk_byp_ack |
| struct: mubi4 |
| package: prim_mubi_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| external: true |
| top_signame: all_clk_byp_ack |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: hi_speed_sel |
| struct: mubi4 |
| package: prim_mubi_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| external: true |
| top_signame: hi_speed_sel |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: div_step_down_req |
| struct: mubi4 |
| package: prim_mubi_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| external: true |
| top_signame: div_step_down_req |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: lc_clk_byp_req |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| top_signame: lc_ctrl_lc_clk_byp_req |
| index: -1 |
| } |
| { |
| name: lc_clk_byp_ack |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| top_signame: lc_ctrl_lc_clk_byp_ack |
| index: -1 |
| } |
| { |
| name: jitter_en |
| struct: mubi4 |
| package: prim_mubi_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| external: true |
| top_signame: clk_main_jitter_en |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: pwr |
| struct: pwr_clk |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| package: pwrmgr_pkg |
| top_signame: pwrmgr_aon_pwr_clk |
| index: -1 |
| } |
| { |
| name: idle |
| struct: mubi4 |
| package: prim_mubi_pkg |
| type: uni |
| act: rcv |
| width: 4 |
| inst_name: clkmgr_aon |
| default: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: clkmgr_aon_idle |
| index: -1 |
| } |
| { |
| name: calib_rdy |
| desc: Indicates clocks are calibrated and frequencies accurate |
| struct: mubi4 |
| package: prim_mubi_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: prim_mubi_pkg::MuBi4True |
| inst_name: clkmgr_aon |
| external: true |
| top_signame: calib_rdy |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: clkmgr_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40420000 |
| } |
| } |
| { |
| name: sysrst_ctrl_aon |
| type: sysrst_ctrl |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_aon_i: aon |
| } |
| clock_group: secure |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: Aon |
| } |
| rst_aon_ni: |
| { |
| name: lc_aon |
| domain: Aon |
| } |
| } |
| domain: |
| [ |
| Aon |
| ] |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_secure |
| clk_aon_i: clkmgr_aon_clocks.clk_aon_secure |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: wkup_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: sysrst_ctrl_aon |
| default: "" |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 0 |
| } |
| { |
| name: rst_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: sysrst_ctrl_aon |
| default: "" |
| package: "" |
| top_signame: pwrmgr_aon_rstreqs |
| index: 0 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: sysrst_ctrl_aon |
| default: "" |
| end_idx: -1 |
| top_signame: sysrst_ctrl_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40430000 |
| } |
| } |
| { |
| name: adc_ctrl_aon |
| type: adc_ctrl |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_aon_i: aon |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: Aon |
| } |
| rst_aon_ni: |
| { |
| name: lc_aon |
| domain: Aon |
| } |
| } |
| domain: |
| [ |
| Aon |
| ] |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| clk_aon_i: clkmgr_aon_clocks.clk_aon_peri |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: adc |
| struct: adc_ast |
| package: ast_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: adc_ctrl_aon |
| default: "" |
| external: true |
| top_signame: adc |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: wkup_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: adc_ctrl_aon |
| default: "" |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: adc_ctrl_aon |
| default: "" |
| end_idx: -1 |
| top_signame: adc_ctrl_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40440000 |
| } |
| } |
| { |
| name: pwm_aon |
| type: pwm |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_core_i: aon |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: Aon |
| } |
| rst_core_ni: |
| { |
| name: lc_aon |
| domain: Aon |
| } |
| } |
| domain: |
| [ |
| Aon |
| ] |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| clk_core_i: clkmgr_aon_clocks.clk_aon_peri |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: pwm_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwm_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40450000 |
| } |
| } |
| { |
| name: pinmux_aon |
| type: pinmux |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_aon_i: aon |
| } |
| clock_group: powerup |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: Aon |
| } |
| rst_aon_ni: |
| { |
| name: lc_aon |
| domain: Aon |
| } |
| rst_sys_ni: |
| { |
| name: sys_io_div4 |
| domain: Aon |
| } |
| } |
| domain: |
| [ |
| Aon |
| ] |
| attr: templated |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_powerup |
| clk_aon_i: clkmgr_aon_clocks.clk_aon_powerup |
| } |
| param_decl: {} |
| memory: {} |
| param_list: |
| [ |
| { |
| name: TargetCfg |
| desc: Target specific pinmux configuration. |
| type: pinmux_pkg::target_cfg_t |
| default: pinmux_pkg::DefaultTargetCfg |
| expose: "true" |
| name_top: PinmuxAonTargetCfg |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: lc_hw_debug_en |
| desc: Debug enable qualifier coming from life cycle controller, used for HW strap qualification. |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: pinmux_aon |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: lc_dft_en |
| desc: Test enable qualifier coming from life cycle controller, used for HW strap qualification. |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: pinmux_aon |
| top_signame: lc_ctrl_lc_dft_en |
| index: -1 |
| } |
| { |
| name: lc_escalate_en |
| desc: |
| ''' |
| Escalation enable signal coming from life cycle controller, used for invalidating |
| the latched lc_hw_debug_en state inside the strap sampling logic. |
| ''' |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: pinmux_aon |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: lc_check_byp_en |
| desc: |
| ''' |
| Check bypass enable signal coming from life cycle controller, used for invalidating |
| the latched lc_hw_debug_en state inside the strap sampling logic. This signal is asserted |
| whenever the life cycle controller performs a life cycle transition. Its main use is |
| to skip any background checks inside the life cycle partition of the OTP controller while |
| a life cycle transition is in progress. |
| ''' |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: pinmux_aon |
| top_signame: lc_ctrl_lc_check_byp_en |
| index: -1 |
| } |
| { |
| name: pinmux_hw_debug_en |
| desc: |
| ''' |
| This is the latched version of lc_hw_debug_en_i. We use it exclusively to gate the JTAG |
| signals and TAP side of the RV_DM so that RV_DM can remain live during an NDM reset cycle. |
| ''' |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: pinmux_aon |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pinmux_aon_pinmux_hw_debug_en |
| index: -1 |
| } |
| { |
| name: lc_jtag |
| desc: Qualified JTAG signals for life cycle controller TAP. |
| struct: jtag |
| package: jtag_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pinmux_aon_lc_jtag |
| index: -1 |
| } |
| { |
| name: rv_jtag |
| desc: Qualified JTAG signals for RISC-V processor TAP. |
| struct: jtag |
| package: jtag_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pinmux_aon_rv_jtag |
| index: -1 |
| } |
| { |
| name: dft_jtag |
| desc: Qualified JTAG signals for DFT TAP. |
| struct: jtag |
| package: jtag_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| top_signame: pinmux_aon_dft_jtag |
| index: -1 |
| } |
| { |
| name: dft_strap_test |
| desc: Sampled DFT strap values, going to the DFT TAP. |
| struct: dft_strap_test_req |
| package: pinmux_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: pinmux_aon |
| external: true |
| top_signame: dft_strap_test |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: dft_hold_tap_sel |
| desc: TAP selection hold indication, asserted by the DFT TAP during boundary scan. |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| default: "'0" |
| inst_name: pinmux_aon |
| package: "" |
| external: true |
| top_signame: dft_hold_tap_sel |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: sleep_en |
| desc: Level signal that is asserted when the power manager enters sleep. |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| top_signame: pwrmgr_aon_low_power |
| index: -1 |
| } |
| { |
| name: strap_en |
| desc: This signal is pulsed high by the power manager after reset in order to sample the HW straps. |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| top_signame: pwrmgr_aon_strap |
| index: -1 |
| } |
| { |
| name: pin_wkup_req |
| desc: Wakeup request from wakeup detectors, to the power manager, running on the AON clock. |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 2 |
| } |
| { |
| name: usbdev_dppullup_en |
| desc: Pullup enable signal coming from the USB IP. |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| package: "" |
| top_signame: usbdev_usb_dp_pullup |
| index: -1 |
| } |
| { |
| name: usbdev_dnpullup_en |
| desc: Pullup enable signal coming from the USB IP. |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| package: "" |
| top_signame: usbdev_usb_dn_pullup |
| index: -1 |
| } |
| { |
| name: usb_dppullup_en |
| desc: " Pullup enable signal going to USB PHY, needs to be maintained in low-power mode." |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| external: true |
| top_signame: usb_dp_pullup_en |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: usb_dnpullup_en |
| desc: Pullup enable signal going to USB PHY, needs to be maintained in low-power mode. |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| external: true |
| top_signame: usb_dn_pullup_en |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: usb_wkup_req |
| desc: Wakeup request from USB wakeup detector, going to the power manager, running on the AON clock. |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 3 |
| } |
| { |
| name: usbdev_suspend_req |
| desc: Indicates whether USB is in suspended state, coming from the USB device. |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| package: "" |
| top_signame: usbdev_usb_aon_suspend_req |
| index: -1 |
| } |
| { |
| name: usbdev_wake_ack |
| desc: Acknowledges the USB wakeup request, coming from the USB device. |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| package: "" |
| top_signame: usbdev_usb_aon_wake_ack |
| index: -1 |
| } |
| { |
| name: usbdev_bus_reset |
| desc: Event signal that indicates what happened while monitoring. |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| top_signame: usbdev_usb_aon_bus_reset |
| index: -1 |
| } |
| { |
| name: usbdev_sense_lost |
| desc: Event signal that indicates what happened while monitoring. |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| top_signame: usbdev_usb_aon_sense_lost |
| index: -1 |
| } |
| { |
| name: usbdev_wake_detect_active |
| desc: State debug information. |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pinmux_aon_usbdev_wake_detect_active |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pinmux_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40460000 |
| } |
| } |
| { |
| name: aon_timer_aon |
| type: aon_timer |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_aon_i: aon |
| } |
| clock_group: timers |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: Aon |
| } |
| rst_aon_ni: |
| { |
| name: lc_aon |
| domain: Aon |
| } |
| } |
| domain: |
| [ |
| Aon |
| ] |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_timers |
| clk_aon_i: clkmgr_aon_clocks.clk_aon_timers |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: nmi_wdog_timer_bark |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: aon_timer_aon |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: aon_timer_aon_nmi_wdog_timer_bark |
| index: -1 |
| } |
| { |
| name: wkup_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: aon_timer_aon |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 4 |
| } |
| { |
| name: aon_timer_rst_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: aon_timer_aon |
| package: "" |
| top_signame: pwrmgr_aon_rstreqs |
| index: 1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: aon_timer_aon |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: sleep_mode |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: aon_timer_aon |
| default: "" |
| package: "" |
| top_signame: pwrmgr_aon_low_power |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: aon_timer_aon |
| default: "" |
| end_idx: -1 |
| top_signame: aon_timer_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40470000 |
| } |
| } |
| { |
| name: ast |
| type: ast |
| clock_srcs: |
| { |
| clk_ast_tlul_i: |
| { |
| clock: io_div4 |
| group: infra |
| } |
| clk_ast_adc_i: |
| { |
| clock: aon |
| group: peri |
| } |
| clk_ast_alert_i: |
| { |
| clock: io_div4 |
| group: secure |
| } |
| clk_ast_es_i: |
| { |
| clock: main |
| group: secure |
| } |
| clk_ast_rng_i: |
| { |
| clock: main |
| group: secure |
| } |
| clk_ast_usb_i: |
| { |
| clock: usb |
| group: peri |
| } |
| } |
| clock_group: secure |
| reset_connections: |
| { |
| rst_ast_tlul_ni: |
| { |
| name: lc_io_div4 |
| domain: "0" |
| } |
| rst_ast_adc_ni: |
| { |
| name: lc_aon |
| domain: Aon |
| } |
| rst_ast_alert_ni: |
| { |
| name: lc_io_div4 |
| domain: "0" |
| } |
| rst_ast_es_ni: |
| { |
| name: lc |
| domain: "0" |
| } |
| rst_ast_rng_ni: |
| { |
| name: lc |
| domain: "0" |
| } |
| rst_ast_usb_ni: |
| { |
| name: usb |
| domain: "0" |
| } |
| } |
| domain: |
| [ |
| Aon |
| "0" |
| ] |
| attr: reggen_only |
| clock_connections: |
| { |
| clk_ast_tlul_i: clkmgr_aon_clocks.clk_io_div4_infra |
| clk_ast_adc_i: clkmgr_aon_clocks.clk_aon_peri |
| clk_ast_alert_i: clkmgr_aon_clocks.clk_io_div4_secure |
| clk_ast_es_i: clkmgr_aon_clocks.clk_main_secure |
| clk_ast_rng_i: clkmgr_aon_clocks.clk_main_secure |
| clk_ast_usb_i: clkmgr_aon_clocks.clk_usb_peri |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: ast |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40480000 |
| } |
| } |
| { |
| name: sensor_ctrl |
| type: sensor_ctrl |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_aon_i: aon |
| } |
| clock_group: secure |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: Aon |
| } |
| rst_aon_ni: |
| { |
| name: lc_aon |
| domain: Aon |
| } |
| } |
| domain: |
| [ |
| Aon |
| ] |
| attr: reggen_top |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_secure |
| clk_aon_i: clkmgr_aon_clocks.clk_aon_secure |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: ast_alert |
| struct: ast_alert |
| package: ast_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: sensor_ctrl |
| default: "" |
| external: true |
| top_signame: sensor_ctrl_ast_alert |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: ast_status |
| struct: ast_status |
| package: ast_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: sensor_ctrl |
| default: "" |
| external: true |
| top_signame: sensor_ctrl_ast_status |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: ast_init_done |
| struct: mubi4 |
| package: prim_mubi_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: prim_mubi_pkg::MuBi4True |
| inst_name: sensor_ctrl |
| external: true |
| top_signame: ast_init_done |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: ast2pinmux |
| struct: logic |
| type: uni |
| act: rcv |
| width: 9 |
| inst_name: sensor_ctrl |
| default: "" |
| package: "" |
| external: true |
| top_signame: ast2pinmux |
| conn_type: false |
| index: -1 |
| } |
| { |
| name: wkup_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: sensor_ctrl |
| default: "" |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 5 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: sensor_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: sensor_ctrl_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40490000 |
| } |
| } |
| { |
| name: sram_ctrl_ret_aon |
| type: sram_ctrl |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_otp_i: io_div4 |
| } |
| clock_group: infra |
| reset_connections: |
| { |
| rst_ni: |
| { |
| name: lc_io_div4 |
| domain: Aon |
| } |
| rst_otp_ni: |
| { |
| name: lc_io_div4 |
| domain: Aon |
| } |
| } |
| domain: |
| [ |
| Aon |
| ] |
| param_decl: |
| { |
| InstrExec: "0" |
| } |
| base_addrs: |
| { |
| regs: 0x40500000 |
| ram: 0x40600000 |
| } |
| memory: |
| { |
| ram: |
| { |
| label: ram_ret_aon |
| swaccess: rw |
| data_intg_passthru: "true" |
| exec: True |
| byte_write: True |
| size: 0x1000 |
| } |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_infra |
| clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra |
| } |
| param_list: |
| [ |
| { |
| name: RndCnstSramKey |
