hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg: set in the sim_cfg that imports this file
  // name: "{dut}"

  // Top level testbench name (sv module).
  tb: tb

  // Top level dut name (sv module): set in the autogenerated sim cfg file that imports this.
  dut: ""

  // Simulator used to sign off this block
  tool: vcs

  // The top level (chip) into which this xbar is meant to go. This is set in the sim_cfg that
  // imports this file.
  top_chip: ""

  // Fusesoc core file used for building the file list.
  fusesoc_core: "lowrisc:dv:{top_chip}_{dut}_sim:0.1"

  // Set the path to testplan md file as it's not in the default location.
  testplan_doc_path: "hw/ip/tlul/doc/dv/#testplan"

  // Bypass VCS CHECK_SUM check as the exclusion file is generated without proper CHECK_SUM value
  vcs_cov_analyze_opts: ["-excl_bypass_checks"]
  vcs_cov_report_opts:  ["-excl_bypass_checks"]
  xcelium_cov_analyze_opts: []
  xcelium_cov_report_opts:  []

  cov_analyze_opts: ["{{tool}_cov_analyze_opts}"]
  cov_report_opts: ["{{tool}_cov_report_opts}"]

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                "{proj_root}/hw/ip/tlul/generic_dv/xbar_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: ["{dut}_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50
}