blob: a802fa4bf59930826efc073745aa9db3fb830c00 [file] [log] [blame]
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Package auto-generated by `reggen` containing data structure
package rbox_reg_pkg;
// Param list
parameter int NumCombo = 4;
// Address width within the block
parameter int BlockAw = 7;
////////////////////////////
// Typedefs for registers //
////////////////////////////
typedef struct packed {
logic q;
} rbox_reg2hw_intr_state_reg_t;
typedef struct packed {
logic q;
} rbox_reg2hw_intr_enable_reg_t;
typedef struct packed {
logic q;
logic qe;
} rbox_reg2hw_intr_test_reg_t;
typedef struct packed {
logic [15:0] q;
logic qe;
} rbox_reg2hw_ec_rst_ctl_reg_t;
typedef struct packed {
struct packed {
logic q;
} key0_in;
struct packed {
logic q;
} key0_out;
struct packed {
logic q;
} key1_in;
struct packed {
logic q;
} key1_out;
struct packed {
logic q;
} key2_in;
struct packed {
logic q;
} key2_out;
struct packed {
logic q;
} pwrb_in;
struct packed {
logic q;
} pwrb_out;
struct packed {
logic q;
} ac_present;
struct packed {
logic q;
} bat_disable;
} rbox_reg2hw_key_invert_ctl_reg_t;
typedef struct packed {
struct packed {
logic q;
} bat_disable_0;
struct packed {
logic q;
} ec_rst_l_0;
struct packed {
logic q;
} pwrb_out_0;
struct packed {
logic q;
} key0_out_0;
struct packed {
logic q;
} key1_out_0;
struct packed {
logic q;
} key2_out_0;
struct packed {
logic q;
} bat_disable_1;
struct packed {
logic q;
} ec_rst_l_1;
struct packed {
logic q;
} pwrb_out_1;
struct packed {
logic q;
} key0_out_1;
struct packed {
logic q;
} key1_out_1;
struct packed {
logic q;
} key2_out_1;
} rbox_reg2hw_pin_allowed_ctl_reg_t;
typedef struct packed {
struct packed {
logic q;
} bat_disable;
struct packed {
logic q;
} ec_rst_l;
struct packed {
logic q;
} pwrb_out;
struct packed {
logic q;
} key0_out;
struct packed {
logic q;
} key1_out;
struct packed {
logic q;
} key2_out;
} rbox_reg2hw_pin_out_ctl_reg_t;
typedef struct packed {
struct packed {
logic q;
} bat_disable;
struct packed {
logic q;
} ec_rst_l;
struct packed {
logic q;
} pwrb_out;
struct packed {
logic q;
} key0_out;
struct packed {
logic q;
} key1_out;
struct packed {
logic q;
} key2_out;
} rbox_reg2hw_pin_out_value_reg_t;
typedef struct packed {
struct packed {
logic q;
} pwrb_in_h2l;
struct packed {
logic q;
} key0_in_h2l;
struct packed {
logic q;
} key1_in_h2l;
struct packed {
logic q;
} key2_in_h2l;
struct packed {
logic q;
} ac_present_h2l;
struct packed {
logic q;
} ec_rst_l_h2l;
struct packed {
logic q;
} pwrb_in_l2h;
struct packed {
logic q;
} key0_in_l2h;
struct packed {
logic q;
} key1_in_l2h;
struct packed {
logic q;
} key2_in_l2h;
struct packed {
logic q;
} ac_present_l2h;
struct packed {
logic q;
} ec_rst_l_l2h;
} rbox_reg2hw_key_intr_ctl_reg_t;
typedef struct packed {
logic [15:0] q;
logic qe;
} rbox_reg2hw_key_intr_debounce_ctl_reg_t;
typedef struct packed {
struct packed {
logic [15:0] q;
logic qe;
} debounce_timer;
struct packed {
logic q;
logic qe;
} auto_block_enable;
} rbox_reg2hw_auto_block_debounce_ctl_reg_t;
typedef struct packed {
struct packed {
logic q;
} key0_out_sel;
struct packed {
logic q;
} key1_out_sel;
struct packed {
logic q;
} key2_out_sel;
struct packed {
logic q;
} key0_out_value;
struct packed {
logic q;
} key1_out_value;
struct packed {
logic q;
} key2_out_value;
} rbox_reg2hw_auto_block_out_ctl_reg_t;
typedef struct packed {
struct packed {
logic q;
} key0_in_sel;
struct packed {
logic q;
} key1_in_sel;
struct packed {
logic q;
} key2_in_sel;
struct packed {
logic q;
} pwrb_in_sel;
struct packed {
logic q;
} ac_present_sel;
} rbox_reg2hw_com_sel_ctl_mreg_t;
typedef struct packed {
logic [31:0] q;
logic qe;
} rbox_reg2hw_com_det_ctl_mreg_t;
typedef struct packed {
struct packed {
logic q;
} bat_disable;
struct packed {
logic q;
} interrupt;
struct packed {
logic q;
} ec_rst;
struct packed {
logic q;
} gsc_rst;
} rbox_reg2hw_com_out_ctl_mreg_t;
typedef struct packed {
logic d;
logic de;
} rbox_hw2reg_intr_state_reg_t;
typedef struct packed {
struct packed {
logic d;
logic de;
} ac_present;
struct packed {
logic d;
logic de;
} ec_rst_l;
struct packed {
logic d;
logic de;
} pwrb_in;
struct packed {
logic d;
logic de;
} key0_in;
struct packed {
logic d;
logic de;
} key1_in;
struct packed {
logic d;
logic de;
} key2_in;
} rbox_hw2reg_pin_in_value_reg_t;
typedef struct packed {
struct packed {
logic d;
logic de;
} combo0_h2l;
struct packed {
logic d;
logic de;
} combo1_h2l;
struct packed {
logic d;
logic de;
} combo2_h2l;
struct packed {
logic d;
logic de;
} combo3_h2l;
} rbox_hw2reg_combo_intr_status_reg_t;
typedef struct packed {
struct packed {
logic d;
logic de;
} pwrb_h2l;
struct packed {
logic d;
logic de;
} key0_in_h2l;
struct packed {
logic d;
logic de;
} key1_in_h2l;
struct packed {
logic d;
logic de;
} key2_in_h2l;
struct packed {
logic d;
logic de;
} ac_present_h2l;
struct packed {
logic d;
logic de;
} ec_rst_l_h2l;
struct packed {
logic d;
logic de;
} pwrb_l2h;
struct packed {
logic d;
logic de;
} key0_in_l2h;
struct packed {
logic d;
logic de;
} key1_in_l2h;
struct packed {
logic d;
logic de;
} key2_in_l2h;
struct packed {
logic d;
logic de;
} ac_present_l2h;
struct packed {
logic d;
logic de;
} ec_rst_l_l2h;
} rbox_hw2reg_key_intr_status_reg_t;
///////////////////////////////////////
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
rbox_reg2hw_intr_state_reg_t intr_state; // [276:276]
rbox_reg2hw_intr_enable_reg_t intr_enable; // [275:275]
rbox_reg2hw_intr_test_reg_t intr_test; // [274:273]
rbox_reg2hw_ec_rst_ctl_reg_t ec_rst_ctl; // [272:256]
rbox_reg2hw_key_invert_ctl_reg_t key_invert_ctl; // [255:246]
rbox_reg2hw_pin_allowed_ctl_reg_t pin_allowed_ctl; // [245:234]
rbox_reg2hw_pin_out_ctl_reg_t pin_out_ctl; // [233:228]
rbox_reg2hw_pin_out_value_reg_t pin_out_value; // [227:222]
rbox_reg2hw_key_intr_ctl_reg_t key_intr_ctl; // [221:210]
rbox_reg2hw_key_intr_debounce_ctl_reg_t key_intr_debounce_ctl; // [209:193]
rbox_reg2hw_auto_block_debounce_ctl_reg_t auto_block_debounce_ctl; // [192:174]
rbox_reg2hw_auto_block_out_ctl_reg_t auto_block_out_ctl; // [173:168]
rbox_reg2hw_com_sel_ctl_mreg_t [3:0] com_sel_ctl; // [167:148]
rbox_reg2hw_com_det_ctl_mreg_t [3:0] com_det_ctl; // [147:16]
rbox_reg2hw_com_out_ctl_mreg_t [3:0] com_out_ctl; // [15:0]
} rbox_reg2hw_t;
///////////////////////////////////////
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
rbox_hw2reg_intr_state_reg_t intr_state; // [45:44]
rbox_hw2reg_pin_in_value_reg_t pin_in_value; // [43:32]
rbox_hw2reg_combo_intr_status_reg_t combo_intr_status; // [31:24]
rbox_hw2reg_key_intr_status_reg_t key_intr_status; // [23:0]
} rbox_hw2reg_t;
// Register Address
parameter logic [BlockAw-1:0] RBOX_INTR_STATE_OFFSET = 7'h 0;
parameter logic [BlockAw-1:0] RBOX_INTR_ENABLE_OFFSET = 7'h 4;
parameter logic [BlockAw-1:0] RBOX_INTR_TEST_OFFSET = 7'h 8;
parameter logic [BlockAw-1:0] RBOX_REGWEN_OFFSET = 7'h c;
parameter logic [BlockAw-1:0] RBOX_EC_RST_CTL_OFFSET = 7'h 10;
parameter logic [BlockAw-1:0] RBOX_KEY_INVERT_CTL_OFFSET = 7'h 14;
parameter logic [BlockAw-1:0] RBOX_PIN_ALLOWED_CTL_OFFSET = 7'h 18;
parameter logic [BlockAw-1:0] RBOX_PIN_OUT_CTL_OFFSET = 7'h 1c;
parameter logic [BlockAw-1:0] RBOX_PIN_OUT_VALUE_OFFSET = 7'h 20;
parameter logic [BlockAw-1:0] RBOX_PIN_IN_VALUE_OFFSET = 7'h 24;
parameter logic [BlockAw-1:0] RBOX_KEY_INTR_CTL_OFFSET = 7'h 28;
parameter logic [BlockAw-1:0] RBOX_KEY_INTR_DEBOUNCE_CTL_OFFSET = 7'h 2c;
parameter logic [BlockAw-1:0] RBOX_AUTO_BLOCK_DEBOUNCE_CTL_OFFSET = 7'h 30;
parameter logic [BlockAw-1:0] RBOX_AUTO_BLOCK_OUT_CTL_OFFSET = 7'h 34;
parameter logic [BlockAw-1:0] RBOX_COM_SEL_CTL_0_OFFSET = 7'h 38;
parameter logic [BlockAw-1:0] RBOX_COM_SEL_CTL_1_OFFSET = 7'h 3c;
parameter logic [BlockAw-1:0] RBOX_COM_SEL_CTL_2_OFFSET = 7'h 40;
parameter logic [BlockAw-1:0] RBOX_COM_SEL_CTL_3_OFFSET = 7'h 44;
parameter logic [BlockAw-1:0] RBOX_COM_DET_CTL_0_OFFSET = 7'h 48;
parameter logic [BlockAw-1:0] RBOX_COM_DET_CTL_1_OFFSET = 7'h 4c;
parameter logic [BlockAw-1:0] RBOX_COM_DET_CTL_2_OFFSET = 7'h 50;
parameter logic [BlockAw-1:0] RBOX_COM_DET_CTL_3_OFFSET = 7'h 54;
parameter logic [BlockAw-1:0] RBOX_COM_OUT_CTL_0_OFFSET = 7'h 58;
parameter logic [BlockAw-1:0] RBOX_COM_OUT_CTL_1_OFFSET = 7'h 5c;
parameter logic [BlockAw-1:0] RBOX_COM_OUT_CTL_2_OFFSET = 7'h 60;
parameter logic [BlockAw-1:0] RBOX_COM_OUT_CTL_3_OFFSET = 7'h 64;
parameter logic [BlockAw-1:0] RBOX_COMBO_INTR_STATUS_OFFSET = 7'h 68;
parameter logic [BlockAw-1:0] RBOX_KEY_INTR_STATUS_OFFSET = 7'h 6c;
// Reset values for hwext registers and their fields
parameter logic [0:0] RBOX_INTR_TEST_RESVAL = 1'h 0;
parameter logic [0:0] RBOX_INTR_TEST_RBOX_INTR_O_RESVAL = 1'h 0;
// Register Index
typedef enum int {
RBOX_INTR_STATE,
RBOX_INTR_ENABLE,
RBOX_INTR_TEST,
RBOX_REGWEN,
RBOX_EC_RST_CTL,
RBOX_KEY_INVERT_CTL,
RBOX_PIN_ALLOWED_CTL,
RBOX_PIN_OUT_CTL,
RBOX_PIN_OUT_VALUE,
RBOX_PIN_IN_VALUE,
RBOX_KEY_INTR_CTL,
RBOX_KEY_INTR_DEBOUNCE_CTL,
RBOX_AUTO_BLOCK_DEBOUNCE_CTL,
RBOX_AUTO_BLOCK_OUT_CTL,
RBOX_COM_SEL_CTL_0,
RBOX_COM_SEL_CTL_1,
RBOX_COM_SEL_CTL_2,
RBOX_COM_SEL_CTL_3,
RBOX_COM_DET_CTL_0,
RBOX_COM_DET_CTL_1,
RBOX_COM_DET_CTL_2,
RBOX_COM_DET_CTL_3,
RBOX_COM_OUT_CTL_0,
RBOX_COM_OUT_CTL_1,
RBOX_COM_OUT_CTL_2,
RBOX_COM_OUT_CTL_3,
RBOX_COMBO_INTR_STATUS,
RBOX_KEY_INTR_STATUS
} rbox_id_e;
// Register width information to check illegal writes
parameter logic [3:0] RBOX_PERMIT [28] = '{
4'b 0001, // index[ 0] RBOX_INTR_STATE
4'b 0001, // index[ 1] RBOX_INTR_ENABLE
4'b 0001, // index[ 2] RBOX_INTR_TEST
4'b 0001, // index[ 3] RBOX_REGWEN
4'b 0011, // index[ 4] RBOX_EC_RST_CTL
4'b 0011, // index[ 5] RBOX_KEY_INVERT_CTL
4'b 0011, // index[ 6] RBOX_PIN_ALLOWED_CTL
4'b 0001, // index[ 7] RBOX_PIN_OUT_CTL
4'b 0001, // index[ 8] RBOX_PIN_OUT_VALUE
4'b 0001, // index[ 9] RBOX_PIN_IN_VALUE
4'b 0011, // index[10] RBOX_KEY_INTR_CTL
4'b 0011, // index[11] RBOX_KEY_INTR_DEBOUNCE_CTL
4'b 0111, // index[12] RBOX_AUTO_BLOCK_DEBOUNCE_CTL
4'b 0001, // index[13] RBOX_AUTO_BLOCK_OUT_CTL
4'b 0001, // index[14] RBOX_COM_SEL_CTL_0
4'b 0001, // index[15] RBOX_COM_SEL_CTL_1
4'b 0001, // index[16] RBOX_COM_SEL_CTL_2
4'b 0001, // index[17] RBOX_COM_SEL_CTL_3
4'b 1111, // index[18] RBOX_COM_DET_CTL_0
4'b 1111, // index[19] RBOX_COM_DET_CTL_1
4'b 1111, // index[20] RBOX_COM_DET_CTL_2
4'b 1111, // index[21] RBOX_COM_DET_CTL_3
4'b 0001, // index[22] RBOX_COM_OUT_CTL_0
4'b 0001, // index[23] RBOX_COM_OUT_CTL_1
4'b 0001, // index[24] RBOX_COM_OUT_CTL_2
4'b 0001, // index[25] RBOX_COM_OUT_CTL_3
4'b 0001, // index[26] RBOX_COMBO_INTR_STATUS
4'b 0011 // index[27] RBOX_KEY_INTR_STATUS
};
endpackage