| From 5caf3a335f38d4cd27d9d00a1947776acebdf10a Mon Sep 17 00:00:00 2001 |
| From: Philipp Wagner <phw@lowrisc.org> |
| Date: Fri, 22 Feb 2019 14:48:46 +0000 |
| Subject: [PATCH] Use lowrisc instead of PULP primitives |
| |
| Signed-off-by: Michael Schaffner <msf@google.com> |
| |
| diff --git a/src/dm_csrs.sv b/src/dm_csrs.sv |
| index 4b0f254..8f12ac4 100644 |
| --- a/src/dm_csrs.sv |
| +++ b/src/dm_csrs.sv |
| @@ -78,6 +78,7 @@ module dm_csrs #( |
| input logic sberror_valid_i, // bus error occurred |
| input logic [2:0] sberror_i // bus error occurred |
| ); |
| + |
| // the amount of bits we need to represent all harts |
| localparam int unsigned HartSelLen = (NrHarts == 1) ? 1 : $clog2(NrHarts); |
| localparam int unsigned NrHartsAligned = 2**HartSelLen; |
| @@ -85,10 +86,6 @@ module dm_csrs #( |
| dm::dtm_op_e dtm_op; |
| assign dtm_op = dm::dtm_op_e'(dmi_req_i.op); |
| |
| - logic resp_queue_full; |
| - logic resp_queue_empty; |
| - logic resp_queue_push; |
| - logic resp_queue_pop; |
| logic [31:0] resp_queue_data; |
| |
| localparam dm::dm_csr_e DataEnd = dm::dm_csr_e'(dm::Data0 + {4'h0, dm::DataCount} - 8'h1); |
| @@ -180,9 +177,6 @@ module dm_csrs #( |
| |
| // a successful response returns zero |
| assign dmi_resp_o.resp = dm::DTM_SUCCESS; |
| - assign dmi_resp_valid_o = ~resp_queue_empty; |
| - assign dmi_req_ready_o = ~resp_queue_full; |
| - assign resp_queue_push = dmi_req_valid_i & dmi_req_ready_o; |
| // SBA |
| assign sbautoincrement_o = sbcs_q.sbautoincrement; |
| assign sbreadonaddr_o = sbcs_q.sbreadonaddr; |
| @@ -554,27 +548,28 @@ module dm_csrs #( |
| assign progbuf_o = progbuf_q; |
| assign data_o = data_q; |
| |
| - assign resp_queue_pop = dmi_resp_ready_i & ~resp_queue_empty; |
| - |
| assign ndmreset_o = dmcontrol_q.ndmreset; |
| |
| + logic unused_testmode; |
| + assign unused_testmode = testmode_i; |
| + |
| // response FIFO |
| - fifo_v2 #( |
| - .dtype ( logic [31:0] ), |
| - .DEPTH ( 2 ) |
| + prim_fifo_sync #( |
| + .Width (32), |
| + .Pass (1'b0), |
| + .Depth (2) |
| ) i_fifo ( |
| - .clk_i ( clk_i ), |
| - .rst_ni ( dmi_rst_ni ), // reset only when system is re-set |
| - .flush_i ( 1'b0 ), // we do not need to flush this queue |
| - .testmode_i ( testmode_i ), |
| - .full_o ( resp_queue_full ), |
| - .empty_o ( resp_queue_empty ), |
| - .alm_full_o ( ), |
| - .alm_empty_o ( ), |
| - .data_i ( resp_queue_data ), |
| - .push_i ( resp_queue_push ), |
| - .data_o ( dmi_resp_o.data ), |
| - .pop_i ( resp_queue_pop ) |
| + .clk_i ( clk_i ), |
| + .rst_ni ( dmi_rst_ni ), // reset only when system is re-set |
| + .clr_i ( 1'b0 ), |
| + .wdata_i ( resp_queue_data ), |
| + .wvalid_i( dmi_req_valid_i ), |
| + .wready_o( dmi_req_ready_o ), |
| + .rdata_o ( dmi_resp_o.data ), |
| + .rvalid_o( dmi_resp_valid_o ), |
| + .rready_i( dmi_resp_ready_i ), |
| + .full_o ( ), // Unused |
| + .depth_o ( ) // Unused |
| ); |
| |
| always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs |
| diff --git a/src/dmi_cdc.sv b/src/dmi_cdc.sv |
| index 4665c91..1299b09 100644 |
| --- a/src/dmi_cdc.sv |
| +++ b/src/dmi_cdc.sv |
| @@ -42,32 +42,44 @@ module dmi_cdc ( |
| input logic core_dmi_valid_i |
| ); |
| |
| - cdc_2phase #(.T(dm::dmi_req_t)) i_cdc_req ( |
| - .src_rst_ni ( trst_ni ), |
| - .src_clk_i ( tck_i ), |
| - .src_data_i ( jtag_dmi_req_i ), |
| - .src_valid_i ( jtag_dmi_valid_i ), |
| - .src_ready_o ( jtag_dmi_ready_o ), |
| + // TODO: Make it clean for synthesis. |
| |
| - .dst_rst_ni ( rst_ni ), |
| - .dst_clk_i ( clk_i ), |
| - .dst_data_o ( core_dmi_req_o ), |
| - .dst_valid_o ( core_dmi_valid_o ), |
| - .dst_ready_i ( core_dmi_ready_i ) |
| + prim_fifo_async #( |
| + .Width ( $bits(dm::dmi_req_t) ), |
| + .Depth ( 4 ) |
| + ) i_cdc_req ( |
| + .clk_wr_i ( tck_i ), |
| + .rst_wr_ni ( trst_ni ), |
| + .wvalid_i ( jtag_dmi_valid_i ), |
| + .wready_o ( jtag_dmi_ready_o ), // wrclk |
| + .wdata_i ( jtag_dmi_req_i ), |
| + .wdepth_o ( ), |
| + |
| + .clk_rd_i ( clk_i ), |
| + .rst_rd_ni ( rst_ni ), |
| + .rvalid_o ( core_dmi_valid_o ), |
| + .rready_i ( core_dmi_ready_i ), |
| + .rdata_o ( core_dmi_req_o ), |
| + .rdepth_o ( ) |
| ); |
| |
| - cdc_2phase #(.T(dm::dmi_resp_t)) i_cdc_resp ( |
| - .src_rst_ni ( rst_ni ), |
| - .src_clk_i ( clk_i ), |
| - .src_data_i ( core_dmi_resp_i ), |
| - .src_valid_i ( core_dmi_valid_i ), |
| - .src_ready_o ( core_dmi_ready_o ), |
| + prim_fifo_async #( |
| + .Width ( $bits(dm::dmi_resp_t) ), |
| + .Depth ( 4 ) |
| + ) i_cdc_resp ( |
| + .clk_wr_i ( clk_i ), |
| + .rst_wr_ni ( rst_ni ), |
| + .wvalid_i ( core_dmi_valid_i ), |
| + .wready_o ( core_dmi_ready_o ), // wrclk |
| + .wdata_i ( core_dmi_resp_i ), |
| + .wdepth_o ( ), |
| |
| - .dst_rst_ni ( trst_ni ), |
| - .dst_clk_i ( tck_i ), |
| - .dst_data_o ( jtag_dmi_resp_o ), |
| - .dst_valid_o ( jtag_dmi_valid_o ), |
| - .dst_ready_i ( jtag_dmi_ready_i ) |
| + .clk_rd_i ( tck_i ), |
| + .rst_rd_ni ( trst_ni ), |
| + .rvalid_o ( jtag_dmi_valid_o ), |
| + .rready_i ( jtag_dmi_ready_i ), |
| + .rdata_o ( jtag_dmi_resp_o ), |
| + .rdepth_o ( ) |
| ); |
| |
| endmodule : dmi_cdc |
| diff --git a/src/dmi_jtag_tap.sv b/src/dmi_jtag_tap.sv |
| index c2e8d6e..5f10e6c 100644 |
| --- a/src/dmi_jtag_tap.sv |
| +++ b/src/dmi_jtag_tap.sv |
| @@ -216,18 +216,14 @@ module dmi_jtag_tap #( |
| // ---------------- |
| // DFT |
| // ---------------- |
| - logic tck_n, tck_ni; |
| - |
| - cluster_clock_inverter i_tck_inv ( |
| - .clk_i ( tck_i ), |
| - .clk_o ( tck_ni ) |
| - ); |
| - |
| - pulp_clock_mux2 i_dft_tck_mux ( |
| - .clk0_i ( tck_ni ), |
| - .clk1_i ( tck_i ), // bypass the inverted clock for testing |
| - .clk_sel_i ( testmode_i ), |
| - .clk_o ( tck_n ) |
| + logic tck_n; |
| + |
| + prim_clock_inv #( |
| + .HasScanMode(1'b1) |
| + ) i_tck_inv ( |
| + .clk_i ( tck_i ), |
| + .clk_no ( tck_n ), |
| + .scanmode_i ( testmode_i ) |
| ); |
| |
| // TDO changes state at negative edge of TCK |
