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opensecura / 3p / lowrisc / opentitan / c90e0c58a98990c1fc667f558c05db6367d5cc37 / . / hw / ip / pinmux / rtl / pinmux_reg_top.sv
blob: 9b45ebaa46405e90502f107d336745638b0801f7 [file] [log] [blame]
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `reggen`
`include "prim_assert.sv"
module pinmux_reg_top (
input clk_i,
input rst_ni,
// Below Regster interface can be changed
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
// To HW
output pinmux_reg_pkg::pinmux_reg2hw_t reg2hw, // Write
input pinmux_reg_pkg::pinmux_hw2reg_t hw2reg, // Read
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
import pinmux_reg_pkg::* ;
localparam int AW = 7;
localparam int DW = 32;
localparam int DBW = DW/8; // Byte Width
// register signals
logic reg_we;
logic reg_re;
logic [AW-1:0] reg_addr;
logic [DW-1:0] reg_wdata;
logic [DBW-1:0] reg_be;
logic [DW-1:0] reg_rdata;
logic reg_error;
logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
tlul_pkg::tl_h2d_t tl_reg_h2d;
tlul_pkg::tl_d2h_t tl_reg_d2h;
assign tl_reg_h2d = tl_i;
assign tl_o = tl_reg_d2h;
tlul_adapter_reg #(
.RegAw(AW),
.RegDw(DW)
) u_reg_if (
.clk_i,
.rst_ni,
.tl_i (tl_reg_h2d),
.tl_o (tl_reg_d2h),
.we_o (reg_we),
.re_o (reg_re),
.addr_o (reg_addr),
.wdata_o (reg_wdata),
.be_o (reg_be),
.rdata_i (reg_rdata),
.error_i (reg_error)
);
assign reg_rdata = reg_rdata_next ;
assign reg_error = (devmode_i & addrmiss) | wr_err ;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
logic regen_qs;
logic regen_wd;
logic regen_we;
logic [5:0] periph_insel_0_in_0_qs;
logic [5:0] periph_insel_0_in_0_wd;
logic periph_insel_0_in_0_we;
logic [5:0] periph_insel_0_in_1_qs;
logic [5:0] periph_insel_0_in_1_wd;
logic periph_insel_0_in_1_we;
logic [5:0] periph_insel_0_in_2_qs;
logic [5:0] periph_insel_0_in_2_wd;
logic periph_insel_0_in_2_we;
logic [5:0] periph_insel_0_in_3_qs;
logic [5:0] periph_insel_0_in_3_wd;
logic periph_insel_0_in_3_we;
logic [5:0] periph_insel_0_in_4_qs;
logic [5:0] periph_insel_0_in_4_wd;
logic periph_insel_0_in_4_we;
logic [5:0] periph_insel_1_in_5_qs;
logic [5:0] periph_insel_1_in_5_wd;
logic periph_insel_1_in_5_we;
logic [5:0] periph_insel_1_in_6_qs;
logic [5:0] periph_insel_1_in_6_wd;
logic periph_insel_1_in_6_we;
logic [5:0] periph_insel_1_in_7_qs;
logic [5:0] periph_insel_1_in_7_wd;
logic periph_insel_1_in_7_we;
logic [5:0] periph_insel_1_in_8_qs;
logic [5:0] periph_insel_1_in_8_wd;
logic periph_insel_1_in_8_we;
logic [5:0] periph_insel_1_in_9_qs;
logic [5:0] periph_insel_1_in_9_wd;
logic periph_insel_1_in_9_we;
logic [5:0] periph_insel_2_in_10_qs;
logic [5:0] periph_insel_2_in_10_wd;
logic periph_insel_2_in_10_we;
logic [5:0] periph_insel_2_in_11_qs;
logic [5:0] periph_insel_2_in_11_wd;
logic periph_insel_2_in_11_we;
logic [5:0] periph_insel_2_in_12_qs;
logic [5:0] periph_insel_2_in_12_wd;
logic periph_insel_2_in_12_we;
logic [5:0] periph_insel_2_in_13_qs;
logic [5:0] periph_insel_2_in_13_wd;
logic periph_insel_2_in_13_we;
logic [5:0] periph_insel_2_in_14_qs;
logic [5:0] periph_insel_2_in_14_wd;
logic periph_insel_2_in_14_we;
logic [5:0] periph_insel_3_in_15_qs;
logic [5:0] periph_insel_3_in_15_wd;
logic periph_insel_3_in_15_we;
logic [5:0] periph_insel_3_in_16_qs;
logic [5:0] periph_insel_3_in_16_wd;
logic periph_insel_3_in_16_we;
logic [5:0] periph_insel_3_in_17_qs;
logic [5:0] periph_insel_3_in_17_wd;
logic periph_insel_3_in_17_we;
logic [5:0] periph_insel_3_in_18_qs;
logic [5:0] periph_insel_3_in_18_wd;
logic periph_insel_3_in_18_we;
logic [5:0] periph_insel_3_in_19_qs;
logic [5:0] periph_insel_3_in_19_wd;
logic periph_insel_3_in_19_we;
logic [5:0] periph_insel_4_in_20_qs;
logic [5:0] periph_insel_4_in_20_wd;
logic periph_insel_4_in_20_we;
logic [5:0] periph_insel_4_in_21_qs;
logic [5:0] periph_insel_4_in_21_wd;
logic periph_insel_4_in_21_we;
logic [5:0] periph_insel_4_in_22_qs;
logic [5:0] periph_insel_4_in_22_wd;
logic periph_insel_4_in_22_we;
logic [5:0] periph_insel_4_in_23_qs;
logic [5:0] periph_insel_4_in_23_wd;
logic periph_insel_4_in_23_we;
logic [5:0] periph_insel_4_in_24_qs;
logic [5:0] periph_insel_4_in_24_wd;
logic periph_insel_4_in_24_we;
logic [5:0] periph_insel_5_in_25_qs;
logic [5:0] periph_insel_5_in_25_wd;
logic periph_insel_5_in_25_we;
logic [5:0] periph_insel_5_in_26_qs;
logic [5:0] periph_insel_5_in_26_wd;
logic periph_insel_5_in_26_we;
logic [5:0] periph_insel_5_in_27_qs;
logic [5:0] periph_insel_5_in_27_wd;
logic periph_insel_5_in_27_we;
logic [5:0] periph_insel_5_in_28_qs;
logic [5:0] periph_insel_5_in_28_wd;
logic periph_insel_5_in_28_we;
logic [5:0] periph_insel_5_in_29_qs;
logic [5:0] periph_insel_5_in_29_wd;
logic periph_insel_5_in_29_we;
logic [5:0] periph_insel_6_in_30_qs;
logic [5:0] periph_insel_6_in_30_wd;
logic periph_insel_6_in_30_we;
logic [5:0] periph_insel_6_in_31_qs;
logic [5:0] periph_insel_6_in_31_wd;
logic periph_insel_6_in_31_we;
logic [5:0] mio_outsel_0_out_0_qs;
logic [5:0] mio_outsel_0_out_0_wd;
logic mio_outsel_0_out_0_we;
logic [5:0] mio_outsel_0_out_1_qs;
logic [5:0] mio_outsel_0_out_1_wd;
logic mio_outsel_0_out_1_we;
logic [5:0] mio_outsel_0_out_2_qs;
logic [5:0] mio_outsel_0_out_2_wd;
logic mio_outsel_0_out_2_we;
logic [5:0] mio_outsel_0_out_3_qs;
logic [5:0] mio_outsel_0_out_3_wd;
logic mio_outsel_0_out_3_we;
logic [5:0] mio_outsel_0_out_4_qs;
logic [5:0] mio_outsel_0_out_4_wd;
logic mio_outsel_0_out_4_we;
logic [5:0] mio_outsel_1_out_5_qs;
logic [5:0] mio_outsel_1_out_5_wd;
logic mio_outsel_1_out_5_we;
logic [5:0] mio_outsel_1_out_6_qs;
logic [5:0] mio_outsel_1_out_6_wd;
logic mio_outsel_1_out_6_we;
logic [5:0] mio_outsel_1_out_7_qs;
logic [5:0] mio_outsel_1_out_7_wd;
logic mio_outsel_1_out_7_we;
logic [5:0] mio_outsel_1_out_8_qs;
logic [5:0] mio_outsel_1_out_8_wd;
logic mio_outsel_1_out_8_we;
logic [5:0] mio_outsel_1_out_9_qs;
logic [5:0] mio_outsel_1_out_9_wd;
logic mio_outsel_1_out_9_we;
logic [5:0] mio_outsel_2_out_10_qs;
logic [5:0] mio_outsel_2_out_10_wd;
logic mio_outsel_2_out_10_we;
logic [5:0] mio_outsel_2_out_11_qs;
logic [5:0] mio_outsel_2_out_11_wd;
logic mio_outsel_2_out_11_we;
logic [5:0] mio_outsel_2_out_12_qs;
logic [5:0] mio_outsel_2_out_12_wd;
logic mio_outsel_2_out_12_we;
logic [5:0] mio_outsel_2_out_13_qs;
logic [5:0] mio_outsel_2_out_13_wd;
logic mio_outsel_2_out_13_we;
logic [5:0] mio_outsel_2_out_14_qs;
logic [5:0] mio_outsel_2_out_14_wd;
logic mio_outsel_2_out_14_we;
logic [5:0] mio_outsel_3_out_15_qs;
logic [5:0] mio_outsel_3_out_15_wd;
logic mio_outsel_3_out_15_we;
logic [5:0] mio_outsel_3_out_16_qs;
logic [5:0] mio_outsel_3_out_16_wd;
logic mio_outsel_3_out_16_we;
logic [5:0] mio_outsel_3_out_17_qs;
logic [5:0] mio_outsel_3_out_17_wd;
logic mio_outsel_3_out_17_we;
logic [5:0] mio_outsel_3_out_18_qs;
logic [5:0] mio_outsel_3_out_18_wd;
logic mio_outsel_3_out_18_we;
logic [5:0] mio_outsel_3_out_19_qs;
logic [5:0] mio_outsel_3_out_19_wd;
logic mio_outsel_3_out_19_we;
logic [5:0] mio_outsel_4_out_20_qs;
logic [5:0] mio_outsel_4_out_20_wd;
logic mio_outsel_4_out_20_we;
logic [5:0] mio_outsel_4_out_21_qs;
logic [5:0] mio_outsel_4_out_21_wd;
logic mio_outsel_4_out_21_we;
logic [5:0] mio_outsel_4_out_22_qs;
logic [5:0] mio_outsel_4_out_22_wd;
logic mio_outsel_4_out_22_we;
logic [5:0] mio_outsel_4_out_23_qs;
logic [5:0] mio_outsel_4_out_23_wd;
logic mio_outsel_4_out_23_we;
logic [5:0] mio_outsel_4_out_24_qs;
logic [5:0] mio_outsel_4_out_24_wd;
logic mio_outsel_4_out_24_we;
logic [5:0] mio_outsel_5_out_25_qs;
logic [5:0] mio_outsel_5_out_25_wd;
logic mio_outsel_5_out_25_we;
logic [5:0] mio_outsel_5_out_26_qs;
logic [5:0] mio_outsel_5_out_26_wd;
logic mio_outsel_5_out_26_we;
logic [5:0] mio_outsel_5_out_27_qs;
logic [5:0] mio_outsel_5_out_27_wd;
logic mio_outsel_5_out_27_we;
logic [5:0] mio_outsel_5_out_28_qs;
logic [5:0] mio_outsel_5_out_28_wd;
logic mio_outsel_5_out_28_we;
logic [5:0] mio_outsel_5_out_29_qs;
logic [5:0] mio_outsel_5_out_29_wd;
logic mio_outsel_5_out_29_we;
logic [5:0] mio_outsel_6_out_30_qs;
logic [5:0] mio_outsel_6_out_30_wd;
logic mio_outsel_6_out_30_we;
logic [5:0] mio_outsel_6_out_31_qs;
logic [5:0] mio_outsel_6_out_31_wd;
logic mio_outsel_6_out_31_we;
logic [1:0] mio_out_sleep_val_0_out_0_qs;
logic [1:0] mio_out_sleep_val_0_out_0_wd;
logic mio_out_sleep_val_0_out_0_we;
logic [1:0] mio_out_sleep_val_0_out_1_qs;
logic [1:0] mio_out_sleep_val_0_out_1_wd;
logic mio_out_sleep_val_0_out_1_we;
logic [1:0] mio_out_sleep_val_0_out_2_qs;
logic [1:0] mio_out_sleep_val_0_out_2_wd;
logic mio_out_sleep_val_0_out_2_we;
logic [1:0] mio_out_sleep_val_0_out_3_qs;
logic [1:0] mio_out_sleep_val_0_out_3_wd;
logic mio_out_sleep_val_0_out_3_we;
logic [1:0] mio_out_sleep_val_0_out_4_qs;
logic [1:0] mio_out_sleep_val_0_out_4_wd;
logic mio_out_sleep_val_0_out_4_we;
logic [1:0] mio_out_sleep_val_0_out_5_qs;
logic [1:0] mio_out_sleep_val_0_out_5_wd;
logic mio_out_sleep_val_0_out_5_we;
logic [1:0] mio_out_sleep_val_0_out_6_qs;
logic [1:0] mio_out_sleep_val_0_out_6_wd;
logic mio_out_sleep_val_0_out_6_we;
logic [1:0] mio_out_sleep_val_0_out_7_qs;
logic [1:0] mio_out_sleep_val_0_out_7_wd;
logic mio_out_sleep_val_0_out_7_we;
logic [1:0] mio_out_sleep_val_0_out_8_qs;
logic [1:0] mio_out_sleep_val_0_out_8_wd;
logic mio_out_sleep_val_0_out_8_we;
logic [1:0] mio_out_sleep_val_0_out_9_qs;
logic [1:0] mio_out_sleep_val_0_out_9_wd;
logic mio_out_sleep_val_0_out_9_we;
logic [1:0] mio_out_sleep_val_0_out_10_qs;
logic [1:0] mio_out_sleep_val_0_out_10_wd;
logic mio_out_sleep_val_0_out_10_we;
logic [1:0] mio_out_sleep_val_0_out_11_qs;
logic [1:0] mio_out_sleep_val_0_out_11_wd;
logic mio_out_sleep_val_0_out_11_we;
logic [1:0] mio_out_sleep_val_0_out_12_qs;
logic [1:0] mio_out_sleep_val_0_out_12_wd;
logic mio_out_sleep_val_0_out_12_we;
logic [1:0] mio_out_sleep_val_0_out_13_qs;
logic [1:0] mio_out_sleep_val_0_out_13_wd;
logic mio_out_sleep_val_0_out_13_we;
logic [1:0] mio_out_sleep_val_0_out_14_qs;
logic [1:0] mio_out_sleep_val_0_out_14_wd;
logic mio_out_sleep_val_0_out_14_we;
logic [1:0] mio_out_sleep_val_0_out_15_qs;
logic [1:0] mio_out_sleep_val_0_out_15_wd;
logic mio_out_sleep_val_0_out_15_we;
logic [1:0] mio_out_sleep_val_1_out_16_qs;
logic [1:0] mio_out_sleep_val_1_out_16_wd;
logic mio_out_sleep_val_1_out_16_we;
logic [1:0] mio_out_sleep_val_1_out_17_qs;
logic [1:0] mio_out_sleep_val_1_out_17_wd;
logic mio_out_sleep_val_1_out_17_we;
logic [1:0] mio_out_sleep_val_1_out_18_qs;
logic [1:0] mio_out_sleep_val_1_out_18_wd;
logic mio_out_sleep_val_1_out_18_we;
logic [1:0] mio_out_sleep_val_1_out_19_qs;
logic [1:0] mio_out_sleep_val_1_out_19_wd;
logic mio_out_sleep_val_1_out_19_we;
logic [1:0] mio_out_sleep_val_1_out_20_qs;
logic [1:0] mio_out_sleep_val_1_out_20_wd;
logic mio_out_sleep_val_1_out_20_we;
logic [1:0] mio_out_sleep_val_1_out_21_qs;
logic [1:0] mio_out_sleep_val_1_out_21_wd;
logic mio_out_sleep_val_1_out_21_we;
logic [1:0] mio_out_sleep_val_1_out_22_qs;
logic [1:0] mio_out_sleep_val_1_out_22_wd;
logic mio_out_sleep_val_1_out_22_we;
logic [1:0] mio_out_sleep_val_1_out_23_qs;
logic [1:0] mio_out_sleep_val_1_out_23_wd;
logic mio_out_sleep_val_1_out_23_we;
logic [1:0] mio_out_sleep_val_1_out_24_qs;
logic [1:0] mio_out_sleep_val_1_out_24_wd;
logic mio_out_sleep_val_1_out_24_we;
logic [1:0] mio_out_sleep_val_1_out_25_qs;
logic [1:0] mio_out_sleep_val_1_out_25_wd;
logic mio_out_sleep_val_1_out_25_we;
logic [1:0] mio_out_sleep_val_1_out_26_qs;
logic [1:0] mio_out_sleep_val_1_out_26_wd;
logic mio_out_sleep_val_1_out_26_we;
logic [1:0] mio_out_sleep_val_1_out_27_qs;
logic [1:0] mio_out_sleep_val_1_out_27_wd;
logic mio_out_sleep_val_1_out_27_we;
logic [1:0] mio_out_sleep_val_1_out_28_qs;
logic [1:0] mio_out_sleep_val_1_out_28_wd;
logic mio_out_sleep_val_1_out_28_we;
logic [1:0] mio_out_sleep_val_1_out_29_qs;
logic [1:0] mio_out_sleep_val_1_out_29_wd;
logic mio_out_sleep_val_1_out_29_we;
logic [1:0] mio_out_sleep_val_1_out_30_qs;
logic [1:0] mio_out_sleep_val_1_out_30_wd;
logic mio_out_sleep_val_1_out_30_we;
logic [1:0] mio_out_sleep_val_1_out_31_qs;
logic [1:0] mio_out_sleep_val_1_out_31_wd;
logic mio_out_sleep_val_1_out_31_we;
logic [1:0] dio_out_sleep_val_out_0_qs;
logic [1:0] dio_out_sleep_val_out_0_wd;
logic dio_out_sleep_val_out_0_we;
logic dio_out_sleep_val_out_0_re;
logic [1:0] dio_out_sleep_val_out_1_qs;
logic [1:0] dio_out_sleep_val_out_1_wd;
logic dio_out_sleep_val_out_1_we;
logic dio_out_sleep_val_out_1_re;
logic [1:0] dio_out_sleep_val_out_2_qs;
logic [1:0] dio_out_sleep_val_out_2_wd;
logic dio_out_sleep_val_out_2_we;
logic dio_out_sleep_val_out_2_re;
logic [1:0] dio_out_sleep_val_out_3_qs;
logic [1:0] dio_out_sleep_val_out_3_wd;
logic dio_out_sleep_val_out_3_we;
logic dio_out_sleep_val_out_3_re;
logic [1:0] dio_out_sleep_val_out_4_qs;
logic [1:0] dio_out_sleep_val_out_4_wd;
logic dio_out_sleep_val_out_4_we;
logic dio_out_sleep_val_out_4_re;
logic [1:0] dio_out_sleep_val_out_5_qs;
logic [1:0] dio_out_sleep_val_out_5_wd;
logic dio_out_sleep_val_out_5_we;
logic dio_out_sleep_val_out_5_re;
logic [1:0] dio_out_sleep_val_out_6_qs;
logic [1:0] dio_out_sleep_val_out_6_wd;
logic dio_out_sleep_val_out_6_we;
logic dio_out_sleep_val_out_6_re;
logic [1:0] dio_out_sleep_val_out_7_qs;
logic [1:0] dio_out_sleep_val_out_7_wd;
logic dio_out_sleep_val_out_7_we;
logic dio_out_sleep_val_out_7_re;
logic [1:0] dio_out_sleep_val_out_8_qs;
logic [1:0] dio_out_sleep_val_out_8_wd;
logic dio_out_sleep_val_out_8_we;
logic dio_out_sleep_val_out_8_re;
logic [1:0] dio_out_sleep_val_out_9_qs;
logic [1:0] dio_out_sleep_val_out_9_wd;
logic dio_out_sleep_val_out_9_we;
logic dio_out_sleep_val_out_9_re;
logic [1:0] dio_out_sleep_val_out_10_qs;
logic [1:0] dio_out_sleep_val_out_10_wd;
logic dio_out_sleep_val_out_10_we;
logic dio_out_sleep_val_out_10_re;
logic [1:0] dio_out_sleep_val_out_11_qs;
logic [1:0] dio_out_sleep_val_out_11_wd;
logic dio_out_sleep_val_out_11_we;
logic dio_out_sleep_val_out_11_re;
logic [1:0] dio_out_sleep_val_out_12_qs;
logic [1:0] dio_out_sleep_val_out_12_wd;
logic dio_out_sleep_val_out_12_we;
logic dio_out_sleep_val_out_12_re;
logic [1:0] dio_out_sleep_val_out_13_qs;
logic [1:0] dio_out_sleep_val_out_13_wd;
logic dio_out_sleep_val_out_13_we;
logic dio_out_sleep_val_out_13_re;
logic [1:0] dio_out_sleep_val_out_14_qs;
logic [1:0] dio_out_sleep_val_out_14_wd;
logic dio_out_sleep_val_out_14_we;
logic dio_out_sleep_val_out_14_re;
logic [1:0] dio_out_sleep_val_out_15_qs;
logic [1:0] dio_out_sleep_val_out_15_wd;
logic dio_out_sleep_val_out_15_we;
logic dio_out_sleep_val_out_15_re;
logic wkup_detector_en_en_0_qs;
logic wkup_detector_en_en_0_wd;
logic wkup_detector_en_en_0_we;
logic wkup_detector_en_en_1_qs;
logic wkup_detector_en_en_1_wd;
logic wkup_detector_en_en_1_we;
logic wkup_detector_en_en_2_qs;
logic wkup_detector_en_en_2_wd;
logic wkup_detector_en_en_2_we;
logic wkup_detector_en_en_3_qs;
logic wkup_detector_en_en_3_wd;
logic wkup_detector_en_en_3_we;
logic wkup_detector_en_en_4_qs;
logic wkup_detector_en_en_4_wd;
logic wkup_detector_en_en_4_we;
logic wkup_detector_en_en_5_qs;
logic wkup_detector_en_en_5_wd;
logic wkup_detector_en_en_5_we;
logic wkup_detector_en_en_6_qs;
logic wkup_detector_en_en_6_wd;
logic wkup_detector_en_en_6_we;
logic wkup_detector_en_en_7_qs;
logic wkup_detector_en_en_7_wd;
logic wkup_detector_en_en_7_we;
logic [2:0] wkup_detector_0_mode_0_qs;
logic [2:0] wkup_detector_0_mode_0_wd;
logic wkup_detector_0_mode_0_we;
logic wkup_detector_0_filter_0_qs;
logic wkup_detector_0_filter_0_wd;
logic wkup_detector_0_filter_0_we;
logic wkup_detector_0_miodio_0_qs;
logic wkup_detector_0_miodio_0_wd;
logic wkup_detector_0_miodio_0_we;
logic [2:0] wkup_detector_1_mode_1_qs;
logic [2:0] wkup_detector_1_mode_1_wd;
logic wkup_detector_1_mode_1_we;
logic wkup_detector_1_filter_1_qs;
logic wkup_detector_1_filter_1_wd;
logic wkup_detector_1_filter_1_we;
logic wkup_detector_1_miodio_1_qs;
logic wkup_detector_1_miodio_1_wd;
logic wkup_detector_1_miodio_1_we;
logic [2:0] wkup_detector_2_mode_2_qs;
logic [2:0] wkup_detector_2_mode_2_wd;
logic wkup_detector_2_mode_2_we;
logic wkup_detector_2_filter_2_qs;
logic wkup_detector_2_filter_2_wd;
logic wkup_detector_2_filter_2_we;
logic wkup_detector_2_miodio_2_qs;
logic wkup_detector_2_miodio_2_wd;
logic wkup_detector_2_miodio_2_we;
logic [2:0] wkup_detector_3_mode_3_qs;
logic [2:0] wkup_detector_3_mode_3_wd;
logic wkup_detector_3_mode_3_we;
logic wkup_detector_3_filter_3_qs;
logic wkup_detector_3_filter_3_wd;
logic wkup_detector_3_filter_3_we;
logic wkup_detector_3_miodio_3_qs;
logic wkup_detector_3_miodio_3_wd;
logic wkup_detector_3_miodio_3_we;
logic [2:0] wkup_detector_4_mode_4_qs;
logic [2:0] wkup_detector_4_mode_4_wd;
logic wkup_detector_4_mode_4_we;
logic wkup_detector_4_filter_4_qs;
logic wkup_detector_4_filter_4_wd;
logic wkup_detector_4_filter_4_we;
logic wkup_detector_4_miodio_4_qs;
logic wkup_detector_4_miodio_4_wd;
logic wkup_detector_4_miodio_4_we;
logic [2:0] wkup_detector_5_mode_5_qs;
logic [2:0] wkup_detector_5_mode_5_wd;
logic wkup_detector_5_mode_5_we;
logic wkup_detector_5_filter_5_qs;
logic wkup_detector_5_filter_5_wd;
logic wkup_detector_5_filter_5_we;
logic wkup_detector_5_miodio_5_qs;
logic wkup_detector_5_miodio_5_wd;
logic wkup_detector_5_miodio_5_we;
logic [2:0] wkup_detector_6_mode_6_qs;
logic [2:0] wkup_detector_6_mode_6_wd;
logic wkup_detector_6_mode_6_we;
logic wkup_detector_6_filter_6_qs;
logic wkup_detector_6_filter_6_wd;
logic wkup_detector_6_filter_6_we;
logic wkup_detector_6_miodio_6_qs;
logic wkup_detector_6_miodio_6_wd;
logic wkup_detector_6_miodio_6_we;
logic [2:0] wkup_detector_7_mode_7_qs;
logic [2:0] wkup_detector_7_mode_7_wd;
logic wkup_detector_7_mode_7_we;
logic wkup_detector_7_filter_7_qs;
logic wkup_detector_7_filter_7_wd;
logic wkup_detector_7_filter_7_we;
logic wkup_detector_7_miodio_7_qs;
logic wkup_detector_7_miodio_7_wd;
logic wkup_detector_7_miodio_7_we;
logic [7:0] wkup_detector_cnt_th_0_th_0_qs;
logic [7:0] wkup_detector_cnt_th_0_th_0_wd;
logic wkup_detector_cnt_th_0_th_0_we;
logic [7:0] wkup_detector_cnt_th_0_th_1_qs;
logic [7:0] wkup_detector_cnt_th_0_th_1_wd;
logic wkup_detector_cnt_th_0_th_1_we;
logic [7:0] wkup_detector_cnt_th_0_th_2_qs;
logic [7:0] wkup_detector_cnt_th_0_th_2_wd;
logic wkup_detector_cnt_th_0_th_2_we;
logic [7:0] wkup_detector_cnt_th_0_th_3_qs;
logic [7:0] wkup_detector_cnt_th_0_th_3_wd;
logic wkup_detector_cnt_th_0_th_3_we;
logic [7:0] wkup_detector_cnt_th_1_th_4_qs;
logic [7:0] wkup_detector_cnt_th_1_th_4_wd;
logic wkup_detector_cnt_th_1_th_4_we;
logic [7:0] wkup_detector_cnt_th_1_th_5_qs;
logic [7:0] wkup_detector_cnt_th_1_th_5_wd;
logic wkup_detector_cnt_th_1_th_5_we;
logic [7:0] wkup_detector_cnt_th_1_th_6_qs;
logic [7:0] wkup_detector_cnt_th_1_th_6_wd;
logic wkup_detector_cnt_th_1_th_6_we;
logic [7:0] wkup_detector_cnt_th_1_th_7_qs;
logic [7:0] wkup_detector_cnt_th_1_th_7_wd;
logic wkup_detector_cnt_th_1_th_7_we;
logic [4:0] wkup_detector_padsel_0_sel_0_qs;
logic [4:0] wkup_detector_padsel_0_sel_0_wd;
logic wkup_detector_padsel_0_sel_0_we;
logic [4:0] wkup_detector_padsel_0_sel_1_qs;
logic [4:0] wkup_detector_padsel_0_sel_1_wd;
logic wkup_detector_padsel_0_sel_1_we;
logic [4:0] wkup_detector_padsel_0_sel_2_qs;
logic [4:0] wkup_detector_padsel_0_sel_2_wd;
logic wkup_detector_padsel_0_sel_2_we;
logic [4:0] wkup_detector_padsel_0_sel_3_qs;
logic [4:0] wkup_detector_padsel_0_sel_3_wd;
logic wkup_detector_padsel_0_sel_3_we;
logic [4:0] wkup_detector_padsel_0_sel_4_qs;
logic [4:0] wkup_detector_padsel_0_sel_4_wd;
logic wkup_detector_padsel_0_sel_4_we;
logic [4:0] wkup_detector_padsel_0_sel_5_qs;
logic [4:0] wkup_detector_padsel_0_sel_5_wd;
logic wkup_detector_padsel_0_sel_5_we;
logic [4:0] wkup_detector_padsel_1_sel_6_qs;
logic [4:0] wkup_detector_padsel_1_sel_6_wd;
logic wkup_detector_padsel_1_sel_6_we;
logic [4:0] wkup_detector_padsel_1_sel_7_qs;
logic [4:0] wkup_detector_padsel_1_sel_7_wd;
logic wkup_detector_padsel_1_sel_7_we;
logic wkup_cause_cause_0_qs;
logic wkup_cause_cause_0_wd;
logic wkup_cause_cause_0_we;
logic wkup_cause_cause_0_re;
logic wkup_cause_cause_1_qs;
logic wkup_cause_cause_1_wd;
logic wkup_cause_cause_1_we;
logic wkup_cause_cause_1_re;
logic wkup_cause_cause_2_qs;
logic wkup_cause_cause_2_wd;
logic wkup_cause_cause_2_we;
logic wkup_cause_cause_2_re;
logic wkup_cause_cause_3_qs;
logic wkup_cause_cause_3_wd;
logic wkup_cause_cause_3_we;
logic wkup_cause_cause_3_re;
logic wkup_cause_cause_4_qs;
logic wkup_cause_cause_4_wd;
logic wkup_cause_cause_4_we;
logic wkup_cause_cause_4_re;
logic wkup_cause_cause_5_qs;
logic wkup_cause_cause_5_wd;
logic wkup_cause_cause_5_we;
logic wkup_cause_cause_5_re;
logic wkup_cause_cause_6_qs;
logic wkup_cause_cause_6_wd;
logic wkup_cause_cause_6_we;
logic wkup_cause_cause_6_re;
logic wkup_cause_cause_7_qs;
logic wkup_cause_cause_7_wd;
logic wkup_cause_cause_7_we;
logic wkup_cause_cause_7_re;
// Register instances
// R[regen]: V(False)
prim_subreg #(
.DW (1),
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_regen (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
.we (regen_we),
.wd (regen_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
.qs (regen_qs)
);
// Subregister 0 of Multireg periph_insel
// R[periph_insel_0]: V(False)
// F[in_0]: 5:0
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_0_in_0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_0_in_0_we & regen_qs),
.wd (periph_insel_0_in_0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[0].q ),
// to register interface (read)
.qs (periph_insel_0_in_0_qs)
);
// F[in_1]: 11:6
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_0_in_1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_0_in_1_we & regen_qs),
.wd (periph_insel_0_in_1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[1].q ),
// to register interface (read)
.qs (periph_insel_0_in_1_qs)
);
// F[in_2]: 17:12
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_0_in_2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_0_in_2_we & regen_qs),
.wd (periph_insel_0_in_2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[2].q ),
// to register interface (read)
.qs (periph_insel_0_in_2_qs)
);
// F[in_3]: 23:18
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_0_in_3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_0_in_3_we & regen_qs),
.wd (periph_insel_0_in_3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[3].q ),
// to register interface (read)
.qs (periph_insel_0_in_3_qs)
);
// F[in_4]: 29:24
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_0_in_4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_0_in_4_we & regen_qs),
.wd (periph_insel_0_in_4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[4].q ),
// to register interface (read)
.qs (periph_insel_0_in_4_qs)
);
// Subregister 5 of Multireg periph_insel
// R[periph_insel_1]: V(False)
// F[in_5]: 5:0
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_1_in_5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_1_in_5_we & regen_qs),
.wd (periph_insel_1_in_5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[5].q ),
// to register interface (read)
.qs (periph_insel_1_in_5_qs)
);
// F[in_6]: 11:6
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_1_in_6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_1_in_6_we & regen_qs),
.wd (periph_insel_1_in_6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[6].q ),
// to register interface (read)
.qs (periph_insel_1_in_6_qs)
);
// F[in_7]: 17:12
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_1_in_7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_1_in_7_we & regen_qs),
.wd (periph_insel_1_in_7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[7].q ),
// to register interface (read)
.qs (periph_insel_1_in_7_qs)
);
// F[in_8]: 23:18
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_1_in_8 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_1_in_8_we & regen_qs),
.wd (periph_insel_1_in_8_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[8].q ),
// to register interface (read)
.qs (periph_insel_1_in_8_qs)
);
// F[in_9]: 29:24
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_1_in_9 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_1_in_9_we & regen_qs),
.wd (periph_insel_1_in_9_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[9].q ),
// to register interface (read)
.qs (periph_insel_1_in_9_qs)
);
// Subregister 10 of Multireg periph_insel
// R[periph_insel_2]: V(False)
// F[in_10]: 5:0
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_2_in_10 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_2_in_10_we & regen_qs),
.wd (periph_insel_2_in_10_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[10].q ),
// to register interface (read)
.qs (periph_insel_2_in_10_qs)
);
// F[in_11]: 11:6
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_2_in_11 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_2_in_11_we & regen_qs),
.wd (periph_insel_2_in_11_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[11].q ),
// to register interface (read)
.qs (periph_insel_2_in_11_qs)
);
// F[in_12]: 17:12
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_2_in_12 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_2_in_12_we & regen_qs),
.wd (periph_insel_2_in_12_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[12].q ),
// to register interface (read)
.qs (periph_insel_2_in_12_qs)
);
// F[in_13]: 23:18
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_2_in_13 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_2_in_13_we & regen_qs),
.wd (periph_insel_2_in_13_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[13].q ),
// to register interface (read)
.qs (periph_insel_2_in_13_qs)
);
// F[in_14]: 29:24
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_2_in_14 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_2_in_14_we & regen_qs),
.wd (periph_insel_2_in_14_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[14].q ),
// to register interface (read)
.qs (periph_insel_2_in_14_qs)
);
// Subregister 15 of Multireg periph_insel
// R[periph_insel_3]: V(False)
// F[in_15]: 5:0
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_3_in_15 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_3_in_15_we & regen_qs),
.wd (periph_insel_3_in_15_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[15].q ),
// to register interface (read)
.qs (periph_insel_3_in_15_qs)
);
// F[in_16]: 11:6
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_3_in_16 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_3_in_16_we & regen_qs),
.wd (periph_insel_3_in_16_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[16].q ),
// to register interface (read)
.qs (periph_insel_3_in_16_qs)
);
// F[in_17]: 17:12
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_3_in_17 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_3_in_17_we & regen_qs),
.wd (periph_insel_3_in_17_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[17].q ),
// to register interface (read)
.qs (periph_insel_3_in_17_qs)
);
// F[in_18]: 23:18
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_3_in_18 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_3_in_18_we & regen_qs),
.wd (periph_insel_3_in_18_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[18].q ),
// to register interface (read)
.qs (periph_insel_3_in_18_qs)
);
// F[in_19]: 29:24
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_3_in_19 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_3_in_19_we & regen_qs),
.wd (periph_insel_3_in_19_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[19].q ),
// to register interface (read)
.qs (periph_insel_3_in_19_qs)
);
// Subregister 20 of Multireg periph_insel
// R[periph_insel_4]: V(False)
// F[in_20]: 5:0
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_4_in_20 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_4_in_20_we & regen_qs),
.wd (periph_insel_4_in_20_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[20].q ),
// to register interface (read)
.qs (periph_insel_4_in_20_qs)
);
// F[in_21]: 11:6
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_4_in_21 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_4_in_21_we & regen_qs),
.wd (periph_insel_4_in_21_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[21].q ),
// to register interface (read)
.qs (periph_insel_4_in_21_qs)
);
// F[in_22]: 17:12
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_4_in_22 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_4_in_22_we & regen_qs),
.wd (periph_insel_4_in_22_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[22].q ),
// to register interface (read)
.qs (periph_insel_4_in_22_qs)
);
// F[in_23]: 23:18
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_4_in_23 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_4_in_23_we & regen_qs),
.wd (periph_insel_4_in_23_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[23].q ),
// to register interface (read)
.qs (periph_insel_4_in_23_qs)
);
// F[in_24]: 29:24
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_4_in_24 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_4_in_24_we & regen_qs),
.wd (periph_insel_4_in_24_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[24].q ),
// to register interface (read)
.qs (periph_insel_4_in_24_qs)
);
// Subregister 25 of Multireg periph_insel
// R[periph_insel_5]: V(False)
// F[in_25]: 5:0
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_5_in_25 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_5_in_25_we & regen_qs),
.wd (periph_insel_5_in_25_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[25].q ),
// to register interface (read)
.qs (periph_insel_5_in_25_qs)
);
// F[in_26]: 11:6
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_5_in_26 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_5_in_26_we & regen_qs),
.wd (periph_insel_5_in_26_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[26].q ),
// to register interface (read)
.qs (periph_insel_5_in_26_qs)
);
// F[in_27]: 17:12
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_5_in_27 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_5_in_27_we & regen_qs),
.wd (periph_insel_5_in_27_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[27].q ),
// to register interface (read)
.qs (periph_insel_5_in_27_qs)
);
// F[in_28]: 23:18
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_5_in_28 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_5_in_28_we & regen_qs),
.wd (periph_insel_5_in_28_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[28].q ),
// to register interface (read)
.qs (periph_insel_5_in_28_qs)
);
// F[in_29]: 29:24
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_5_in_29 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_5_in_29_we & regen_qs),
.wd (periph_insel_5_in_29_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[29].q ),
// to register interface (read)
.qs (periph_insel_5_in_29_qs)
);
// Subregister 30 of Multireg periph_insel
// R[periph_insel_6]: V(False)
// F[in_30]: 5:0
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_6_in_30 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_6_in_30_we & regen_qs),
.wd (periph_insel_6_in_30_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[30].q ),
// to register interface (read)
.qs (periph_insel_6_in_30_qs)
);
// F[in_31]: 11:6
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_periph_insel_6_in_31 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (periph_insel_6_in_31_we & regen_qs),
.wd (periph_insel_6_in_31_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.periph_insel[31].q ),
// to register interface (read)
.qs (periph_insel_6_in_31_qs)
);
// Subregister 0 of Multireg mio_outsel
// R[mio_outsel_0]: V(False)
// F[out_0]: 5:0
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_0_out_0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_0_out_0_we & regen_qs),
.wd (mio_outsel_0_out_0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[0].q ),
// to register interface (read)
.qs (mio_outsel_0_out_0_qs)
);
// F[out_1]: 11:6
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_0_out_1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_0_out_1_we & regen_qs),
.wd (mio_outsel_0_out_1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[1].q ),
// to register interface (read)
.qs (mio_outsel_0_out_1_qs)
);
// F[out_2]: 17:12
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_0_out_2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_0_out_2_we & regen_qs),
.wd (mio_outsel_0_out_2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[2].q ),
// to register interface (read)
.qs (mio_outsel_0_out_2_qs)
);
// F[out_3]: 23:18
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_0_out_3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_0_out_3_we & regen_qs),
.wd (mio_outsel_0_out_3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[3].q ),
// to register interface (read)
.qs (mio_outsel_0_out_3_qs)
);
// F[out_4]: 29:24
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_0_out_4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_0_out_4_we & regen_qs),
.wd (mio_outsel_0_out_4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[4].q ),
// to register interface (read)
.qs (mio_outsel_0_out_4_qs)
);
// Subregister 5 of Multireg mio_outsel
// R[mio_outsel_1]: V(False)
// F[out_5]: 5:0
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_1_out_5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_1_out_5_we & regen_qs),
.wd (mio_outsel_1_out_5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[5].q ),
// to register interface (read)
.qs (mio_outsel_1_out_5_qs)
);
// F[out_6]: 11:6
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_1_out_6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_1_out_6_we & regen_qs),
.wd (mio_outsel_1_out_6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[6].q ),
// to register interface (read)
.qs (mio_outsel_1_out_6_qs)
);
// F[out_7]: 17:12
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_1_out_7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_1_out_7_we & regen_qs),
.wd (mio_outsel_1_out_7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[7].q ),
// to register interface (read)
.qs (mio_outsel_1_out_7_qs)
);
// F[out_8]: 23:18
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_1_out_8 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_1_out_8_we & regen_qs),
.wd (mio_outsel_1_out_8_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[8].q ),
// to register interface (read)
.qs (mio_outsel_1_out_8_qs)
);
// F[out_9]: 29:24
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_1_out_9 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_1_out_9_we & regen_qs),
.wd (mio_outsel_1_out_9_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[9].q ),
// to register interface (read)
.qs (mio_outsel_1_out_9_qs)
);
// Subregister 10 of Multireg mio_outsel
// R[mio_outsel_2]: V(False)
// F[out_10]: 5:0
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_2_out_10 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_2_out_10_we & regen_qs),
.wd (mio_outsel_2_out_10_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[10].q ),
// to register interface (read)
.qs (mio_outsel_2_out_10_qs)
);
// F[out_11]: 11:6
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_2_out_11 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_2_out_11_we & regen_qs),
.wd (mio_outsel_2_out_11_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[11].q ),
// to register interface (read)
.qs (mio_outsel_2_out_11_qs)
);
// F[out_12]: 17:12
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_2_out_12 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_2_out_12_we & regen_qs),
.wd (mio_outsel_2_out_12_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[12].q ),
// to register interface (read)
.qs (mio_outsel_2_out_12_qs)
);
// F[out_13]: 23:18
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_2_out_13 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_2_out_13_we & regen_qs),
.wd (mio_outsel_2_out_13_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[13].q ),
// to register interface (read)
.qs (mio_outsel_2_out_13_qs)
);
// F[out_14]: 29:24
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_2_out_14 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_2_out_14_we & regen_qs),
.wd (mio_outsel_2_out_14_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[14].q ),
// to register interface (read)
.qs (mio_outsel_2_out_14_qs)
);
// Subregister 15 of Multireg mio_outsel
// R[mio_outsel_3]: V(False)
// F[out_15]: 5:0
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_3_out_15 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_3_out_15_we & regen_qs),
.wd (mio_outsel_3_out_15_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[15].q ),
// to register interface (read)
.qs (mio_outsel_3_out_15_qs)
);
// F[out_16]: 11:6
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_3_out_16 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_3_out_16_we & regen_qs),
.wd (mio_outsel_3_out_16_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[16].q ),
// to register interface (read)
.qs (mio_outsel_3_out_16_qs)
);
// F[out_17]: 17:12
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_3_out_17 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_3_out_17_we & regen_qs),
.wd (mio_outsel_3_out_17_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[17].q ),
// to register interface (read)
.qs (mio_outsel_3_out_17_qs)
);
// F[out_18]: 23:18
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_3_out_18 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_3_out_18_we & regen_qs),
.wd (mio_outsel_3_out_18_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[18].q ),
// to register interface (read)
.qs (mio_outsel_3_out_18_qs)
);
// F[out_19]: 29:24
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_3_out_19 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_3_out_19_we & regen_qs),
.wd (mio_outsel_3_out_19_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[19].q ),
// to register interface (read)
.qs (mio_outsel_3_out_19_qs)
);
// Subregister 20 of Multireg mio_outsel
// R[mio_outsel_4]: V(False)
// F[out_20]: 5:0
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_4_out_20 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_4_out_20_we & regen_qs),
.wd (mio_outsel_4_out_20_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[20].q ),
// to register interface (read)
.qs (mio_outsel_4_out_20_qs)
);
// F[out_21]: 11:6
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_4_out_21 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_4_out_21_we & regen_qs),
.wd (mio_outsel_4_out_21_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[21].q ),
// to register interface (read)
.qs (mio_outsel_4_out_21_qs)
);
// F[out_22]: 17:12
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_4_out_22 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_4_out_22_we & regen_qs),
.wd (mio_outsel_4_out_22_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[22].q ),
// to register interface (read)
.qs (mio_outsel_4_out_22_qs)
);
// F[out_23]: 23:18
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_4_out_23 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_4_out_23_we & regen_qs),
.wd (mio_outsel_4_out_23_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[23].q ),
// to register interface (read)
.qs (mio_outsel_4_out_23_qs)
);
// F[out_24]: 29:24
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_4_out_24 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_4_out_24_we & regen_qs),
.wd (mio_outsel_4_out_24_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[24].q ),
// to register interface (read)
.qs (mio_outsel_4_out_24_qs)
);
// Subregister 25 of Multireg mio_outsel
// R[mio_outsel_5]: V(False)
// F[out_25]: 5:0
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_5_out_25 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_5_out_25_we & regen_qs),
.wd (mio_outsel_5_out_25_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[25].q ),
// to register interface (read)
.qs (mio_outsel_5_out_25_qs)
);
// F[out_26]: 11:6
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_5_out_26 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_5_out_26_we & regen_qs),
.wd (mio_outsel_5_out_26_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[26].q ),
// to register interface (read)
.qs (mio_outsel_5_out_26_qs)
);
// F[out_27]: 17:12
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_5_out_27 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_5_out_27_we & regen_qs),
.wd (mio_outsel_5_out_27_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[27].q ),
// to register interface (read)
.qs (mio_outsel_5_out_27_qs)
);
// F[out_28]: 23:18
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_5_out_28 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_5_out_28_we & regen_qs),
.wd (mio_outsel_5_out_28_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[28].q ),
// to register interface (read)
.qs (mio_outsel_5_out_28_qs)
);
// F[out_29]: 29:24
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_5_out_29 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_5_out_29_we & regen_qs),
.wd (mio_outsel_5_out_29_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[29].q ),
// to register interface (read)
.qs (mio_outsel_5_out_29_qs)
);
// Subregister 30 of Multireg mio_outsel
// R[mio_outsel_6]: V(False)
// F[out_30]: 5:0
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_6_out_30 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_6_out_30_we & regen_qs),
.wd (mio_outsel_6_out_30_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[30].q ),
// to register interface (read)
.qs (mio_outsel_6_out_30_qs)
);
// F[out_31]: 11:6
prim_subreg #(
.DW (6),
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_6_out_31 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_outsel_6_out_31_we & regen_qs),
.wd (mio_outsel_6_out_31_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_outsel[31].q ),
// to register interface (read)
.qs (mio_outsel_6_out_31_qs)
);
// Subregister 0 of Multireg mio_out_sleep_val
// R[mio_out_sleep_val_0]: V(False)
// F[out_0]: 1:0
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_0_we & regen_qs),
.wd (mio_out_sleep_val_0_out_0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[0].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_0_qs)
);
// F[out_1]: 3:2
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_1_we & regen_qs),
.wd (mio_out_sleep_val_0_out_1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[1].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_1_qs)
);
// F[out_2]: 5:4
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_2_we & regen_qs),
.wd (mio_out_sleep_val_0_out_2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[2].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_2_qs)
);
// F[out_3]: 7:6
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_3_we & regen_qs),
.wd (mio_out_sleep_val_0_out_3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[3].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_3_qs)
);
// F[out_4]: 9:8
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_4_we & regen_qs),
.wd (mio_out_sleep_val_0_out_4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[4].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_4_qs)
);
// F[out_5]: 11:10
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_5_we & regen_qs),
.wd (mio_out_sleep_val_0_out_5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[5].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_5_qs)
);
// F[out_6]: 13:12
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_6_we & regen_qs),
.wd (mio_out_sleep_val_0_out_6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[6].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_6_qs)
);
// F[out_7]: 15:14
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_7_we & regen_qs),
.wd (mio_out_sleep_val_0_out_7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[7].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_7_qs)
);
// F[out_8]: 17:16
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_8 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_8_we & regen_qs),
.wd (mio_out_sleep_val_0_out_8_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[8].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_8_qs)
);
// F[out_9]: 19:18
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_9 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_9_we & regen_qs),
.wd (mio_out_sleep_val_0_out_9_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[9].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_9_qs)
);
// F[out_10]: 21:20
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_10 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_10_we & regen_qs),
.wd (mio_out_sleep_val_0_out_10_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[10].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_10_qs)
);
// F[out_11]: 23:22
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_11 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_11_we & regen_qs),
.wd (mio_out_sleep_val_0_out_11_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[11].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_11_qs)
);
// F[out_12]: 25:24
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_12 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_12_we & regen_qs),
.wd (mio_out_sleep_val_0_out_12_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[12].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_12_qs)
);
// F[out_13]: 27:26
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_13 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_13_we & regen_qs),
.wd (mio_out_sleep_val_0_out_13_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[13].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_13_qs)
);
// F[out_14]: 29:28
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_14 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_14_we & regen_qs),
.wd (mio_out_sleep_val_0_out_14_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[14].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_14_qs)
);
// F[out_15]: 31:30
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_0_out_15 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_0_out_15_we & regen_qs),
.wd (mio_out_sleep_val_0_out_15_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[15].q ),
// to register interface (read)
.qs (mio_out_sleep_val_0_out_15_qs)
);
// Subregister 16 of Multireg mio_out_sleep_val
// R[mio_out_sleep_val_1]: V(False)
// F[out_16]: 1:0
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_16 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_16_we & regen_qs),
.wd (mio_out_sleep_val_1_out_16_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[16].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_16_qs)
);
// F[out_17]: 3:2
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_17 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_17_we & regen_qs),
.wd (mio_out_sleep_val_1_out_17_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[17].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_17_qs)
);
// F[out_18]: 5:4
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_18 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_18_we & regen_qs),
.wd (mio_out_sleep_val_1_out_18_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[18].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_18_qs)
);
// F[out_19]: 7:6
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_19 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_19_we & regen_qs),
.wd (mio_out_sleep_val_1_out_19_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[19].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_19_qs)
);
// F[out_20]: 9:8
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_20 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_20_we & regen_qs),
.wd (mio_out_sleep_val_1_out_20_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[20].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_20_qs)
);
// F[out_21]: 11:10
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_21 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_21_we & regen_qs),
.wd (mio_out_sleep_val_1_out_21_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[21].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_21_qs)
);
// F[out_22]: 13:12
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_22 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_22_we & regen_qs),
.wd (mio_out_sleep_val_1_out_22_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[22].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_22_qs)
);
// F[out_23]: 15:14
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_23 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_23_we & regen_qs),
.wd (mio_out_sleep_val_1_out_23_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[23].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_23_qs)
);
// F[out_24]: 17:16
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_24 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_24_we & regen_qs),
.wd (mio_out_sleep_val_1_out_24_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[24].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_24_qs)
);
// F[out_25]: 19:18
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_25 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_25_we & regen_qs),
.wd (mio_out_sleep_val_1_out_25_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[25].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_25_qs)
);
// F[out_26]: 21:20
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_26 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_26_we & regen_qs),
.wd (mio_out_sleep_val_1_out_26_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[26].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_26_qs)
);
// F[out_27]: 23:22
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_27 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_27_we & regen_qs),
.wd (mio_out_sleep_val_1_out_27_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[27].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_27_qs)
);
// F[out_28]: 25:24
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_28 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_28_we & regen_qs),
.wd (mio_out_sleep_val_1_out_28_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[28].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_28_qs)
);
// F[out_29]: 27:26
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_29 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_29_we & regen_qs),
.wd (mio_out_sleep_val_1_out_29_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[29].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_29_qs)
);
// F[out_30]: 29:28
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_30 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_30_we & regen_qs),
.wd (mio_out_sleep_val_1_out_30_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[30].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_30_qs)
);
// F[out_31]: 31:30
prim_subreg #(
.DW (2),
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_out_sleep_val_1_out_31 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (mio_out_sleep_val_1_out_31_we & regen_qs),
.wd (mio_out_sleep_val_1_out_31_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.mio_out_sleep_val[31].q ),
// to register interface (read)
.qs (mio_out_sleep_val_1_out_31_qs)
);
// Subregister 0 of Multireg dio_out_sleep_val
// R[dio_out_sleep_val]: V(True)
// F[out_0]: 1:0
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_0 (
.re (dio_out_sleep_val_out_0_re),
// qualified with register enable
.we (dio_out_sleep_val_out_0_we & regen_qs),
.wd (dio_out_sleep_val_out_0_wd),
.d (hw2reg.dio_out_sleep_val[0].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[0].qe),
.q (reg2hw.dio_out_sleep_val[0].q ),
.qs (dio_out_sleep_val_out_0_qs)
);
// F[out_1]: 3:2
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_1 (
.re (dio_out_sleep_val_out_1_re),
// qualified with register enable
.we (dio_out_sleep_val_out_1_we & regen_qs),
.wd (dio_out_sleep_val_out_1_wd),
.d (hw2reg.dio_out_sleep_val[1].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[1].qe),
.q (reg2hw.dio_out_sleep_val[1].q ),
.qs (dio_out_sleep_val_out_1_qs)
);
// F[out_2]: 5:4
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_2 (
.re (dio_out_sleep_val_out_2_re),
// qualified with register enable
.we (dio_out_sleep_val_out_2_we & regen_qs),
.wd (dio_out_sleep_val_out_2_wd),
.d (hw2reg.dio_out_sleep_val[2].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[2].qe),
.q (reg2hw.dio_out_sleep_val[2].q ),
.qs (dio_out_sleep_val_out_2_qs)
);
// F[out_3]: 7:6
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_3 (
.re (dio_out_sleep_val_out_3_re),
// qualified with register enable
.we (dio_out_sleep_val_out_3_we & regen_qs),
.wd (dio_out_sleep_val_out_3_wd),
.d (hw2reg.dio_out_sleep_val[3].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[3].qe),
.q (reg2hw.dio_out_sleep_val[3].q ),
.qs (dio_out_sleep_val_out_3_qs)
);
// F[out_4]: 9:8
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_4 (
.re (dio_out_sleep_val_out_4_re),
// qualified with register enable
.we (dio_out_sleep_val_out_4_we & regen_qs),
.wd (dio_out_sleep_val_out_4_wd),
.d (hw2reg.dio_out_sleep_val[4].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[4].qe),
.q (reg2hw.dio_out_sleep_val[4].q ),
.qs (dio_out_sleep_val_out_4_qs)
);
// F[out_5]: 11:10
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_5 (
.re (dio_out_sleep_val_out_5_re),
// qualified with register enable
.we (dio_out_sleep_val_out_5_we & regen_qs),
.wd (dio_out_sleep_val_out_5_wd),
.d (hw2reg.dio_out_sleep_val[5].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[5].qe),
.q (reg2hw.dio_out_sleep_val[5].q ),
.qs (dio_out_sleep_val_out_5_qs)
);
// F[out_6]: 13:12
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_6 (
.re (dio_out_sleep_val_out_6_re),
// qualified with register enable
.we (dio_out_sleep_val_out_6_we & regen_qs),
.wd (dio_out_sleep_val_out_6_wd),
.d (hw2reg.dio_out_sleep_val[6].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[6].qe),
.q (reg2hw.dio_out_sleep_val[6].q ),
.qs (dio_out_sleep_val_out_6_qs)
);
// F[out_7]: 15:14
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_7 (
.re (dio_out_sleep_val_out_7_re),
// qualified with register enable
.we (dio_out_sleep_val_out_7_we & regen_qs),
.wd (dio_out_sleep_val_out_7_wd),
.d (hw2reg.dio_out_sleep_val[7].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[7].qe),
.q (reg2hw.dio_out_sleep_val[7].q ),
.qs (dio_out_sleep_val_out_7_qs)
);
// F[out_8]: 17:16
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_8 (
.re (dio_out_sleep_val_out_8_re),
// qualified with register enable
.we (dio_out_sleep_val_out_8_we & regen_qs),
.wd (dio_out_sleep_val_out_8_wd),
.d (hw2reg.dio_out_sleep_val[8].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[8].qe),
.q (reg2hw.dio_out_sleep_val[8].q ),
.qs (dio_out_sleep_val_out_8_qs)
);
// F[out_9]: 19:18
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_9 (
.re (dio_out_sleep_val_out_9_re),
// qualified with register enable
.we (dio_out_sleep_val_out_9_we & regen_qs),
.wd (dio_out_sleep_val_out_9_wd),
.d (hw2reg.dio_out_sleep_val[9].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[9].qe),
.q (reg2hw.dio_out_sleep_val[9].q ),
.qs (dio_out_sleep_val_out_9_qs)
);
// F[out_10]: 21:20
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_10 (
.re (dio_out_sleep_val_out_10_re),
// qualified with register enable
.we (dio_out_sleep_val_out_10_we & regen_qs),
.wd (dio_out_sleep_val_out_10_wd),
.d (hw2reg.dio_out_sleep_val[10].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[10].qe),
.q (reg2hw.dio_out_sleep_val[10].q ),
.qs (dio_out_sleep_val_out_10_qs)
);
// F[out_11]: 23:22
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_11 (
.re (dio_out_sleep_val_out_11_re),
// qualified with register enable
.we (dio_out_sleep_val_out_11_we & regen_qs),
.wd (dio_out_sleep_val_out_11_wd),
.d (hw2reg.dio_out_sleep_val[11].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[11].qe),
.q (reg2hw.dio_out_sleep_val[11].q ),
.qs (dio_out_sleep_val_out_11_qs)
);
// F[out_12]: 25:24
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_12 (
.re (dio_out_sleep_val_out_12_re),
// qualified with register enable
.we (dio_out_sleep_val_out_12_we & regen_qs),
.wd (dio_out_sleep_val_out_12_wd),
.d (hw2reg.dio_out_sleep_val[12].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[12].qe),
.q (reg2hw.dio_out_sleep_val[12].q ),
.qs (dio_out_sleep_val_out_12_qs)
);
// F[out_13]: 27:26
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_13 (
.re (dio_out_sleep_val_out_13_re),
// qualified with register enable
.we (dio_out_sleep_val_out_13_we & regen_qs),
.wd (dio_out_sleep_val_out_13_wd),
.d (hw2reg.dio_out_sleep_val[13].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[13].qe),
.q (reg2hw.dio_out_sleep_val[13].q ),
.qs (dio_out_sleep_val_out_13_qs)
);
// F[out_14]: 29:28
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_14 (
.re (dio_out_sleep_val_out_14_re),
// qualified with register enable
.we (dio_out_sleep_val_out_14_we & regen_qs),
.wd (dio_out_sleep_val_out_14_wd),
.d (hw2reg.dio_out_sleep_val[14].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[14].qe),
.q (reg2hw.dio_out_sleep_val[14].q ),
.qs (dio_out_sleep_val_out_14_qs)
);
// F[out_15]: 31:30
prim_subreg_ext #(
.DW (2)
) u_dio_out_sleep_val_out_15 (
.re (dio_out_sleep_val_out_15_re),
// qualified with register enable
.we (dio_out_sleep_val_out_15_we & regen_qs),
.wd (dio_out_sleep_val_out_15_wd),
.d (hw2reg.dio_out_sleep_val[15].d),
.qre (),
.qe (reg2hw.dio_out_sleep_val[15].qe),
.q (reg2hw.dio_out_sleep_val[15].q ),
.qs (dio_out_sleep_val_out_15_qs)
);
// Subregister 0 of Multireg wkup_detector_en
// R[wkup_detector_en]: V(False)
// F[en_0]: 0:0
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_en_0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_en_en_0_we & regen_qs),
.wd (wkup_detector_en_en_0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_en[0].q ),
// to register interface (read)
.qs (wkup_detector_en_en_0_qs)
);
// F[en_1]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_en_1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_en_en_1_we & regen_qs),
.wd (wkup_detector_en_en_1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_en[1].q ),
// to register interface (read)
.qs (wkup_detector_en_en_1_qs)
);
// F[en_2]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_en_2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_en_en_2_we & regen_qs),
.wd (wkup_detector_en_en_2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_en[2].q ),
// to register interface (read)
.qs (wkup_detector_en_en_2_qs)
);
// F[en_3]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_en_3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_en_en_3_we & regen_qs),
.wd (wkup_detector_en_en_3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_en[3].q ),
// to register interface (read)
.qs (wkup_detector_en_en_3_qs)
);
// F[en_4]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_en_4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_en_en_4_we & regen_qs),
.wd (wkup_detector_en_en_4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_en[4].q ),
// to register interface (read)
.qs (wkup_detector_en_en_4_qs)
);
// F[en_5]: 5:5
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_en_5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_en_en_5_we & regen_qs),
.wd (wkup_detector_en_en_5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_en[5].q ),
// to register interface (read)
.qs (wkup_detector_en_en_5_qs)
);
// F[en_6]: 6:6
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_en_6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_en_en_6_we & regen_qs),
.wd (wkup_detector_en_en_6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_en[6].q ),
// to register interface (read)
.qs (wkup_detector_en_en_6_qs)
);
// F[en_7]: 7:7
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_en_7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_en_en_7_we & regen_qs),
.wd (wkup_detector_en_en_7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_en[7].q ),
// to register interface (read)
.qs (wkup_detector_en_en_7_qs)
);
// Subregister 0 of Multireg wkup_detector
// R[wkup_detector_0]: V(False)
// F[mode_0]: 2:0
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_0_mode_0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_0_mode_0_we & regen_qs),
.wd (wkup_detector_0_mode_0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[0].mode.q ),
// to register interface (read)
.qs (wkup_detector_0_mode_0_qs)
);
// F[filter_0]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_0_filter_0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_0_filter_0_we & regen_qs),
.wd (wkup_detector_0_filter_0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[0].filter.q ),
// to register interface (read)
.qs (wkup_detector_0_filter_0_qs)
);
// F[miodio_0]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_0_miodio_0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_0_miodio_0_we & regen_qs),
.wd (wkup_detector_0_miodio_0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[0].miodio.q ),
// to register interface (read)
.qs (wkup_detector_0_miodio_0_qs)
);
// Subregister 1 of Multireg wkup_detector
// R[wkup_detector_1]: V(False)
// F[mode_1]: 2:0
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_1_mode_1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_1_mode_1_we & regen_qs),
.wd (wkup_detector_1_mode_1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[1].mode.q ),
// to register interface (read)
.qs (wkup_detector_1_mode_1_qs)
);
// F[filter_1]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_1_filter_1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_1_filter_1_we & regen_qs),
.wd (wkup_detector_1_filter_1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[1].filter.q ),
// to register interface (read)
.qs (wkup_detector_1_filter_1_qs)
);
// F[miodio_1]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_1_miodio_1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_1_miodio_1_we & regen_qs),
.wd (wkup_detector_1_miodio_1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[1].miodio.q ),
// to register interface (read)
.qs (wkup_detector_1_miodio_1_qs)
);
// Subregister 2 of Multireg wkup_detector
// R[wkup_detector_2]: V(False)
// F[mode_2]: 2:0
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_2_mode_2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_2_mode_2_we & regen_qs),
.wd (wkup_detector_2_mode_2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[2].mode.q ),
// to register interface (read)
.qs (wkup_detector_2_mode_2_qs)
);
// F[filter_2]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_2_filter_2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_2_filter_2_we & regen_qs),
.wd (wkup_detector_2_filter_2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[2].filter.q ),
// to register interface (read)
.qs (wkup_detector_2_filter_2_qs)
);
// F[miodio_2]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_2_miodio_2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_2_miodio_2_we & regen_qs),
.wd (wkup_detector_2_miodio_2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[2].miodio.q ),
// to register interface (read)
.qs (wkup_detector_2_miodio_2_qs)
);
// Subregister 3 of Multireg wkup_detector
// R[wkup_detector_3]: V(False)
// F[mode_3]: 2:0
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_3_mode_3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_3_mode_3_we & regen_qs),
.wd (wkup_detector_3_mode_3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[3].mode.q ),
// to register interface (read)
.qs (wkup_detector_3_mode_3_qs)
);
// F[filter_3]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_3_filter_3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_3_filter_3_we & regen_qs),
.wd (wkup_detector_3_filter_3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[3].filter.q ),
// to register interface (read)
.qs (wkup_detector_3_filter_3_qs)
);
// F[miodio_3]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_3_miodio_3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_3_miodio_3_we & regen_qs),
.wd (wkup_detector_3_miodio_3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[3].miodio.q ),
// to register interface (read)
.qs (wkup_detector_3_miodio_3_qs)
);
// Subregister 4 of Multireg wkup_detector
// R[wkup_detector_4]: V(False)
// F[mode_4]: 2:0
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_4_mode_4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_4_mode_4_we & regen_qs),
.wd (wkup_detector_4_mode_4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[4].mode.q ),
// to register interface (read)
.qs (wkup_detector_4_mode_4_qs)
);
// F[filter_4]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_4_filter_4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_4_filter_4_we & regen_qs),
.wd (wkup_detector_4_filter_4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[4].filter.q ),
// to register interface (read)
.qs (wkup_detector_4_filter_4_qs)
);
// F[miodio_4]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_4_miodio_4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_4_miodio_4_we & regen_qs),
.wd (wkup_detector_4_miodio_4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[4].miodio.q ),
// to register interface (read)
.qs (wkup_detector_4_miodio_4_qs)
);
// Subregister 5 of Multireg wkup_detector
// R[wkup_detector_5]: V(False)
// F[mode_5]: 2:0
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_5_mode_5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_5_mode_5_we & regen_qs),
.wd (wkup_detector_5_mode_5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[5].mode.q ),
// to register interface (read)
.qs (wkup_detector_5_mode_5_qs)
);
// F[filter_5]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_5_filter_5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_5_filter_5_we & regen_qs),
.wd (wkup_detector_5_filter_5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[5].filter.q ),
// to register interface (read)
.qs (wkup_detector_5_filter_5_qs)
);
// F[miodio_5]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_5_miodio_5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_5_miodio_5_we & regen_qs),
.wd (wkup_detector_5_miodio_5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[5].miodio.q ),
// to register interface (read)
.qs (wkup_detector_5_miodio_5_qs)
);
// Subregister 6 of Multireg wkup_detector
// R[wkup_detector_6]: V(False)
// F[mode_6]: 2:0
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_6_mode_6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_6_mode_6_we & regen_qs),
.wd (wkup_detector_6_mode_6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[6].mode.q ),
// to register interface (read)
.qs (wkup_detector_6_mode_6_qs)
);
// F[filter_6]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_6_filter_6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_6_filter_6_we & regen_qs),
.wd (wkup_detector_6_filter_6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[6].filter.q ),
// to register interface (read)
.qs (wkup_detector_6_filter_6_qs)
);
// F[miodio_6]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_6_miodio_6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_6_miodio_6_we & regen_qs),
.wd (wkup_detector_6_miodio_6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[6].miodio.q ),
// to register interface (read)
.qs (wkup_detector_6_miodio_6_qs)
);
// Subregister 7 of Multireg wkup_detector
// R[wkup_detector_7]: V(False)
// F[mode_7]: 2:0
prim_subreg #(
.DW (3),
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_7_mode_7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_7_mode_7_we & regen_qs),
.wd (wkup_detector_7_mode_7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[7].mode.q ),
// to register interface (read)
.qs (wkup_detector_7_mode_7_qs)
);
// F[filter_7]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_7_filter_7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_7_filter_7_we & regen_qs),
.wd (wkup_detector_7_filter_7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[7].filter.q ),
// to register interface (read)
.qs (wkup_detector_7_filter_7_qs)
);
// F[miodio_7]: 4:4
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_7_miodio_7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_7_miodio_7_we & regen_qs),
.wd (wkup_detector_7_miodio_7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector[7].miodio.q ),
// to register interface (read)
.qs (wkup_detector_7_miodio_7_qs)
);
// Subregister 0 of Multireg wkup_detector_cnt_th
// R[wkup_detector_cnt_th_0]: V(False)
// F[th_0]: 7:0
prim_subreg #(
.DW (8),
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_0_th_0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_cnt_th_0_th_0_we & regen_qs),
.wd (wkup_detector_cnt_th_0_th_0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_cnt_th[0].q ),
// to register interface (read)
.qs (wkup_detector_cnt_th_0_th_0_qs)
);
// F[th_1]: 15:8
prim_subreg #(
.DW (8),
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_0_th_1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_cnt_th_0_th_1_we & regen_qs),
.wd (wkup_detector_cnt_th_0_th_1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_cnt_th[1].q ),
// to register interface (read)
.qs (wkup_detector_cnt_th_0_th_1_qs)
);
// F[th_2]: 23:16
prim_subreg #(
.DW (8),
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_0_th_2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_cnt_th_0_th_2_we & regen_qs),
.wd (wkup_detector_cnt_th_0_th_2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_cnt_th[2].q ),
// to register interface (read)
.qs (wkup_detector_cnt_th_0_th_2_qs)
);
// F[th_3]: 31:24
prim_subreg #(
.DW (8),
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_0_th_3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_cnt_th_0_th_3_we & regen_qs),
.wd (wkup_detector_cnt_th_0_th_3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_cnt_th[3].q ),
// to register interface (read)
.qs (wkup_detector_cnt_th_0_th_3_qs)
);
// Subregister 4 of Multireg wkup_detector_cnt_th
// R[wkup_detector_cnt_th_1]: V(False)
// F[th_4]: 7:0
prim_subreg #(
.DW (8),
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_1_th_4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_cnt_th_1_th_4_we & regen_qs),
.wd (wkup_detector_cnt_th_1_th_4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_cnt_th[4].q ),
// to register interface (read)
.qs (wkup_detector_cnt_th_1_th_4_qs)
);
// F[th_5]: 15:8
prim_subreg #(
.DW (8),
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_1_th_5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_cnt_th_1_th_5_we & regen_qs),
.wd (wkup_detector_cnt_th_1_th_5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_cnt_th[5].q ),
// to register interface (read)
.qs (wkup_detector_cnt_th_1_th_5_qs)
);
// F[th_6]: 23:16
prim_subreg #(
.DW (8),
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_1_th_6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_cnt_th_1_th_6_we & regen_qs),
.wd (wkup_detector_cnt_th_1_th_6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_cnt_th[6].q ),
// to register interface (read)
.qs (wkup_detector_cnt_th_1_th_6_qs)
);
// F[th_7]: 31:24
prim_subreg #(
.DW (8),
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_1_th_7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_cnt_th_1_th_7_we & regen_qs),
.wd (wkup_detector_cnt_th_1_th_7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_cnt_th[7].q ),
// to register interface (read)
.qs (wkup_detector_cnt_th_1_th_7_qs)
);
// Subregister 0 of Multireg wkup_detector_padsel
// R[wkup_detector_padsel_0]: V(False)
// F[sel_0]: 4:0
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_wkup_detector_padsel_0_sel_0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_padsel_0_sel_0_we & regen_qs),
.wd (wkup_detector_padsel_0_sel_0_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_padsel[0].q ),
// to register interface (read)
.qs (wkup_detector_padsel_0_sel_0_qs)
);
// F[sel_1]: 9:5
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_wkup_detector_padsel_0_sel_1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_padsel_0_sel_1_we & regen_qs),
.wd (wkup_detector_padsel_0_sel_1_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_padsel[1].q ),
// to register interface (read)
.qs (wkup_detector_padsel_0_sel_1_qs)
);
// F[sel_2]: 14:10
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_wkup_detector_padsel_0_sel_2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_padsel_0_sel_2_we & regen_qs),
.wd (wkup_detector_padsel_0_sel_2_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_padsel[2].q ),
// to register interface (read)
.qs (wkup_detector_padsel_0_sel_2_qs)
);
// F[sel_3]: 19:15
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_wkup_detector_padsel_0_sel_3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_padsel_0_sel_3_we & regen_qs),
.wd (wkup_detector_padsel_0_sel_3_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_padsel[3].q ),
// to register interface (read)
.qs (wkup_detector_padsel_0_sel_3_qs)
);
// F[sel_4]: 24:20
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_wkup_detector_padsel_0_sel_4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_padsel_0_sel_4_we & regen_qs),
.wd (wkup_detector_padsel_0_sel_4_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_padsel[4].q ),
// to register interface (read)
.qs (wkup_detector_padsel_0_sel_4_qs)
);
// F[sel_5]: 29:25
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_wkup_detector_padsel_0_sel_5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_padsel_0_sel_5_we & regen_qs),
.wd (wkup_detector_padsel_0_sel_5_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_padsel[5].q ),
// to register interface (read)
.qs (wkup_detector_padsel_0_sel_5_qs)
);
// Subregister 6 of Multireg wkup_detector_padsel
// R[wkup_detector_padsel_1]: V(False)
// F[sel_6]: 4:0
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_wkup_detector_padsel_1_sel_6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_padsel_1_sel_6_we & regen_qs),
.wd (wkup_detector_padsel_1_sel_6_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_padsel[6].q ),
// to register interface (read)
.qs (wkup_detector_padsel_1_sel_6_qs)
);
// F[sel_7]: 9:5
prim_subreg #(
.DW (5),
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_wkup_detector_padsel_1_sel_7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
.we (wkup_detector_padsel_1_sel_7_we & regen_qs),
.wd (wkup_detector_padsel_1_sel_7_wd),
// from internal hardware
.de (1'b0),
.d ('0 ),
// to internal hardware
.qe (),
.q (reg2hw.wkup_detector_padsel[7].q ),
// to register interface (read)
.qs (wkup_detector_padsel_1_sel_7_qs)
);
// Subregister 0 of Multireg wkup_cause
// R[wkup_cause]: V(True)
// F[cause_0]: 0:0
prim_subreg_ext #(
.DW (1)
) u_wkup_cause_cause_0 (
.re (wkup_cause_cause_0_re),
// qualified with register enable
.we (wkup_cause_cause_0_we & regen_qs),
.wd (wkup_cause_cause_0_wd),
.d (hw2reg.wkup_cause[0].d),
.qre (),
.qe (reg2hw.wkup_cause[0].qe),
.q (reg2hw.wkup_cause[0].q ),
.qs (wkup_cause_cause_0_qs)
);
// F[cause_1]: 1:1
prim_subreg_ext #(
.DW (1)
) u_wkup_cause_cause_1 (
.re (wkup_cause_cause_1_re),
// qualified with register enable
.we (wkup_cause_cause_1_we & regen_qs),
.wd (wkup_cause_cause_1_wd),
.d (hw2reg.wkup_cause[1].d),
.qre (),
.qe (reg2hw.wkup_cause[1].qe),
.q (reg2hw.wkup_cause[1].q ),
.qs (wkup_cause_cause_1_qs)
);
// F[cause_2]: 2:2
prim_subreg_ext #(
.DW (1)
) u_wkup_cause_cause_2 (
.re (wkup_cause_cause_2_re),
// qualified with register enable
.we (wkup_cause_cause_2_we & regen_qs),
.wd (wkup_cause_cause_2_wd),
.d (hw2reg.wkup_cause[2].d),
.qre (),
.qe (reg2hw.wkup_cause[2].qe),
.q (reg2hw.wkup_cause[2].q ),
.qs (wkup_cause_cause_2_qs)
);
// F[cause_3]: 3:3
prim_subreg_ext #(
.DW (1)
) u_wkup_cause_cause_3 (
.re (wkup_cause_cause_3_re),
// qualified with register enable
.we (wkup_cause_cause_3_we & regen_qs),
.wd (wkup_cause_cause_3_wd),
.d (hw2reg.wkup_cause[3].d),
.qre (),
.qe (reg2hw.wkup_cause[3].qe),
.q (reg2hw.wkup_cause[3].q ),
.qs (wkup_cause_cause_3_qs)
);
// F[cause_4]: 4:4
prim_subreg_ext #(
.DW (1)
) u_wkup_cause_cause_4 (
.re (wkup_cause_cause_4_re),
// qualified with register enable
.we (wkup_cause_cause_4_we & regen_qs),
.wd (wkup_cause_cause_4_wd),
.d (hw2reg.wkup_cause[4].d),
.qre (),
.qe (reg2hw.wkup_cause[4].qe),
.q (reg2hw.wkup_cause[4].q ),
.qs (wkup_cause_cause_4_qs)
);
// F[cause_5]: 5:5
prim_subreg_ext #(
.DW (1)
) u_wkup_cause_cause_5 (
.re (wkup_cause_cause_5_re),
// qualified with register enable
.we (wkup_cause_cause_5_we & regen_qs),
.wd (wkup_cause_cause_5_wd),
.d (hw2reg.wkup_cause[5].d),
.qre (),
.qe (reg2hw.wkup_cause[5].qe),
.q (reg2hw.wkup_cause[5].q ),
.qs (wkup_cause_cause_5_qs)
);
// F[cause_6]: 6:6
prim_subreg_ext #(
.DW (1)
) u_wkup_cause_cause_6 (
.re (wkup_cause_cause_6_re),
// qualified with register enable
.we (wkup_cause_cause_6_we & regen_qs),
.wd (wkup_cause_cause_6_wd),
.d (hw2reg.wkup_cause[6].d),
.qre (),
.qe (reg2hw.wkup_cause[6].qe),
.q (reg2hw.wkup_cause[6].q ),
.qs (wkup_cause_cause_6_qs)
);
// F[cause_7]: 7:7
prim_subreg_ext #(
.DW (1)
) u_wkup_cause_cause_7 (
.re (wkup_cause_cause_7_re),
// qualified with register enable
.we (wkup_cause_cause_7_we & regen_qs),
.wd (wkup_cause_cause_7_wd),
.d (hw2reg.wkup_cause[7].d),
.qre (),
.qe (reg2hw.wkup_cause[7].qe),
.q (reg2hw.wkup_cause[7].q ),
.qs (wkup_cause_cause_7_qs)
);
logic [31:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == PINMUX_REGEN_OFFSET);
addr_hit[ 1] = (reg_addr == PINMUX_PERIPH_INSEL_0_OFFSET);
addr_hit[ 2] = (reg_addr == PINMUX_PERIPH_INSEL_1_OFFSET);
addr_hit[ 3] = (reg_addr == PINMUX_PERIPH_INSEL_2_OFFSET);
addr_hit[ 4] = (reg_addr == PINMUX_PERIPH_INSEL_3_OFFSET);
addr_hit[ 5] = (reg_addr == PINMUX_PERIPH_INSEL_4_OFFSET);
addr_hit[ 6] = (reg_addr == PINMUX_PERIPH_INSEL_5_OFFSET);
addr_hit[ 7] = (reg_addr == PINMUX_PERIPH_INSEL_6_OFFSET);
addr_hit[ 8] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET);
addr_hit[ 9] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET);
addr_hit[10] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET);
addr_hit[11] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET);
addr_hit[12] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET);
addr_hit[13] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET);
addr_hit[14] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET);
addr_hit[15] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_0_OFFSET);
addr_hit[16] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL_1_OFFSET);
addr_hit[17] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_OFFSET);
addr_hit[18] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_OFFSET);
addr_hit[19] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET);
addr_hit[20] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET);
addr_hit[21] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET);
addr_hit[22] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET);
addr_hit[23] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET);
addr_hit[24] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET);
addr_hit[25] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET);
addr_hit[26] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET);
addr_hit[27] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET);
addr_hit[28] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET);
addr_hit[29] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET);
addr_hit[30] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET);
addr_hit[31] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
// Check sub-word write is permitted
always_comb begin
wr_err = 1'b0;
if (addr_hit[ 0] && reg_we && (PINMUX_PERMIT[ 0] != (PINMUX_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[ 1] && reg_we && (PINMUX_PERMIT[ 1] != (PINMUX_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[ 2] && reg_we && (PINMUX_PERMIT[ 2] != (PINMUX_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[ 3] && reg_we && (PINMUX_PERMIT[ 3] != (PINMUX_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[ 4] && reg_we && (PINMUX_PERMIT[ 4] != (PINMUX_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[ 5] && reg_we && (PINMUX_PERMIT[ 5] != (PINMUX_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[ 6] && reg_we && (PINMUX_PERMIT[ 6] != (PINMUX_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[ 7] && reg_we && (PINMUX_PERMIT[ 7] != (PINMUX_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[ 8] && reg_we && (PINMUX_PERMIT[ 8] != (PINMUX_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[ 9] && reg_we && (PINMUX_PERMIT[ 9] != (PINMUX_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[10] && reg_we && (PINMUX_PERMIT[10] != (PINMUX_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[11] && reg_we && (PINMUX_PERMIT[11] != (PINMUX_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[12] && reg_we && (PINMUX_PERMIT[12] != (PINMUX_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[13] && reg_we && (PINMUX_PERMIT[13] != (PINMUX_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[14] && reg_we && (PINMUX_PERMIT[14] != (PINMUX_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[15] && reg_we && (PINMUX_PERMIT[15] != (PINMUX_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[16] && reg_we && (PINMUX_PERMIT[16] != (PINMUX_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[17] && reg_we && (PINMUX_PERMIT[17] != (PINMUX_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[18] && reg_we && (PINMUX_PERMIT[18] != (PINMUX_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[19] && reg_we && (PINMUX_PERMIT[19] != (PINMUX_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[20] && reg_we && (PINMUX_PERMIT[20] != (PINMUX_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[21] && reg_we && (PINMUX_PERMIT[21] != (PINMUX_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[22] && reg_we && (PINMUX_PERMIT[22] != (PINMUX_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[23] && reg_we && (PINMUX_PERMIT[23] != (PINMUX_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[24] && reg_we && (PINMUX_PERMIT[24] != (PINMUX_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[25] && reg_we && (PINMUX_PERMIT[25] != (PINMUX_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[26] && reg_we && (PINMUX_PERMIT[26] != (PINMUX_PERMIT[26] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[27] && reg_we && (PINMUX_PERMIT[27] != (PINMUX_PERMIT[27] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[28] && reg_we && (PINMUX_PERMIT[28] != (PINMUX_PERMIT[28] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[29] && reg_we && (PINMUX_PERMIT[29] != (PINMUX_PERMIT[29] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[30] && reg_we && (PINMUX_PERMIT[30] != (PINMUX_PERMIT[30] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[31] && reg_we && (PINMUX_PERMIT[31] != (PINMUX_PERMIT[31] & reg_be))) wr_err = 1'b1 ;
end
assign regen_we = addr_hit[0] & reg_we & ~wr_err;
assign regen_wd = reg_wdata[0];
assign periph_insel_0_in_0_we = addr_hit[1] & reg_we & ~wr_err;
assign periph_insel_0_in_0_wd = reg_wdata[5:0];
assign periph_insel_0_in_1_we = addr_hit[1] & reg_we & ~wr_err;
assign periph_insel_0_in_1_wd = reg_wdata[11:6];
assign periph_insel_0_in_2_we = addr_hit[1] & reg_we & ~wr_err;
assign periph_insel_0_in_2_wd = reg_wdata[17:12];
assign periph_insel_0_in_3_we = addr_hit[1] & reg_we & ~wr_err;
assign periph_insel_0_in_3_wd = reg_wdata[23:18];
assign periph_insel_0_in_4_we = addr_hit[1] & reg_we & ~wr_err;
assign periph_insel_0_in_4_wd = reg_wdata[29:24];
assign periph_insel_1_in_5_we = addr_hit[2] & reg_we & ~wr_err;
assign periph_insel_1_in_5_wd = reg_wdata[5:0];
assign periph_insel_1_in_6_we = addr_hit[2] & reg_we & ~wr_err;
assign periph_insel_1_in_6_wd = reg_wdata[11:6];
assign periph_insel_1_in_7_we = addr_hit[2] & reg_we & ~wr_err;
assign periph_insel_1_in_7_wd = reg_wdata[17:12];
assign periph_insel_1_in_8_we = addr_hit[2] & reg_we & ~wr_err;
assign periph_insel_1_in_8_wd = reg_wdata[23:18];
assign periph_insel_1_in_9_we = addr_hit[2] & reg_we & ~wr_err;
assign periph_insel_1_in_9_wd = reg_wdata[29:24];
assign periph_insel_2_in_10_we = addr_hit[3] & reg_we & ~wr_err;
assign periph_insel_2_in_10_wd = reg_wdata[5:0];
assign periph_insel_2_in_11_we = addr_hit[3] & reg_we & ~wr_err;
assign periph_insel_2_in_11_wd = reg_wdata[11:6];
assign periph_insel_2_in_12_we = addr_hit[3] & reg_we & ~wr_err;
assign periph_insel_2_in_12_wd = reg_wdata[17:12];
assign periph_insel_2_in_13_we = addr_hit[3] & reg_we & ~wr_err;
assign periph_insel_2_in_13_wd = reg_wdata[23:18];
assign periph_insel_2_in_14_we = addr_hit[3] & reg_we & ~wr_err;
assign periph_insel_2_in_14_wd = reg_wdata[29:24];
assign periph_insel_3_in_15_we = addr_hit[4] & reg_we & ~wr_err;
assign periph_insel_3_in_15_wd = reg_wdata[5:0];
assign periph_insel_3_in_16_we = addr_hit[4] & reg_we & ~wr_err;
assign periph_insel_3_in_16_wd = reg_wdata[11:6];
assign periph_insel_3_in_17_we = addr_hit[4] & reg_we & ~wr_err;
assign periph_insel_3_in_17_wd = reg_wdata[17:12];
assign periph_insel_3_in_18_we = addr_hit[4] & reg_we & ~wr_err;
assign periph_insel_3_in_18_wd = reg_wdata[23:18];
assign periph_insel_3_in_19_we = addr_hit[4] & reg_we & ~wr_err;
assign periph_insel_3_in_19_wd = reg_wdata[29:24];
assign periph_insel_4_in_20_we = addr_hit[5] & reg_we & ~wr_err;
assign periph_insel_4_in_20_wd = reg_wdata[5:0];
assign periph_insel_4_in_21_we = addr_hit[5] & reg_we & ~wr_err;
assign periph_insel_4_in_21_wd = reg_wdata[11:6];
assign periph_insel_4_in_22_we = addr_hit[5] & reg_we & ~wr_err;
assign periph_insel_4_in_22_wd = reg_wdata[17:12];
assign periph_insel_4_in_23_we = addr_hit[5] & reg_we & ~wr_err;
assign periph_insel_4_in_23_wd = reg_wdata[23:18];
assign periph_insel_4_in_24_we = addr_hit[5] & reg_we & ~wr_err;
assign periph_insel_4_in_24_wd = reg_wdata[29:24];
assign periph_insel_5_in_25_we = addr_hit[6] & reg_we & ~wr_err;
assign periph_insel_5_in_25_wd = reg_wdata[5:0];
assign periph_insel_5_in_26_we = addr_hit[6] & reg_we & ~wr_err;
assign periph_insel_5_in_26_wd = reg_wdata[11:6];
assign periph_insel_5_in_27_we = addr_hit[6] & reg_we & ~wr_err;
assign periph_insel_5_in_27_wd = reg_wdata[17:12];
assign periph_insel_5_in_28_we = addr_hit[6] & reg_we & ~wr_err;
assign periph_insel_5_in_28_wd = reg_wdata[23:18];
assign periph_insel_5_in_29_we = addr_hit[6] & reg_we & ~wr_err;
assign periph_insel_5_in_29_wd = reg_wdata[29:24];
assign periph_insel_6_in_30_we = addr_hit[7] & reg_we & ~wr_err;
assign periph_insel_6_in_30_wd = reg_wdata[5:0];
assign periph_insel_6_in_31_we = addr_hit[7] & reg_we & ~wr_err;
assign periph_insel_6_in_31_wd = reg_wdata[11:6];
assign mio_outsel_0_out_0_we = addr_hit[8] & reg_we & ~wr_err;
assign mio_outsel_0_out_0_wd = reg_wdata[5:0];
assign mio_outsel_0_out_1_we = addr_hit[8] & reg_we & ~wr_err;
assign mio_outsel_0_out_1_wd = reg_wdata[11:6];
assign mio_outsel_0_out_2_we = addr_hit[8] & reg_we & ~wr_err;
assign mio_outsel_0_out_2_wd = reg_wdata[17:12];
assign mio_outsel_0_out_3_we = addr_hit[8] & reg_we & ~wr_err;
assign mio_outsel_0_out_3_wd = reg_wdata[23:18];
assign mio_outsel_0_out_4_we = addr_hit[8] & reg_we & ~wr_err;
assign mio_outsel_0_out_4_wd = reg_wdata[29:24];
assign mio_outsel_1_out_5_we = addr_hit[9] & reg_we & ~wr_err;
assign mio_outsel_1_out_5_wd = reg_wdata[5:0];
assign mio_outsel_1_out_6_we = addr_hit[9] & reg_we & ~wr_err;
assign mio_outsel_1_out_6_wd = reg_wdata[11:6];
assign mio_outsel_1_out_7_we = addr_hit[9] & reg_we & ~wr_err;
assign mio_outsel_1_out_7_wd = reg_wdata[17:12];
assign mio_outsel_1_out_8_we = addr_hit[9] & reg_we & ~wr_err;
assign mio_outsel_1_out_8_wd = reg_wdata[23:18];
assign mio_outsel_1_out_9_we = addr_hit[9] & reg_we & ~wr_err;
assign mio_outsel_1_out_9_wd = reg_wdata[29:24];
assign mio_outsel_2_out_10_we = addr_hit[10] & reg_we & ~wr_err;
assign mio_outsel_2_out_10_wd = reg_wdata[5:0];
assign mio_outsel_2_out_11_we = addr_hit[10] & reg_we & ~wr_err;
assign mio_outsel_2_out_11_wd = reg_wdata[11:6];
assign mio_outsel_2_out_12_we = addr_hit[10] & reg_we & ~wr_err;
assign mio_outsel_2_out_12_wd = reg_wdata[17:12];
assign mio_outsel_2_out_13_we = addr_hit[10] & reg_we & ~wr_err;
assign mio_outsel_2_out_13_wd = reg_wdata[23:18];
assign mio_outsel_2_out_14_we = addr_hit[10] & reg_we & ~wr_err;
assign mio_outsel_2_out_14_wd = reg_wdata[29:24];
assign mio_outsel_3_out_15_we = addr_hit[11] & reg_we & ~wr_err;
assign mio_outsel_3_out_15_wd = reg_wdata[5:0];
assign mio_outsel_3_out_16_we = addr_hit[11] & reg_we & ~wr_err;
assign mio_outsel_3_out_16_wd = reg_wdata[11:6];
assign mio_outsel_3_out_17_we = addr_hit[11] & reg_we & ~wr_err;
assign mio_outsel_3_out_17_wd = reg_wdata[17:12];
assign mio_outsel_3_out_18_we = addr_hit[11] & reg_we & ~wr_err;
assign mio_outsel_3_out_18_wd = reg_wdata[23:18];
assign mio_outsel_3_out_19_we = addr_hit[11] & reg_we & ~wr_err;
assign mio_outsel_3_out_19_wd = reg_wdata[29:24];
assign mio_outsel_4_out_20_we = addr_hit[12] & reg_we & ~wr_err;
assign mio_outsel_4_out_20_wd = reg_wdata[5:0];
assign mio_outsel_4_out_21_we = addr_hit[12] & reg_we & ~wr_err;
assign mio_outsel_4_out_21_wd = reg_wdata[11:6];
assign mio_outsel_4_out_22_we = addr_hit[12] & reg_we & ~wr_err;
assign mio_outsel_4_out_22_wd = reg_wdata[17:12];
assign mio_outsel_4_out_23_we = addr_hit[12] & reg_we & ~wr_err;
assign mio_outsel_4_out_23_wd = reg_wdata[23:18];
assign mio_outsel_4_out_24_we = addr_hit[12] & reg_we & ~wr_err;
assign mio_outsel_4_out_24_wd = reg_wdata[29:24];
assign mio_outsel_5_out_25_we = addr_hit[13] & reg_we & ~wr_err;
assign mio_outsel_5_out_25_wd = reg_wdata[5:0];
assign mio_outsel_5_out_26_we = addr_hit[13] & reg_we & ~wr_err;
assign mio_outsel_5_out_26_wd = reg_wdata[11:6];
assign mio_outsel_5_out_27_we = addr_hit[13] & reg_we & ~wr_err;
assign mio_outsel_5_out_27_wd = reg_wdata[17:12];
assign mio_outsel_5_out_28_we = addr_hit[13] & reg_we & ~wr_err;
assign mio_outsel_5_out_28_wd = reg_wdata[23:18];
assign mio_outsel_5_out_29_we = addr_hit[13] & reg_we & ~wr_err;
assign mio_outsel_5_out_29_wd = reg_wdata[29:24];
assign mio_outsel_6_out_30_we = addr_hit[14] & reg_we & ~wr_err;
assign mio_outsel_6_out_30_wd = reg_wdata[5:0];
assign mio_outsel_6_out_31_we = addr_hit[14] & reg_we & ~wr_err;
assign mio_outsel_6_out_31_wd = reg_wdata[11:6];
assign mio_out_sleep_val_0_out_0_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_0_wd = reg_wdata[1:0];
assign mio_out_sleep_val_0_out_1_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_1_wd = reg_wdata[3:2];
assign mio_out_sleep_val_0_out_2_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_2_wd = reg_wdata[5:4];
assign mio_out_sleep_val_0_out_3_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_3_wd = reg_wdata[7:6];
assign mio_out_sleep_val_0_out_4_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_4_wd = reg_wdata[9:8];
assign mio_out_sleep_val_0_out_5_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_5_wd = reg_wdata[11:10];
assign mio_out_sleep_val_0_out_6_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_6_wd = reg_wdata[13:12];
assign mio_out_sleep_val_0_out_7_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_7_wd = reg_wdata[15:14];
assign mio_out_sleep_val_0_out_8_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_8_wd = reg_wdata[17:16];
assign mio_out_sleep_val_0_out_9_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_9_wd = reg_wdata[19:18];
assign mio_out_sleep_val_0_out_10_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_10_wd = reg_wdata[21:20];
assign mio_out_sleep_val_0_out_11_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_11_wd = reg_wdata[23:22];
assign mio_out_sleep_val_0_out_12_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_12_wd = reg_wdata[25:24];
assign mio_out_sleep_val_0_out_13_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_13_wd = reg_wdata[27:26];
assign mio_out_sleep_val_0_out_14_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_14_wd = reg_wdata[29:28];
assign mio_out_sleep_val_0_out_15_we = addr_hit[15] & reg_we & ~wr_err;
assign mio_out_sleep_val_0_out_15_wd = reg_wdata[31:30];
assign mio_out_sleep_val_1_out_16_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_16_wd = reg_wdata[1:0];
assign mio_out_sleep_val_1_out_17_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_17_wd = reg_wdata[3:2];
assign mio_out_sleep_val_1_out_18_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_18_wd = reg_wdata[5:4];
assign mio_out_sleep_val_1_out_19_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_19_wd = reg_wdata[7:6];
assign mio_out_sleep_val_1_out_20_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_20_wd = reg_wdata[9:8];
assign mio_out_sleep_val_1_out_21_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_21_wd = reg_wdata[11:10];
assign mio_out_sleep_val_1_out_22_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_22_wd = reg_wdata[13:12];
assign mio_out_sleep_val_1_out_23_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_23_wd = reg_wdata[15:14];
assign mio_out_sleep_val_1_out_24_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_24_wd = reg_wdata[17:16];
assign mio_out_sleep_val_1_out_25_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_25_wd = reg_wdata[19:18];
assign mio_out_sleep_val_1_out_26_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_26_wd = reg_wdata[21:20];
assign mio_out_sleep_val_1_out_27_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_27_wd = reg_wdata[23:22];
assign mio_out_sleep_val_1_out_28_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_28_wd = reg_wdata[25:24];
assign mio_out_sleep_val_1_out_29_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_29_wd = reg_wdata[27:26];
assign mio_out_sleep_val_1_out_30_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_30_wd = reg_wdata[29:28];
assign mio_out_sleep_val_1_out_31_we = addr_hit[16] & reg_we & ~wr_err;
assign mio_out_sleep_val_1_out_31_wd = reg_wdata[31:30];
assign dio_out_sleep_val_out_0_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_0_wd = reg_wdata[1:0];
assign dio_out_sleep_val_out_0_re = addr_hit[17] && reg_re;
assign dio_out_sleep_val_out_1_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_1_wd = reg_wdata[3:2];
assign dio_out_sleep_val_out_1_re = addr_hit[17] && reg_re;
assign dio_out_sleep_val_out_2_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_2_wd = reg_wdata[5:4];
assign dio_out_sleep_val_out_2_re = addr_hit[17] && reg_re;
assign dio_out_sleep_val_out_3_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_3_wd = reg_wdata[7:6];
assign dio_out_sleep_val_out_3_re = addr_hit[17] && reg_re;
assign dio_out_sleep_val_out_4_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_4_wd = reg_wdata[9:8];
assign dio_out_sleep_val_out_4_re = addr_hit[17] && reg_re;
assign dio_out_sleep_val_out_5_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_5_wd = reg_wdata[11:10];
assign dio_out_sleep_val_out_5_re = addr_hit[17] && reg_re;
assign dio_out_sleep_val_out_6_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_6_wd = reg_wdata[13:12];
assign dio_out_sleep_val_out_6_re = addr_hit[17] && reg_re;
assign dio_out_sleep_val_out_7_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_7_wd = reg_wdata[15:14];
assign dio_out_sleep_val_out_7_re = addr_hit[17] && reg_re;
assign dio_out_sleep_val_out_8_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_8_wd = reg_wdata[17:16];
assign dio_out_sleep_val_out_8_re = addr_hit[17] && reg_re;
assign dio_out_sleep_val_out_9_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_9_wd = reg_wdata[19:18];
assign dio_out_sleep_val_out_9_re = addr_hit[17] && reg_re;
assign dio_out_sleep_val_out_10_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_10_wd = reg_wdata[21:20];
assign dio_out_sleep_val_out_10_re = addr_hit[17] && reg_re;
assign dio_out_sleep_val_out_11_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_11_wd = reg_wdata[23:22];
assign dio_out_sleep_val_out_11_re = addr_hit[17] && reg_re;
assign dio_out_sleep_val_out_12_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_12_wd = reg_wdata[25:24];
assign dio_out_sleep_val_out_12_re = addr_hit[17] && reg_re;
assign dio_out_sleep_val_out_13_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_13_wd = reg_wdata[27:26];
assign dio_out_sleep_val_out_13_re = addr_hit[17] && reg_re;
assign dio_out_sleep_val_out_14_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_14_wd = reg_wdata[29:28];
assign dio_out_sleep_val_out_14_re = addr_hit[17] && reg_re;
assign dio_out_sleep_val_out_15_we = addr_hit[17] & reg_we & ~wr_err;
assign dio_out_sleep_val_out_15_wd = reg_wdata[31:30];
assign dio_out_sleep_val_out_15_re = addr_hit[17] && reg_re;
assign wkup_detector_en_en_0_we = addr_hit[18] & reg_we & ~wr_err;
assign wkup_detector_en_en_0_wd = reg_wdata[0];
assign wkup_detector_en_en_1_we = addr_hit[18] & reg_we & ~wr_err;
assign wkup_detector_en_en_1_wd = reg_wdata[1];
assign wkup_detector_en_en_2_we = addr_hit[18] & reg_we & ~wr_err;
assign wkup_detector_en_en_2_wd = reg_wdata[2];
assign wkup_detector_en_en_3_we = addr_hit[18] & reg_we & ~wr_err;
assign wkup_detector_en_en_3_wd = reg_wdata[3];
assign wkup_detector_en_en_4_we = addr_hit[18] & reg_we & ~wr_err;
assign wkup_detector_en_en_4_wd = reg_wdata[4];
assign wkup_detector_en_en_5_we = addr_hit[18] & reg_we & ~wr_err;
assign wkup_detector_en_en_5_wd = reg_wdata[5];
assign wkup_detector_en_en_6_we = addr_hit[18] & reg_we & ~wr_err;
assign wkup_detector_en_en_6_wd = reg_wdata[6];
assign wkup_detector_en_en_7_we = addr_hit[18] & reg_we & ~wr_err;
assign wkup_detector_en_en_7_wd = reg_wdata[7];
assign wkup_detector_0_mode_0_we = addr_hit[19] & reg_we & ~wr_err;
assign wkup_detector_0_mode_0_wd = reg_wdata[2:0];
assign wkup_detector_0_filter_0_we = addr_hit[19] & reg_we & ~wr_err;
assign wkup_detector_0_filter_0_wd = reg_wdata[3];
assign wkup_detector_0_miodio_0_we = addr_hit[19] & reg_we & ~wr_err;
assign wkup_detector_0_miodio_0_wd = reg_wdata[4];
assign wkup_detector_1_mode_1_we = addr_hit[20] & reg_we & ~wr_err;
assign wkup_detector_1_mode_1_wd = reg_wdata[2:0];
assign wkup_detector_1_filter_1_we = addr_hit[20] & reg_we & ~wr_err;
assign wkup_detector_1_filter_1_wd = reg_wdata[3];
assign wkup_detector_1_miodio_1_we = addr_hit[20] & reg_we & ~wr_err;
assign wkup_detector_1_miodio_1_wd = reg_wdata[4];
assign wkup_detector_2_mode_2_we = addr_hit[21] & reg_we & ~wr_err;
assign wkup_detector_2_mode_2_wd = reg_wdata[2:0];
assign wkup_detector_2_filter_2_we = addr_hit[21] & reg_we & ~wr_err;
assign wkup_detector_2_filter_2_wd = reg_wdata[3];
assign wkup_detector_2_miodio_2_we = addr_hit[21] & reg_we & ~wr_err;
assign wkup_detector_2_miodio_2_wd = reg_wdata[4];
assign wkup_detector_3_mode_3_we = addr_hit[22] & reg_we & ~wr_err;
assign wkup_detector_3_mode_3_wd = reg_wdata[2:0];
assign wkup_detector_3_filter_3_we = addr_hit[22] & reg_we & ~wr_err;
assign wkup_detector_3_filter_3_wd = reg_wdata[3];
assign wkup_detector_3_miodio_3_we = addr_hit[22] & reg_we & ~wr_err;
assign wkup_detector_3_miodio_3_wd = reg_wdata[4];
assign wkup_detector_4_mode_4_we = addr_hit[23] & reg_we & ~wr_err;
assign wkup_detector_4_mode_4_wd = reg_wdata[2:0];
assign wkup_detector_4_filter_4_we = addr_hit[23] & reg_we & ~wr_err;
assign wkup_detector_4_filter_4_wd = reg_wdata[3];
assign wkup_detector_4_miodio_4_we = addr_hit[23] & reg_we & ~wr_err;
assign wkup_detector_4_miodio_4_wd = reg_wdata[4];
assign wkup_detector_5_mode_5_we = addr_hit[24] & reg_we & ~wr_err;
assign wkup_detector_5_mode_5_wd = reg_wdata[2:0];
assign wkup_detector_5_filter_5_we = addr_hit[24] & reg_we & ~wr_err;
assign wkup_detector_5_filter_5_wd = reg_wdata[3];
assign wkup_detector_5_miodio_5_we = addr_hit[24] & reg_we & ~wr_err;
assign wkup_detector_5_miodio_5_wd = reg_wdata[4];
assign wkup_detector_6_mode_6_we = addr_hit[25] & reg_we & ~wr_err;
assign wkup_detector_6_mode_6_wd = reg_wdata[2:0];
assign wkup_detector_6_filter_6_we = addr_hit[25] & reg_we & ~wr_err;
assign wkup_detector_6_filter_6_wd = reg_wdata[3];
assign wkup_detector_6_miodio_6_we = addr_hit[25] & reg_we & ~wr_err;
assign wkup_detector_6_miodio_6_wd = reg_wdata[4];
assign wkup_detector_7_mode_7_we = addr_hit[26] & reg_we & ~wr_err;
assign wkup_detector_7_mode_7_wd = reg_wdata[2:0];
assign wkup_detector_7_filter_7_we = addr_hit[26] & reg_we & ~wr_err;
assign wkup_detector_7_filter_7_wd = reg_wdata[3];
assign wkup_detector_7_miodio_7_we = addr_hit[26] & reg_we & ~wr_err;
assign wkup_detector_7_miodio_7_wd = reg_wdata[4];
assign wkup_detector_cnt_th_0_th_0_we = addr_hit[27] & reg_we & ~wr_err;
assign wkup_detector_cnt_th_0_th_0_wd = reg_wdata[7:0];
assign wkup_detector_cnt_th_0_th_1_we = addr_hit[27] & reg_we & ~wr_err;
assign wkup_detector_cnt_th_0_th_1_wd = reg_wdata[15:8];
assign wkup_detector_cnt_th_0_th_2_we = addr_hit[27] & reg_we & ~wr_err;
assign wkup_detector_cnt_th_0_th_2_wd = reg_wdata[23:16];
assign wkup_detector_cnt_th_0_th_3_we = addr_hit[27] & reg_we & ~wr_err;
assign wkup_detector_cnt_th_0_th_3_wd = reg_wdata[31:24];
assign wkup_detector_cnt_th_1_th_4_we = addr_hit[28] & reg_we & ~wr_err;
assign wkup_detector_cnt_th_1_th_4_wd = reg_wdata[7:0];
assign wkup_detector_cnt_th_1_th_5_we = addr_hit[28] & reg_we & ~wr_err;
assign wkup_detector_cnt_th_1_th_5_wd = reg_wdata[15:8];
assign wkup_detector_cnt_th_1_th_6_we = addr_hit[28] & reg_we & ~wr_err;
assign wkup_detector_cnt_th_1_th_6_wd = reg_wdata[23:16];
assign wkup_detector_cnt_th_1_th_7_we = addr_hit[28] & reg_we & ~wr_err;
assign wkup_detector_cnt_th_1_th_7_wd = reg_wdata[31:24];
assign wkup_detector_padsel_0_sel_0_we = addr_hit[29] & reg_we & ~wr_err;
assign wkup_detector_padsel_0_sel_0_wd = reg_wdata[4:0];
assign wkup_detector_padsel_0_sel_1_we = addr_hit[29] & reg_we & ~wr_err;
assign wkup_detector_padsel_0_sel_1_wd = reg_wdata[9:5];
assign wkup_detector_padsel_0_sel_2_we = addr_hit[29] & reg_we & ~wr_err;
assign wkup_detector_padsel_0_sel_2_wd = reg_wdata[14:10];
assign wkup_detector_padsel_0_sel_3_we = addr_hit[29] & reg_we & ~wr_err;
assign wkup_detector_padsel_0_sel_3_wd = reg_wdata[19:15];
assign wkup_detector_padsel_0_sel_4_we = addr_hit[29] & reg_we & ~wr_err;
assign wkup_detector_padsel_0_sel_4_wd = reg_wdata[24:20];
assign wkup_detector_padsel_0_sel_5_we = addr_hit[29] & reg_we & ~wr_err;
assign wkup_detector_padsel_0_sel_5_wd = reg_wdata[29:25];
assign wkup_detector_padsel_1_sel_6_we = addr_hit[30] & reg_we & ~wr_err;
assign wkup_detector_padsel_1_sel_6_wd = reg_wdata[4:0];
assign wkup_detector_padsel_1_sel_7_we = addr_hit[30] & reg_we & ~wr_err;
assign wkup_detector_padsel_1_sel_7_wd = reg_wdata[9:5];
assign wkup_cause_cause_0_we = addr_hit[31] & reg_we & ~wr_err;
assign wkup_cause_cause_0_wd = reg_wdata[0];
assign wkup_cause_cause_0_re = addr_hit[31] && reg_re;
assign wkup_cause_cause_1_we = addr_hit[31] & reg_we & ~wr_err;
assign wkup_cause_cause_1_wd = reg_wdata[1];
assign wkup_cause_cause_1_re = addr_hit[31] && reg_re;
assign wkup_cause_cause_2_we = addr_hit[31] & reg_we & ~wr_err;
assign wkup_cause_cause_2_wd = reg_wdata[2];
assign wkup_cause_cause_2_re = addr_hit[31] && reg_re;
assign wkup_cause_cause_3_we = addr_hit[31] & reg_we & ~wr_err;
assign wkup_cause_cause_3_wd = reg_wdata[3];
assign wkup_cause_cause_3_re = addr_hit[31] && reg_re;
assign wkup_cause_cause_4_we = addr_hit[31] & reg_we & ~wr_err;
assign wkup_cause_cause_4_wd = reg_wdata[4];
assign wkup_cause_cause_4_re = addr_hit[31] && reg_re;
assign wkup_cause_cause_5_we = addr_hit[31] & reg_we & ~wr_err;
assign wkup_cause_cause_5_wd = reg_wdata[5];
assign wkup_cause_cause_5_re = addr_hit[31] && reg_re;
assign wkup_cause_cause_6_we = addr_hit[31] & reg_we & ~wr_err;
assign wkup_cause_cause_6_wd = reg_wdata[6];
assign wkup_cause_cause_6_re = addr_hit[31] && reg_re;
assign wkup_cause_cause_7_we = addr_hit[31] & reg_we & ~wr_err;
assign wkup_cause_cause_7_wd = reg_wdata[7];
assign wkup_cause_cause_7_re = addr_hit[31] && reg_re;
// Read data return
always_comb begin
reg_rdata_next = '0;
unique case (1'b1)
addr_hit[0]: begin
reg_rdata_next[0] = regen_qs;
end
addr_hit[1]: begin
reg_rdata_next[5:0] = periph_insel_0_in_0_qs;
reg_rdata_next[11:6] = periph_insel_0_in_1_qs;
reg_rdata_next[17:12] = periph_insel_0_in_2_qs;
reg_rdata_next[23:18] = periph_insel_0_in_3_qs;
reg_rdata_next[29:24] = periph_insel_0_in_4_qs;
end
addr_hit[2]: begin
reg_rdata_next[5:0] = periph_insel_1_in_5_qs;
reg_rdata_next[11:6] = periph_insel_1_in_6_qs;
reg_rdata_next[17:12] = periph_insel_1_in_7_qs;
reg_rdata_next[23:18] = periph_insel_1_in_8_qs;
reg_rdata_next[29:24] = periph_insel_1_in_9_qs;
end
addr_hit[3]: begin
reg_rdata_next[5:0] = periph_insel_2_in_10_qs;
reg_rdata_next[11:6] = periph_insel_2_in_11_qs;
reg_rdata_next[17:12] = periph_insel_2_in_12_qs;
reg_rdata_next[23:18] = periph_insel_2_in_13_qs;
reg_rdata_next[29:24] = periph_insel_2_in_14_qs;
end
addr_hit[4]: begin
reg_rdata_next[5:0] = periph_insel_3_in_15_qs;
reg_rdata_next[11:6] = periph_insel_3_in_16_qs;
reg_rdata_next[17:12] = periph_insel_3_in_17_qs;
reg_rdata_next[23:18] = periph_insel_3_in_18_qs;
reg_rdata_next[29:24] = periph_insel_3_in_19_qs;
end
addr_hit[5]: begin
reg_rdata_next[5:0] = periph_insel_4_in_20_qs;
reg_rdata_next[11:6] = periph_insel_4_in_21_qs;
reg_rdata_next[17:12] = periph_insel_4_in_22_qs;
reg_rdata_next[23:18] = periph_insel_4_in_23_qs;
reg_rdata_next[29:24] = periph_insel_4_in_24_qs;
end
addr_hit[6]: begin
reg_rdata_next[5:0] = periph_insel_5_in_25_qs;
reg_rdata_next[11:6] = periph_insel_5_in_26_qs;
reg_rdata_next[17:12] = periph_insel_5_in_27_qs;
reg_rdata_next[23:18] = periph_insel_5_in_28_qs;
reg_rdata_next[29:24] = periph_insel_5_in_29_qs;
end
addr_hit[7]: begin
reg_rdata_next[5:0] = periph_insel_6_in_30_qs;
reg_rdata_next[11:6] = periph_insel_6_in_31_qs;
end
addr_hit[8]: begin
reg_rdata_next[5:0] = mio_outsel_0_out_0_qs;
reg_rdata_next[11:6] = mio_outsel_0_out_1_qs;
reg_rdata_next[17:12] = mio_outsel_0_out_2_qs;
reg_rdata_next[23:18] = mio_outsel_0_out_3_qs;
reg_rdata_next[29:24] = mio_outsel_0_out_4_qs;
end
addr_hit[9]: begin
reg_rdata_next[5:0] = mio_outsel_1_out_5_qs;
reg_rdata_next[11:6] = mio_outsel_1_out_6_qs;
reg_rdata_next[17:12] = mio_outsel_1_out_7_qs;
reg_rdata_next[23:18] = mio_outsel_1_out_8_qs;
reg_rdata_next[29:24] = mio_outsel_1_out_9_qs;
end
addr_hit[10]: begin
reg_rdata_next[5:0] = mio_outsel_2_out_10_qs;
reg_rdata_next[11:6] = mio_outsel_2_out_11_qs;
reg_rdata_next[17:12] = mio_outsel_2_out_12_qs;
reg_rdata_next[23:18] = mio_outsel_2_out_13_qs;
reg_rdata_next[29:24] = mio_outsel_2_out_14_qs;
end
addr_hit[11]: begin
reg_rdata_next[5:0] = mio_outsel_3_out_15_qs;
reg_rdata_next[11:6] = mio_outsel_3_out_16_qs;
reg_rdata_next[17:12] = mio_outsel_3_out_17_qs;
reg_rdata_next[23:18] = mio_outsel_3_out_18_qs;
reg_rdata_next[29:24] = mio_outsel_3_out_19_qs;
end
addr_hit[12]: begin
reg_rdata_next[5:0] = mio_outsel_4_out_20_qs;
reg_rdata_next[11:6] = mio_outsel_4_out_21_qs;
reg_rdata_next[17:12] = mio_outsel_4_out_22_qs;
reg_rdata_next[23:18] = mio_outsel_4_out_23_qs;
reg_rdata_next[29:24] = mio_outsel_4_out_24_qs;
end
addr_hit[13]: begin
reg_rdata_next[5:0] = mio_outsel_5_out_25_qs;
reg_rdata_next[11:6] = mio_outsel_5_out_26_qs;
reg_rdata_next[17:12] = mio_outsel_5_out_27_qs;
reg_rdata_next[23:18] = mio_outsel_5_out_28_qs;
reg_rdata_next[29:24] = mio_outsel_5_out_29_qs;
end
addr_hit[14]: begin
reg_rdata_next[5:0] = mio_outsel_6_out_30_qs;
reg_rdata_next[11:6] = mio_outsel_6_out_31_qs;
end
addr_hit[15]: begin
reg_rdata_next[1:0] = mio_out_sleep_val_0_out_0_qs;
reg_rdata_next[3:2] = mio_out_sleep_val_0_out_1_qs;
reg_rdata_next[5:4] = mio_out_sleep_val_0_out_2_qs;
reg_rdata_next[7:6] = mio_out_sleep_val_0_out_3_qs;
reg_rdata_next[9:8] = mio_out_sleep_val_0_out_4_qs;
reg_rdata_next[11:10] = mio_out_sleep_val_0_out_5_qs;
reg_rdata_next[13:12] = mio_out_sleep_val_0_out_6_qs;
reg_rdata_next[15:14] = mio_out_sleep_val_0_out_7_qs;
reg_rdata_next[17:16] = mio_out_sleep_val_0_out_8_qs;
reg_rdata_next[19:18] = mio_out_sleep_val_0_out_9_qs;
reg_rdata_next[21:20] = mio_out_sleep_val_0_out_10_qs;
reg_rdata_next[23:22] = mio_out_sleep_val_0_out_11_qs;
reg_rdata_next[25:24] = mio_out_sleep_val_0_out_12_qs;
reg_rdata_next[27:26] = mio_out_sleep_val_0_out_13_qs;
reg_rdata_next[29:28] = mio_out_sleep_val_0_out_14_qs;
reg_rdata_next[31:30] = mio_out_sleep_val_0_out_15_qs;
end
addr_hit[16]: begin
reg_rdata_next[1:0] = mio_out_sleep_val_1_out_16_qs;
reg_rdata_next[3:2] = mio_out_sleep_val_1_out_17_qs;
reg_rdata_next[5:4] = mio_out_sleep_val_1_out_18_qs;
reg_rdata_next[7:6] = mio_out_sleep_val_1_out_19_qs;
reg_rdata_next[9:8] = mio_out_sleep_val_1_out_20_qs;
reg_rdata_next[11:10] = mio_out_sleep_val_1_out_21_qs;
reg_rdata_next[13:12] = mio_out_sleep_val_1_out_22_qs;
reg_rdata_next[15:14] = mio_out_sleep_val_1_out_23_qs;
reg_rdata_next[17:16] = mio_out_sleep_val_1_out_24_qs;
reg_rdata_next[19:18] = mio_out_sleep_val_1_out_25_qs;
reg_rdata_next[21:20] = mio_out_sleep_val_1_out_26_qs;
reg_rdata_next[23:22] = mio_out_sleep_val_1_out_27_qs;
reg_rdata_next[25:24] = mio_out_sleep_val_1_out_28_qs;
reg_rdata_next[27:26] = mio_out_sleep_val_1_out_29_qs;
reg_rdata_next[29:28] = mio_out_sleep_val_1_out_30_qs;
reg_rdata_next[31:30] = mio_out_sleep_val_1_out_31_qs;
end
addr_hit[17]: begin
reg_rdata_next[1:0] = dio_out_sleep_val_out_0_qs;
reg_rdata_next[3:2] = dio_out_sleep_val_out_1_qs;
reg_rdata_next[5:4] = dio_out_sleep_val_out_2_qs;
reg_rdata_next[7:6] = dio_out_sleep_val_out_3_qs;
reg_rdata_next[9:8] = dio_out_sleep_val_out_4_qs;
reg_rdata_next[11:10] = dio_out_sleep_val_out_5_qs;
reg_rdata_next[13:12] = dio_out_sleep_val_out_6_qs;
reg_rdata_next[15:14] = dio_out_sleep_val_out_7_qs;
reg_rdata_next[17:16] = dio_out_sleep_val_out_8_qs;
reg_rdata_next[19:18] = dio_out_sleep_val_out_9_qs;
reg_rdata_next[21:20] = dio_out_sleep_val_out_10_qs;
reg_rdata_next[23:22] = dio_out_sleep_val_out_11_qs;
reg_rdata_next[25:24] = dio_out_sleep_val_out_12_qs;
reg_rdata_next[27:26] = dio_out_sleep_val_out_13_qs;
reg_rdata_next[29:28] = dio_out_sleep_val_out_14_qs;
reg_rdata_next[31:30] = dio_out_sleep_val_out_15_qs;
end
addr_hit[18]: begin
reg_rdata_next[0] = wkup_detector_en_en_0_qs;
reg_rdata_next[1] = wkup_detector_en_en_1_qs;
reg_rdata_next[2] = wkup_detector_en_en_2_qs;
reg_rdata_next[3] = wkup_detector_en_en_3_qs;
reg_rdata_next[4] = wkup_detector_en_en_4_qs;
reg_rdata_next[5] = wkup_detector_en_en_5_qs;
reg_rdata_next[6] = wkup_detector_en_en_6_qs;
reg_rdata_next[7] = wkup_detector_en_en_7_qs;
end
addr_hit[19]: begin
reg_rdata_next[2:0] = wkup_detector_0_mode_0_qs;
reg_rdata_next[3] = wkup_detector_0_filter_0_qs;
reg_rdata_next[4] = wkup_detector_0_miodio_0_qs;
end
addr_hit[20]: begin
reg_rdata_next[2:0] = wkup_detector_1_mode_1_qs;
reg_rdata_next[3] = wkup_detector_1_filter_1_qs;
reg_rdata_next[4] = wkup_detector_1_miodio_1_qs;
end
addr_hit[21]: begin
reg_rdata_next[2:0] = wkup_detector_2_mode_2_qs;
reg_rdata_next[3] = wkup_detector_2_filter_2_qs;
reg_rdata_next[4] = wkup_detector_2_miodio_2_qs;
end
addr_hit[22]: begin
reg_rdata_next[2:0] = wkup_detector_3_mode_3_qs;
reg_rdata_next[3] = wkup_detector_3_filter_3_qs;
reg_rdata_next[4] = wkup_detector_3_miodio_3_qs;
end
addr_hit[23]: begin
reg_rdata_next[2:0] = wkup_detector_4_mode_4_qs;
reg_rdata_next[3] = wkup_detector_4_filter_4_qs;
reg_rdata_next[4] = wkup_detector_4_miodio_4_qs;
end
addr_hit[24]: begin
reg_rdata_next[2:0] = wkup_detector_5_mode_5_qs;
reg_rdata_next[3] = wkup_detector_5_filter_5_qs;
reg_rdata_next[4] = wkup_detector_5_miodio_5_qs;
end
addr_hit[25]: begin
reg_rdata_next[2:0] = wkup_detector_6_mode_6_qs;
reg_rdata_next[3] = wkup_detector_6_filter_6_qs;
reg_rdata_next[4] = wkup_detector_6_miodio_6_qs;
end
addr_hit[26]: begin
reg_rdata_next[2:0] = wkup_detector_7_mode_7_qs;
reg_rdata_next[3] = wkup_detector_7_filter_7_qs;
reg_rdata_next[4] = wkup_detector_7_miodio_7_qs;
end
addr_hit[27]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_0_th_0_qs;
reg_rdata_next[15:8] = wkup_detector_cnt_th_0_th_1_qs;
reg_rdata_next[23:16] = wkup_detector_cnt_th_0_th_2_qs;
reg_rdata_next[31:24] = wkup_detector_cnt_th_0_th_3_qs;
end
addr_hit[28]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_1_th_4_qs;
reg_rdata_next[15:8] = wkup_detector_cnt_th_1_th_5_qs;
reg_rdata_next[23:16] = wkup_detector_cnt_th_1_th_6_qs;
reg_rdata_next[31:24] = wkup_detector_cnt_th_1_th_7_qs;
end
addr_hit[29]: begin
reg_rdata_next[4:0] = wkup_detector_padsel_0_sel_0_qs;
reg_rdata_next[9:5] = wkup_detector_padsel_0_sel_1_qs;
reg_rdata_next[14:10] = wkup_detector_padsel_0_sel_2_qs;
reg_rdata_next[19:15] = wkup_detector_padsel_0_sel_3_qs;
reg_rdata_next[24:20] = wkup_detector_padsel_0_sel_4_qs;
reg_rdata_next[29:25] = wkup_detector_padsel_0_sel_5_qs;
end
addr_hit[30]: begin
reg_rdata_next[4:0] = wkup_detector_padsel_1_sel_6_qs;
reg_rdata_next[9:5] = wkup_detector_padsel_1_sel_7_qs;
end
addr_hit[31]: begin
reg_rdata_next[0] = wkup_cause_cause_0_qs;
reg_rdata_next[1] = wkup_cause_cause_1_qs;
reg_rdata_next[2] = wkup_cause_cause_2_qs;
reg_rdata_next[3] = wkup_cause_cause_3_qs;
reg_rdata_next[4] = wkup_cause_cause_4_qs;
reg_rdata_next[5] = wkup_cause_cause_5_qs;
reg_rdata_next[6] = wkup_cause_cause_6_qs;
reg_rdata_next[7] = wkup_cause_cause_7_qs;
end
default: begin
reg_rdata_next = '1;
end
endcase
end
// Assertions for Register Interface
`ASSERT_PULSE(wePulse, reg_we)
`ASSERT_PULSE(rePulse, reg_re)
`ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
`ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
// this is formulated as an assumption such that the FPV testbenches do disprove this
// property by mistake
`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
endmodule