[clkmgr] updates to support clkmgr idle connections
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/clkmgr/data/clkmgr.hjson.tpl b/hw/ip/clkmgr/data/clkmgr.hjson.tpl
index 5c01a8e..f3715d2 100644
--- a/hw/ip/clkmgr/data/clkmgr.hjson.tpl
+++ b/hw/ip/clkmgr/data/clkmgr.hjson.tpl
@@ -80,11 +80,12 @@
package: "clkmgr_pkg", // This should be moved elsewhere later
},
- { struct: "clk_hint_status",
+ { struct: "logic",
type: "uni",
- name: "status",
+ name: "idle",
act: "rcv",
- package: "clkmgr_pkg",
+ package: "",
+ width: "${len(hint_clks)}"
},
],
@@ -127,7 +128,7 @@
swaccess: "rw",
hwaccess: "hro",
fields: [
-% for clk in hint_clks:
+% for clk in hint_clks.keys():
{
bits: "${loop.index}",
name: "${clk.upper()}_HINT",
@@ -153,7 +154,7 @@
swaccess: "ro",
hwaccess: "hwo",
fields: [
-% for clk in hint_clks:
+% for clk in hint_clks.keys():
{
bits: "${loop.index}",
name: "${clk.upper()}_VAL",
diff --git a/hw/ip/clkmgr/data/clkmgr.sv.tpl b/hw/ip/clkmgr/data/clkmgr.sv.tpl
index 0d2f646..48f0551 100644
--- a/hw/ip/clkmgr/data/clkmgr.sv.tpl
+++ b/hw/ip/clkmgr/data/clkmgr.sv.tpl
@@ -44,7 +44,7 @@
input clk_dft_t dft_i,
// idle hints
- input clk_hint_status_t status_i,
+ input [${len(hint_clks)-1}:0] idle_i,
// clock output interface
% for intf in export_clks:
@@ -234,20 +234,20 @@
% endfor
% for k,v in hint_clks.items():
- assign ${k}_en = ${k}_hint | ~status_i.idle[${loop.index}];
+ assign ${k}_en = ${k}_hint | ~idle_i[${v["name"].capitalize()}];
prim_flop_2sync #(
.Width(1)
) u_${k}_hint_sync (
- .clk_i(clk_${v}_i),
- .rst_ni(rst_${v}_ni),
+ .clk_i(clk_${v["src"]}_i),
+ .rst_ni(rst_${v["src"]}_ni),
.d_i(reg2hw.clk_hints.${k}_hint.q),
.q_o(${k}_hint)
);
prim_clock_gating u_${k}_cg (
- .clk_i(clk_${v}_i),
- .en_i(${k}_en & clk_${v}_en),
+ .clk_i(clk_${v["src"]}_i),
+ .en_i(${k}_en & clk_${v["src"]}_en),
.test_en_i(dft_i.test_en),
.clk_o(clocks_o.${k})
);
diff --git a/hw/ip/clkmgr/data/clkmgr_pkg.sv.tpl b/hw/ip/clkmgr/data/clkmgr_pkg.sv.tpl
index 97b091f..41ae8d0 100644
--- a/hw/ip/clkmgr/data/clkmgr_pkg.sv.tpl
+++ b/hw/ip/clkmgr/data/clkmgr_pkg.sv.tpl
@@ -12,6 +12,12 @@
package clkmgr_pkg;
+ typedef enum int {
+% for hint, v in hint_clks.items():
+ ${v['name'].capitalize()} = ${loop.index}${"," if not loop.last else ""}
+% endfor
+ } hint_names_e;
+
typedef struct packed {
logic test_en;
} clk_dft_t;
diff --git a/hw/ip/hmac/data/hmac.hjson b/hw/ip/hmac/data/hmac.hjson
index 51d54a2..d3cb0b2 100644
--- a/hw/ip/hmac/data/hmac.hjson
+++ b/hw/ip/hmac/data/hmac.hjson
@@ -16,6 +16,15 @@
desc: "HMAC error occurred. ERR_CODE register shows which error occurred"
}
],
+ inter_signal_list: [
+ { name: "idle",
+ type: "uni",
+ act: "req",
+ package: "",
+ struct: "logic",
+ width: "1"
+ }
+ ],
alert_list: [
{ name: "msg_push_sha_disabled",
desc: "Dummy alert which is triggered upon writing a message when SHA is disabled",
diff --git a/hw/ip/hmac/rtl/hmac.sv b/hw/ip/hmac/rtl/hmac.sv
index 32588e5..93faa22 100644
--- a/hw/ip/hmac/rtl/hmac.sv
+++ b/hw/ip/hmac/rtl/hmac.sv
@@ -23,6 +23,8 @@
output logic intr_fifo_empty_o,
output logic intr_hmac_err_o,
+ output logic idle_o,
+
// alerts
input alert_rx_t [NumAlerts-1:0] alert_rx_i,
output alert_tx_t [NumAlerts-1:0] alert_tx_o
@@ -523,6 +525,13 @@
);
end : gen_alert_tx
+
+ /////////////////////
+ // Idle output //
+ /////////////////////
+ // TBD this should be connected later
+ assign idle_o = 1'b1;
+
//////////////////////////////////////////////
// Assertions, Assumptions, and Coverpoints //
//////////////////////////////////////////////
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index cbbcd40..ca27784 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -411,7 +411,8 @@
'pwrmgr.pwr_rst' : ['rstmgr.pwr'],
'pwrmgr.pwr_clk' : ['clkmgr.pwr'],
'flash_ctrl.keymgr': ['keymgr.flash'],
- 'alert_handler.crashdump': ['rstmgr.alert_dump']
+ 'alert_handler.crashdump': ['rstmgr.alert_dump'],
+ 'clkmgr.idle' : [],
}
// top is to connect to top net/struct.
@@ -419,7 +420,6 @@
// use of the signal is up to top template
'top': [
'rstmgr.resets', 'rstmgr.cpu', 'pwrmgr.pwr_cpu', 'clkmgr.clocks',
- 'aes.idle', 'clkmgr.status',
// Xbars
'main.tl_corei', 'main.tl_cored', 'main.tl_dm_sba', 'main.tl_debug_mem'
diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index 4777298..69b8e28 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -181,11 +181,6 @@
% endfor
## Inter-module signal collection
- always_comb begin
- // TODO: So far just aes is connected
- clkmgr_status.idle = clkmgr_pkg::CLK_HINT_STATUS_DEFAULT;
- clkmgr_status.idle[0] = aes_idle;
- end
// Non-debug module reset == reset for everything except for the debug module
logic ndmreset_req;
diff --git a/util/topgen.py b/util/topgen.py
index 52ead8d..7fb01e7 100755
--- a/util/topgen.py
+++ b/util/topgen.py
@@ -489,10 +489,10 @@
# clock classification
grps = top['clocks']['groups']
- src_aon_attr = OrderedDict()
ft_clks = OrderedDict()
rg_clks = OrderedDict()
sw_clks = OrderedDict()
+ src_aon_attr = OrderedDict()
hint_clks = OrderedDict()
# construct a dictionary of the aon attribute for easier lookup
@@ -532,12 +532,20 @@
])
# sw hint clocks
- hint_clks = OrderedDict([
+ hints = OrderedDict([
(clk, src)
for grp in grps for (clk, src) in grp['clocks'].items()
if grp['sw_cg'] == 'hint' and not src_aon_attr[src]
])
+ # hint clocks dict
+ for clk, src in hints.items():
+ # the clock if constructed as clk_{src_name}_{module_name}.
+ # so to get the module name we split from the right and pick the last entry
+ hint_clks[clk] = OrderedDict()
+ hint_clks[clk]['name'] = (clk.rsplit('_', 1)[-1])
+ hint_clks[clk]['src'] = src
+
for idx, tpl in enumerate(tpls):
out = ""
with tpl.open(mode='r', encoding='UTF-8') as fin:
diff --git a/util/topgen/merge.py b/util/topgen/merge.py
index bf2e5f8..10e698b 100644
--- a/util/topgen/merge.py
+++ b/util/topgen/merge.py
@@ -521,6 +521,7 @@
clk_paths = clks_attr['hier_paths']
groups_in_top = [x["name"].lower() for x in clks_attr['groups']]
exported_clks = OrderedDict()
+ trans_eps = []
# Assign default parameters to source clocks
for src in clks_attr['srcs']:
@@ -551,6 +552,10 @@
'clock_group']
ep_grp = ep['clock_group']
+ # if ep is in the transactional group, collect into list below
+ if ep['clock_group'] == 'trans':
+ trans_eps.append(ep['name'])
+
# end point names and clocks
ep_name = ep['name']
ep_clks = []
@@ -618,6 +623,11 @@
for intf in top['exported_clks']:
top['inter_module']['external']['clkmgr.clocks_{}'.format(intf)] = "clks_{}".format(intf)
+ # add to intermodule connections
+ for ep in trans_eps:
+ entry = ep + ".idle"
+ top['inter_module']['connect']['clkmgr.idle'].append(entry)
+
def amend_resets(top):
"""Add a path variable to reset declaration
