[spi_host/doc] updated dv doc, testplan and checklist for V1 Signed-off-by: Rasmus Madsen <rasmus.madsen@wdc.com>
diff --git a/hw/ip/spi_host/data/spi_host_testplan.hjson b/hw/ip/spi_host/data/spi_host_testplan.hjson index 0a3ee75..634b9e9 100644 --- a/hw/ip/spi_host/data/spi_host_testplan.hjson +++ b/hw/ip/spi_host/data/spi_host_testplan.hjson
@@ -325,5 +325,12 @@ Collect coverage that all events was enabled and seen ''' } + { + name: different_ch_settings_cg + desc: ''' + - check that multiple end points was running at different speeds concurrently. + - collect coverage that multiple SPI endpoints was run with different config opts + ''' + } ] }
diff --git a/hw/ip/spi_host/doc/checklist.md b/hw/ip/spi_host/doc/checklist.md index 92f3d11..d736300 100644 --- a/hw/ip/spi_host/doc/checklist.md +++ b/hw/ip/spi_host/doc/checklist.md
@@ -131,24 +131,24 @@ --------------|---------------------------------------|-------------|------------------ Documentation | [DV_DOC_DRAFT_COMPLETED][] | DONE | [SPI_HOST DV document]({{<relref "dv" >}}) Documentation | [TESTPLAN_COMPLETED][] | DONE | [SPI_HOST Testplan]({{<relref "dv/index.md#testplan" >}}) -Testbench | [TB_TOP_CREATED][] | Not Started | -Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started | -Testbench | [SIM_TB_ENV_CREATED][] | Not Started | -Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Not Started | -Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Not Started | -Testbench | [TB_GEN_AUTOMATED][] | Not Started | -Tests | [SIM_SMOKE_TEST_PASSING][] | Not Started | -Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Not Started | +Testbench | [TB_TOP_CREATED][] | DONE | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| DONE | +Testbench | [SIM_TB_ENV_CREATED][] | DONE | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | DONE | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | DONE | +Testbench | [TB_GEN_AUTOMATED][] | DONE | +Tests | [SIM_SMOKE_TEST_PASSING][] | DONE | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | DONE | Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A | -Tool Setup | [SIM_ALT_TOOL_SETUP][] | Not Started | -Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Not Started | -Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started | -Regression | [FPV_REGRESSION_SETUP][] | Not Started | -Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Not Started | -Code Quality | [TB_LINT_SETUP][] | Not Started | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | Xcelium (signoff), VCS (alt) +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | DONE | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started | TBD When 8856 goes in +Regression | [FPV_REGRESSION_SETUP][] | N/A | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | DONE | +Code Quality | [TB_LINT_SETUP][] | DONE | Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | N/A | Review | [DESIGN_SPEC_REVIEWED][] | DONE | -Review | [TESTPLAN_REVIEWED][] | Not Started | +Review | [TESTPLAN_REVIEWED][] | Not Started | TBD in V1 review Review | [STD_TEST_CATEGORIES_PLANNED][] | DONE | Review | [V2_CHECKLIST_SCOPED][] | Not Started |
diff --git a/hw/ip/spi_host/doc/dv/index.md b/hw/ip/spi_host/doc/dv/index.md index ccbf0c3..c6bfc99 100644 --- a/hw/ip/spi_host/doc/dv/index.md +++ b/hw/ip/spi_host/doc/dv/index.md
@@ -60,9 +60,24 @@ Transactions will be sampled by the monitor and passed on to the predictor in the scoreboard. ### SPI Agent -SPI agent is configured to work in target mode. -The agent monitor samples the pins and stores the data in a sequence item that is forwarded to the predictor in the scoreboard. -The sequence item is then compared to a sequence item from the predictor generated on the stimulus from the TL_UL accesses. +SPI agent is configured to work in device mode. +The Agent will decode the SPI transactions send by the DUT and respond with random data to any read command received. +Write data is discarded. +The agent sequence could potentially be upgraded to work as a BFM that could store writes for later read back. +In the current state the agent recognises 6 commands: +* ReadStd: 8'b11001100 +* WriteStd: 8'b11111100 +* ReadDual: 8'b00000011 +* WriteDual: 8'b00001100 +* ReadQuad: 8'b00001111 +* WriteQuad: 8'b11110000 +* CmdOnly: 8'b10000001 + +for V1 only ReadStd, WriteStd and CmdOnly has been implemented. + +The agent monitor will capture both the outgoing host transactions where it creates an item for the device sequence and for the scoreboard to check agains the configuration. +and the incoming device transactions where it will capture the response items and forward them to another tlm_analysis_port in the host scoreboard. + ### UVM RAL Model The SPI_HOST RAL model is created with the [`ralgen`]({{< relref "hw/dv/tools/ralgen/README.md" >}}) FuseSoC generator script automatically when the simulation is at the build stage. @@ -73,20 +88,26 @@ #### Test sequences All test sequences reside in `hw/ip/spi_host/dv/env/seq_lib`. The `spi_host_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. -All test sequences are extended from `spi_host_base_vseq`. +On top of `spi_host_base_vseq` is `spi_host_tx_rx_vseq` which form more complex task from the basic tasks in the base vseq. +All test sequences are extended from `spi_host_tx_rx_vseq`. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. Some of the most commonly used tasks / functions are as follows: -* spi_read(int len, bit [3:0] addr) +* generate_transaction() - read ***len*** bytes from address ***addr*** + Generates a SPI transaction of n segments with command, address, dummy and data segements + +* read_rx_fifo() -* spi_write(int len, bit [3:0] addr) + Read available data in the RX fifo - write ***len*** bytes to address ***addr*** +* send_trans_(spi_transaction_item trans) + + Will handle the sequence of writing potential data to the tx fifo and then configuring the DUT to transmit it + in correct order. #### Functional coverage To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. -the list of functional coverpoints can be found under covergroups in the [testplan](#testplan) +The list of functional coverpoints can be found under covergroups in the [testplan](#testplan) ### Self-checking strategy @@ -101,15 +122,23 @@ **SPI_AGENT** -* spi_channel: TBD - subject to change until env is in place +* host_data_fifo: outgoing SPI item from the DUT captured by the monitor +* device_data_fifo: incoming SPI item for the DUT captured by the monitor -The tl_ul FIFOs provide the transaction items that will be converted to SPI transactions in the DUT. -A predictor in the DUT will collect these transactions and convert them into SPI items with an address and data. +When a host programs the DUT to transmit a SPI message. +The tl-ul agent monitor will capture these in tl items and forward these to the `tl_a_chan_fifo`. +A predictor will use the tl-ul transactions to generate the expected SPI items. +The SPI agent monitor will capture the actual transmitted SPI segments into SPI items and forward them to the `host_data_fifo`. +And the scoreboard will compare the items from the fifo to the expected items created by the predictor to validate the transaction. -On the SPI channel transactions are received in segments. -These segments are re-assembled into full SPI transactions and stored in SPI sequence items. +The SPI device will generate responses to the SPI commands from the DUT. +The SPI agent monitor will capture these into SPI items which are forwarded to the `device_data_fifo` +A predictor will take these and generate the expected tl data response. +The host will then read these from the DUT rx fifo. +The read transaction is captured and forwarded to the `tl_d_chan_fifo` +When the scoreboard receives an item on the `tl_d_chan_fifo` it will match the data to the predicted data to validate the transaction. +This way both outgoing and incoming transactions are validated independently of each other. -The generated item from the predictor and the re-assembled item from the SPI channel is then compared in the scoreboard to validate then transaction. #### Assertions * TLUL assertions: The `tb/spi_host_bind.sv` binds the `tlul_assert` [assertions]({{< relref "hw/ip/tlul/doc/TlulProtocolChecker.md" >}}) to the IP to ensure TileLink interface protocol compliance.
diff --git a/hw/ip/spi_host/dv/cov/spi_host_cov_if.sv b/hw/ip/spi_host/dv/cov/spi_host_cov_if.sv new file mode 100644 index 0000000..878083c --- /dev/null +++ b/hw/ip/spi_host/dv/cov/spi_host_cov_if.sv
@@ -0,0 +1,26 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Implements functional coverage for spi_host + +interface spi_host_cov_if + ( + input logic clk_i + ); + + import uvm_pkg::*; + import spi_host_pkg::*; + import dv_utils_pkg::*; + `include "dv_fcov_macros.svh" + + bit en_full_cov = 1'b1; + bit en_intg_cov = 1'b1; + + /////////////////////////////////// + // Control register cover points // + /////////////////////////////////// + + // TODO add covergroups and coverpoints + +endinterface
diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_tx_rx_vseq.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_tx_rx_vseq.sv index 80727cc..b40c23d 100644 --- a/hw/ip/spi_host/dv/env/seq_lib/spi_host_tx_rx_vseq.sv +++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_tx_rx_vseq.sv
@@ -78,7 +78,6 @@ virtual task generate_transaction(); transaction_init(); `DV_CHECK_RANDOMIZE_FATAL(transaction) - `uvm_info(`gfn, $sformatf("%s",transaction.convert2string()), UVM_LOW); endtask endclass : spi_host_tx_rx_vseq
diff --git a/hw/ip/spi_host/dv/spi_host_sim_cfg.hjson b/hw/ip/spi_host/dv/spi_host_sim_cfg.hjson index 07d54b5..963b2ea 100644 --- a/hw/ip/spi_host/dv/spi_host_sim_cfg.hjson +++ b/hw/ip/spi_host/dv/spi_host_sim_cfg.hjson
@@ -72,13 +72,10 @@ ] // List of regressions. - // TODO: temporaly disable due to WiP V1 - /* regressions: [ { name: smoke tests: ["spi_host_smoke"] } ] - */ }