| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| { |
| // This is a cfg hjson group for DV simulations. It includes ALL individual DV simulation |
| // cfgs of the IPs and the full chip used in top_earlgrey. This enables the common |
| // regression sets to be run in one shot. |
| name: top_earlgrey_batch_sim |
| |
| import_cfgs: [// Project wide common cfg file |
| "{proj_root}/hw/data/common_project_cfg.hjson"] |
| |
| use_cfgs: ["{proj_root}/hw/ip/aes/dv/aes_sim_cfg.hjson", |
| // "{proj_root}/hw/ip/entropy_src/dv/entropy_src_sim_cfg.hjson", |
| "{proj_root}/hw/ip/flash_ctrl/dv/flash_ctrl_sim_cfg.hjson", |
| "{proj_root}/hw/ip/gpio/dv/gpio_sim_cfg.hjson", |
| "{proj_root}/hw/ip/hmac/dv/hmac_sim_cfg.hjson", |
| "{proj_root}/hw/ip/i2c/dv/i2c_sim_cfg.hjson", |
| "{proj_root}/hw/ip/keymgr/dv/keymgr_sim_cfg.hjson", |
| "{proj_root}/hw/ip/rv_timer/dv/rv_timer_sim_cfg.hjson", |
| "{proj_root}/hw/ip/spi_device/dv/spi_device_sim_cfg.hjson", |
| "{proj_root}/hw/ip/uart/dv/uart_sim_cfg.hjson", |
| "{proj_root}/hw/ip/usbdev/dv/usbdev_sim_cfg.hjson", |
| "{proj_root}/hw/ip/prim/dv/prim_present/prim_present_sim_cfg.hjson", |
| "{proj_root}/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson", |
| "{proj_root}/hw/ip/prim/dv/prim_prince/prim_prince_sim_cfg.hjson", |
| "{proj_root}/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_sim_cfg.hjson", |
| "{proj_root}/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson", |
| "{proj_root}/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson", |
| "{proj_root}/hw/top_earlgrey/dv/chip_sim_cfg.hjson"] |
| } |
