| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // Register Top module auto-generated by `reggen` |
| |
| `include "prim_assert.sv" |
| |
| module pwm_reg_top ( |
| input clk_i, |
| input rst_ni, |
| |
| // Below Regster interface can be changed |
| input tlul_pkg::tl_h2d_t tl_i, |
| output tlul_pkg::tl_d2h_t tl_o, |
| // To HW |
| output pwm_reg_pkg::pwm_reg2hw_t reg2hw, // Write |
| |
| // Integrity check errors |
| output logic intg_err_o, |
| |
| // Config |
| input devmode_i // If 1, explicit error return for unmapped register access |
| ); |
| |
| import pwm_reg_pkg::* ; |
| |
| localparam int AW = 7; |
| localparam int DW = 32; |
| localparam int DBW = DW/8; // Byte Width |
| |
| // register signals |
| logic reg_we; |
| logic reg_re; |
| logic [AW-1:0] reg_addr; |
| logic [DW-1:0] reg_wdata; |
| logic [DBW-1:0] reg_be; |
| logic [DW-1:0] reg_rdata; |
| logic reg_error; |
| |
| logic addrmiss, wr_err; |
| |
| logic [DW-1:0] reg_rdata_next; |
| |
| tlul_pkg::tl_h2d_t tl_reg_h2d; |
| tlul_pkg::tl_d2h_t tl_reg_d2h; |
| |
| // incoming payload check |
| logic intg_err; |
| tlul_cmd_intg_chk u_chk ( |
| .tl_i, |
| .err_o(intg_err) |
| ); |
| |
| logic intg_err_q; |
| always_ff @(posedge clk_i or negedge rst_ni) begin |
| if (!rst_ni) begin |
| intg_err_q <= '0; |
| end else if (intg_err) begin |
| intg_err_q <= 1'b1; |
| end |
| end |
| |
| // integrity error output is permanent and should be used for alert generation |
| // register errors are transactional |
| assign intg_err_o = intg_err_q | intg_err; |
| |
| // outgoing integrity generation |
| tlul_pkg::tl_d2h_t tl_o_pre; |
| tlul_rsp_intg_gen u_rsp_intg_gen ( |
| .tl_i(tl_o_pre), |
| .tl_o |
| ); |
| |
| assign tl_reg_h2d = tl_i; |
| assign tl_o_pre = tl_reg_d2h; |
| |
| tlul_adapter_reg #( |
| .RegAw(AW), |
| .RegDw(DW) |
| ) u_reg_if ( |
| .clk_i, |
| .rst_ni, |
| |
| .tl_i (tl_reg_h2d), |
| .tl_o (tl_reg_d2h), |
| |
| .we_o (reg_we), |
| .re_o (reg_re), |
| .addr_o (reg_addr), |
| .wdata_o (reg_wdata), |
| .be_o (reg_be), |
| .rdata_i (reg_rdata), |
| .error_i (reg_error) |
| ); |
| |
| assign reg_rdata = reg_rdata_next ; |
| assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err; |
| |
| // Define SW related signals |
| // Format: <reg>_<field>_{wd|we|qs} |
| // or <reg>_{wd|we|qs} if field == 1 or 0 |
| logic regen_qs; |
| logic regen_wd; |
| logic regen_we; |
| logic [26:0] cfg_clk_div_qs; |
| logic [26:0] cfg_clk_div_wd; |
| logic cfg_clk_div_we; |
| logic [3:0] cfg_dc_resn_qs; |
| logic [3:0] cfg_dc_resn_wd; |
| logic cfg_dc_resn_we; |
| logic cfg_cntr_en_qs; |
| logic cfg_cntr_en_wd; |
| logic cfg_cntr_en_we; |
| logic pwm_en_en_0_qs; |
| logic pwm_en_en_0_wd; |
| logic pwm_en_en_0_we; |
| logic pwm_en_en_1_qs; |
| logic pwm_en_en_1_wd; |
| logic pwm_en_en_1_we; |
| logic pwm_en_en_2_qs; |
| logic pwm_en_en_2_wd; |
| logic pwm_en_en_2_we; |
| logic pwm_en_en_3_qs; |
| logic pwm_en_en_3_wd; |
| logic pwm_en_en_3_we; |
| logic pwm_en_en_4_qs; |
| logic pwm_en_en_4_wd; |
| logic pwm_en_en_4_we; |
| logic pwm_en_en_5_qs; |
| logic pwm_en_en_5_wd; |
| logic pwm_en_en_5_we; |
| logic invert_invert_0_qs; |
| logic invert_invert_0_wd; |
| logic invert_invert_0_we; |
| logic invert_invert_1_qs; |
| logic invert_invert_1_wd; |
| logic invert_invert_1_we; |
| logic invert_invert_2_qs; |
| logic invert_invert_2_wd; |
| logic invert_invert_2_we; |
| logic invert_invert_3_qs; |
| logic invert_invert_3_wd; |
| logic invert_invert_3_we; |
| logic invert_invert_4_qs; |
| logic invert_invert_4_wd; |
| logic invert_invert_4_we; |
| logic invert_invert_5_qs; |
| logic invert_invert_5_wd; |
| logic invert_invert_5_we; |
| logic [15:0] pwm_param_0_phase_delay_0_qs; |
| logic [15:0] pwm_param_0_phase_delay_0_wd; |
| logic pwm_param_0_phase_delay_0_we; |
| logic pwm_param_0_htbt_en_0_qs; |
| logic pwm_param_0_htbt_en_0_wd; |
| logic pwm_param_0_htbt_en_0_we; |
| logic pwm_param_0_blink_en_0_qs; |
| logic pwm_param_0_blink_en_0_wd; |
| logic pwm_param_0_blink_en_0_we; |
| logic [15:0] pwm_param_1_phase_delay_1_qs; |
| logic [15:0] pwm_param_1_phase_delay_1_wd; |
| logic pwm_param_1_phase_delay_1_we; |
| logic pwm_param_1_htbt_en_1_qs; |
| logic pwm_param_1_htbt_en_1_wd; |
| logic pwm_param_1_htbt_en_1_we; |
| logic pwm_param_1_blink_en_1_qs; |
| logic pwm_param_1_blink_en_1_wd; |
| logic pwm_param_1_blink_en_1_we; |
| logic [15:0] pwm_param_2_phase_delay_2_qs; |
| logic [15:0] pwm_param_2_phase_delay_2_wd; |
| logic pwm_param_2_phase_delay_2_we; |
| logic pwm_param_2_htbt_en_2_qs; |
| logic pwm_param_2_htbt_en_2_wd; |
| logic pwm_param_2_htbt_en_2_we; |
| logic pwm_param_2_blink_en_2_qs; |
| logic pwm_param_2_blink_en_2_wd; |
| logic pwm_param_2_blink_en_2_we; |
| logic [15:0] pwm_param_3_phase_delay_3_qs; |
| logic [15:0] pwm_param_3_phase_delay_3_wd; |
| logic pwm_param_3_phase_delay_3_we; |
| logic pwm_param_3_htbt_en_3_qs; |
| logic pwm_param_3_htbt_en_3_wd; |
| logic pwm_param_3_htbt_en_3_we; |
| logic pwm_param_3_blink_en_3_qs; |
| logic pwm_param_3_blink_en_3_wd; |
| logic pwm_param_3_blink_en_3_we; |
| logic [15:0] pwm_param_4_phase_delay_4_qs; |
| logic [15:0] pwm_param_4_phase_delay_4_wd; |
| logic pwm_param_4_phase_delay_4_we; |
| logic pwm_param_4_htbt_en_4_qs; |
| logic pwm_param_4_htbt_en_4_wd; |
| logic pwm_param_4_htbt_en_4_we; |
| logic pwm_param_4_blink_en_4_qs; |
| logic pwm_param_4_blink_en_4_wd; |
| logic pwm_param_4_blink_en_4_we; |
| logic [15:0] pwm_param_5_phase_delay_5_qs; |
| logic [15:0] pwm_param_5_phase_delay_5_wd; |
| logic pwm_param_5_phase_delay_5_we; |
| logic pwm_param_5_htbt_en_5_qs; |
| logic pwm_param_5_htbt_en_5_wd; |
| logic pwm_param_5_htbt_en_5_we; |
| logic pwm_param_5_blink_en_5_qs; |
| logic pwm_param_5_blink_en_5_wd; |
| logic pwm_param_5_blink_en_5_we; |
| logic [15:0] duty_cycle_0_a_0_qs; |
| logic [15:0] duty_cycle_0_a_0_wd; |
| logic duty_cycle_0_a_0_we; |
| logic [15:0] duty_cycle_0_b_0_qs; |
| logic [15:0] duty_cycle_0_b_0_wd; |
| logic duty_cycle_0_b_0_we; |
| logic [15:0] duty_cycle_1_a_1_qs; |
| logic [15:0] duty_cycle_1_a_1_wd; |
| logic duty_cycle_1_a_1_we; |
| logic [15:0] duty_cycle_1_b_1_qs; |
| logic [15:0] duty_cycle_1_b_1_wd; |
| logic duty_cycle_1_b_1_we; |
| logic [15:0] duty_cycle_2_a_2_qs; |
| logic [15:0] duty_cycle_2_a_2_wd; |
| logic duty_cycle_2_a_2_we; |
| logic [15:0] duty_cycle_2_b_2_qs; |
| logic [15:0] duty_cycle_2_b_2_wd; |
| logic duty_cycle_2_b_2_we; |
| logic [15:0] duty_cycle_3_a_3_qs; |
| logic [15:0] duty_cycle_3_a_3_wd; |
| logic duty_cycle_3_a_3_we; |
| logic [15:0] duty_cycle_3_b_3_qs; |
| logic [15:0] duty_cycle_3_b_3_wd; |
| logic duty_cycle_3_b_3_we; |
| logic [15:0] duty_cycle_4_a_4_qs; |
| logic [15:0] duty_cycle_4_a_4_wd; |
| logic duty_cycle_4_a_4_we; |
| logic [15:0] duty_cycle_4_b_4_qs; |
| logic [15:0] duty_cycle_4_b_4_wd; |
| logic duty_cycle_4_b_4_we; |
| logic [15:0] duty_cycle_5_a_5_qs; |
| logic [15:0] duty_cycle_5_a_5_wd; |
| logic duty_cycle_5_a_5_we; |
| logic [15:0] duty_cycle_5_b_5_qs; |
| logic [15:0] duty_cycle_5_b_5_wd; |
| logic duty_cycle_5_b_5_we; |
| logic [15:0] blink_param_0_x_0_qs; |
| logic [15:0] blink_param_0_x_0_wd; |
| logic blink_param_0_x_0_we; |
| logic [15:0] blink_param_0_y_0_qs; |
| logic [15:0] blink_param_0_y_0_wd; |
| logic blink_param_0_y_0_we; |
| logic [15:0] blink_param_1_x_1_qs; |
| logic [15:0] blink_param_1_x_1_wd; |
| logic blink_param_1_x_1_we; |
| logic [15:0] blink_param_1_y_1_qs; |
| logic [15:0] blink_param_1_y_1_wd; |
| logic blink_param_1_y_1_we; |
| logic [15:0] blink_param_2_x_2_qs; |
| logic [15:0] blink_param_2_x_2_wd; |
| logic blink_param_2_x_2_we; |
| logic [15:0] blink_param_2_y_2_qs; |
| logic [15:0] blink_param_2_y_2_wd; |
| logic blink_param_2_y_2_we; |
| logic [15:0] blink_param_3_x_3_qs; |
| logic [15:0] blink_param_3_x_3_wd; |
| logic blink_param_3_x_3_we; |
| logic [15:0] blink_param_3_y_3_qs; |
| logic [15:0] blink_param_3_y_3_wd; |
| logic blink_param_3_y_3_we; |
| logic [15:0] blink_param_4_x_4_qs; |
| logic [15:0] blink_param_4_x_4_wd; |
| logic blink_param_4_x_4_we; |
| logic [15:0] blink_param_4_y_4_qs; |
| logic [15:0] blink_param_4_y_4_wd; |
| logic blink_param_4_y_4_we; |
| logic [15:0] blink_param_5_x_5_qs; |
| logic [15:0] blink_param_5_x_5_wd; |
| logic blink_param_5_x_5_we; |
| logic [15:0] blink_param_5_y_5_qs; |
| logic [15:0] blink_param_5_y_5_wd; |
| logic blink_param_5_y_5_we; |
| |
| // Register instances |
| // R[regen]: V(False) |
| |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("W1C"), |
| .RESVAL (1'h1) |
| ) u_regen ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (regen_we), |
| .wd (regen_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.regen.q ), |
| |
| // to register interface (read) |
| .qs (regen_qs) |
| ); |
| |
| |
| // R[cfg]: V(False) |
| |
| // F[clk_div]: 26:0 |
| prim_subreg #( |
| .DW (27), |
| .SWACCESS("RW"), |
| .RESVAL (27'h8000) |
| ) u_cfg_clk_div ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (cfg_clk_div_we), |
| .wd (cfg_clk_div_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cfg.clk_div.q ), |
| |
| // to register interface (read) |
| .qs (cfg_clk_div_qs) |
| ); |
| |
| |
| // F[dc_resn]: 30:27 |
| prim_subreg #( |
| .DW (4), |
| .SWACCESS("RW"), |
| .RESVAL (4'h7) |
| ) u_cfg_dc_resn ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (cfg_dc_resn_we), |
| .wd (cfg_dc_resn_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cfg.dc_resn.q ), |
| |
| // to register interface (read) |
| .qs (cfg_dc_resn_qs) |
| ); |
| |
| |
| // F[cntr_en]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_cfg_cntr_en ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (cfg_cntr_en_we), |
| .wd (cfg_cntr_en_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.cfg.cntr_en.q ), |
| |
| // to register interface (read) |
| .qs (cfg_cntr_en_qs) |
| ); |
| |
| |
| |
| // Subregister 0 of Multireg pwm_en |
| // R[pwm_en]: V(False) |
| |
| // F[en_0]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_en_en_0 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_en_en_0_we), |
| .wd (pwm_en_en_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_en[0].q ), |
| |
| // to register interface (read) |
| .qs (pwm_en_en_0_qs) |
| ); |
| |
| |
| // F[en_1]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_en_en_1 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_en_en_1_we), |
| .wd (pwm_en_en_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_en[1].q ), |
| |
| // to register interface (read) |
| .qs (pwm_en_en_1_qs) |
| ); |
| |
| |
| // F[en_2]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_en_en_2 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_en_en_2_we), |
| .wd (pwm_en_en_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_en[2].q ), |
| |
| // to register interface (read) |
| .qs (pwm_en_en_2_qs) |
| ); |
| |
| |
| // F[en_3]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_en_en_3 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_en_en_3_we), |
| .wd (pwm_en_en_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_en[3].q ), |
| |
| // to register interface (read) |
| .qs (pwm_en_en_3_qs) |
| ); |
| |
| |
| // F[en_4]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_en_en_4 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_en_en_4_we), |
| .wd (pwm_en_en_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_en[4].q ), |
| |
| // to register interface (read) |
| .qs (pwm_en_en_4_qs) |
| ); |
| |
| |
| // F[en_5]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_en_en_5 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_en_en_5_we), |
| .wd (pwm_en_en_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_en[5].q ), |
| |
| // to register interface (read) |
| .qs (pwm_en_en_5_qs) |
| ); |
| |
| |
| |
| |
| // Subregister 0 of Multireg invert |
| // R[invert]: V(False) |
| |
| // F[invert_0]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_invert_invert_0 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (invert_invert_0_we), |
| .wd (invert_invert_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.invert[0].q ), |
| |
| // to register interface (read) |
| .qs (invert_invert_0_qs) |
| ); |
| |
| |
| // F[invert_1]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_invert_invert_1 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (invert_invert_1_we), |
| .wd (invert_invert_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.invert[1].q ), |
| |
| // to register interface (read) |
| .qs (invert_invert_1_qs) |
| ); |
| |
| |
| // F[invert_2]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_invert_invert_2 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (invert_invert_2_we), |
| .wd (invert_invert_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.invert[2].q ), |
| |
| // to register interface (read) |
| .qs (invert_invert_2_qs) |
| ); |
| |
| |
| // F[invert_3]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_invert_invert_3 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (invert_invert_3_we), |
| .wd (invert_invert_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.invert[3].q ), |
| |
| // to register interface (read) |
| .qs (invert_invert_3_qs) |
| ); |
| |
| |
| // F[invert_4]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_invert_invert_4 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (invert_invert_4_we), |
| .wd (invert_invert_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.invert[4].q ), |
| |
| // to register interface (read) |
| .qs (invert_invert_4_qs) |
| ); |
| |
| |
| // F[invert_5]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_invert_invert_5 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (invert_invert_5_we), |
| .wd (invert_invert_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.invert[5].q ), |
| |
| // to register interface (read) |
| .qs (invert_invert_5_qs) |
| ); |
| |
| |
| |
| |
| // Subregister 0 of Multireg pwm_param |
| // R[pwm_param_0]: V(False) |
| |
| // F[phase_delay_0]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_pwm_param_0_phase_delay_0 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_0_phase_delay_0_we), |
| .wd (pwm_param_0_phase_delay_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[0].phase_delay.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_0_phase_delay_0_qs) |
| ); |
| |
| |
| // F[htbt_en_0]: 30:30 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_param_0_htbt_en_0 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_0_htbt_en_0_we), |
| .wd (pwm_param_0_htbt_en_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[0].htbt_en.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_0_htbt_en_0_qs) |
| ); |
| |
| |
| // F[blink_en_0]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_param_0_blink_en_0 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_0_blink_en_0_we), |
| .wd (pwm_param_0_blink_en_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[0].blink_en.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_0_blink_en_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg pwm_param |
| // R[pwm_param_1]: V(False) |
| |
| // F[phase_delay_1]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_pwm_param_1_phase_delay_1 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_1_phase_delay_1_we), |
| .wd (pwm_param_1_phase_delay_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[1].phase_delay.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_1_phase_delay_1_qs) |
| ); |
| |
| |
| // F[htbt_en_1]: 30:30 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_param_1_htbt_en_1 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_1_htbt_en_1_we), |
| .wd (pwm_param_1_htbt_en_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[1].htbt_en.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_1_htbt_en_1_qs) |
| ); |
| |
| |
| // F[blink_en_1]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_param_1_blink_en_1 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_1_blink_en_1_we), |
| .wd (pwm_param_1_blink_en_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[1].blink_en.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_1_blink_en_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg pwm_param |
| // R[pwm_param_2]: V(False) |
| |
| // F[phase_delay_2]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_pwm_param_2_phase_delay_2 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_2_phase_delay_2_we), |
| .wd (pwm_param_2_phase_delay_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[2].phase_delay.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_2_phase_delay_2_qs) |
| ); |
| |
| |
| // F[htbt_en_2]: 30:30 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_param_2_htbt_en_2 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_2_htbt_en_2_we), |
| .wd (pwm_param_2_htbt_en_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[2].htbt_en.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_2_htbt_en_2_qs) |
| ); |
| |
| |
| // F[blink_en_2]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_param_2_blink_en_2 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_2_blink_en_2_we), |
| .wd (pwm_param_2_blink_en_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[2].blink_en.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_2_blink_en_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg pwm_param |
| // R[pwm_param_3]: V(False) |
| |
| // F[phase_delay_3]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_pwm_param_3_phase_delay_3 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_3_phase_delay_3_we), |
| .wd (pwm_param_3_phase_delay_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[3].phase_delay.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_3_phase_delay_3_qs) |
| ); |
| |
| |
| // F[htbt_en_3]: 30:30 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_param_3_htbt_en_3 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_3_htbt_en_3_we), |
| .wd (pwm_param_3_htbt_en_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[3].htbt_en.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_3_htbt_en_3_qs) |
| ); |
| |
| |
| // F[blink_en_3]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_param_3_blink_en_3 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_3_blink_en_3_we), |
| .wd (pwm_param_3_blink_en_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[3].blink_en.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_3_blink_en_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg pwm_param |
| // R[pwm_param_4]: V(False) |
| |
| // F[phase_delay_4]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_pwm_param_4_phase_delay_4 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_4_phase_delay_4_we), |
| .wd (pwm_param_4_phase_delay_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[4].phase_delay.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_4_phase_delay_4_qs) |
| ); |
| |
| |
| // F[htbt_en_4]: 30:30 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_param_4_htbt_en_4 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_4_htbt_en_4_we), |
| .wd (pwm_param_4_htbt_en_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[4].htbt_en.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_4_htbt_en_4_qs) |
| ); |
| |
| |
| // F[blink_en_4]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_param_4_blink_en_4 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_4_blink_en_4_we), |
| .wd (pwm_param_4_blink_en_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[4].blink_en.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_4_blink_en_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg pwm_param |
| // R[pwm_param_5]: V(False) |
| |
| // F[phase_delay_5]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_pwm_param_5_phase_delay_5 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_5_phase_delay_5_we), |
| .wd (pwm_param_5_phase_delay_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[5].phase_delay.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_5_phase_delay_5_qs) |
| ); |
| |
| |
| // F[htbt_en_5]: 30:30 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_param_5_htbt_en_5 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_5_htbt_en_5_we), |
| .wd (pwm_param_5_htbt_en_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[5].htbt_en.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_5_htbt_en_5_qs) |
| ); |
| |
| |
| // F[blink_en_5]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_pwm_param_5_blink_en_5 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (pwm_param_5_blink_en_5_we), |
| .wd (pwm_param_5_blink_en_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.pwm_param[5].blink_en.q ), |
| |
| // to register interface (read) |
| .qs (pwm_param_5_blink_en_5_qs) |
| ); |
| |
| |
| |
| |
| // Subregister 0 of Multireg duty_cycle |
| // R[duty_cycle_0]: V(False) |
| |
| // F[a_0]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h7fff) |
| ) u_duty_cycle_0_a_0 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (duty_cycle_0_a_0_we), |
| .wd (duty_cycle_0_a_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.duty_cycle[0].a.q ), |
| |
| // to register interface (read) |
| .qs (duty_cycle_0_a_0_qs) |
| ); |
| |
| |
| // F[b_0]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h7fff) |
| ) u_duty_cycle_0_b_0 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (duty_cycle_0_b_0_we), |
| .wd (duty_cycle_0_b_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.duty_cycle[0].b.q ), |
| |
| // to register interface (read) |
| .qs (duty_cycle_0_b_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg duty_cycle |
| // R[duty_cycle_1]: V(False) |
| |
| // F[a_1]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h7fff) |
| ) u_duty_cycle_1_a_1 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (duty_cycle_1_a_1_we), |
| .wd (duty_cycle_1_a_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.duty_cycle[1].a.q ), |
| |
| // to register interface (read) |
| .qs (duty_cycle_1_a_1_qs) |
| ); |
| |
| |
| // F[b_1]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h7fff) |
| ) u_duty_cycle_1_b_1 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (duty_cycle_1_b_1_we), |
| .wd (duty_cycle_1_b_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.duty_cycle[1].b.q ), |
| |
| // to register interface (read) |
| .qs (duty_cycle_1_b_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg duty_cycle |
| // R[duty_cycle_2]: V(False) |
| |
| // F[a_2]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h7fff) |
| ) u_duty_cycle_2_a_2 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (duty_cycle_2_a_2_we), |
| .wd (duty_cycle_2_a_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.duty_cycle[2].a.q ), |
| |
| // to register interface (read) |
| .qs (duty_cycle_2_a_2_qs) |
| ); |
| |
| |
| // F[b_2]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h7fff) |
| ) u_duty_cycle_2_b_2 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (duty_cycle_2_b_2_we), |
| .wd (duty_cycle_2_b_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.duty_cycle[2].b.q ), |
| |
| // to register interface (read) |
| .qs (duty_cycle_2_b_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg duty_cycle |
| // R[duty_cycle_3]: V(False) |
| |
| // F[a_3]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h7fff) |
| ) u_duty_cycle_3_a_3 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (duty_cycle_3_a_3_we), |
| .wd (duty_cycle_3_a_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.duty_cycle[3].a.q ), |
| |
| // to register interface (read) |
| .qs (duty_cycle_3_a_3_qs) |
| ); |
| |
| |
| // F[b_3]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h7fff) |
| ) u_duty_cycle_3_b_3 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (duty_cycle_3_b_3_we), |
| .wd (duty_cycle_3_b_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.duty_cycle[3].b.q ), |
| |
| // to register interface (read) |
| .qs (duty_cycle_3_b_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg duty_cycle |
| // R[duty_cycle_4]: V(False) |
| |
| // F[a_4]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h7fff) |
| ) u_duty_cycle_4_a_4 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (duty_cycle_4_a_4_we), |
| .wd (duty_cycle_4_a_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.duty_cycle[4].a.q ), |
| |
| // to register interface (read) |
| .qs (duty_cycle_4_a_4_qs) |
| ); |
| |
| |
| // F[b_4]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h7fff) |
| ) u_duty_cycle_4_b_4 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (duty_cycle_4_b_4_we), |
| .wd (duty_cycle_4_b_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.duty_cycle[4].b.q ), |
| |
| // to register interface (read) |
| .qs (duty_cycle_4_b_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg duty_cycle |
| // R[duty_cycle_5]: V(False) |
| |
| // F[a_5]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h7fff) |
| ) u_duty_cycle_5_a_5 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (duty_cycle_5_a_5_we), |
| .wd (duty_cycle_5_a_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.duty_cycle[5].a.q ), |
| |
| // to register interface (read) |
| .qs (duty_cycle_5_a_5_qs) |
| ); |
| |
| |
| // F[b_5]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h7fff) |
| ) u_duty_cycle_5_b_5 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (duty_cycle_5_b_5_we), |
| .wd (duty_cycle_5_b_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.duty_cycle[5].b.q ), |
| |
| // to register interface (read) |
| .qs (duty_cycle_5_b_5_qs) |
| ); |
| |
| |
| |
| |
| // Subregister 0 of Multireg blink_param |
| // R[blink_param_0]: V(False) |
| |
| // F[x_0]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_blink_param_0_x_0 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (blink_param_0_x_0_we), |
| .wd (blink_param_0_x_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.blink_param[0].x.q ), |
| |
| // to register interface (read) |
| .qs (blink_param_0_x_0_qs) |
| ); |
| |
| |
| // F[y_0]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_blink_param_0_y_0 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (blink_param_0_y_0_we), |
| .wd (blink_param_0_y_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.blink_param[0].y.q ), |
| |
| // to register interface (read) |
| .qs (blink_param_0_y_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg blink_param |
| // R[blink_param_1]: V(False) |
| |
| // F[x_1]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_blink_param_1_x_1 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (blink_param_1_x_1_we), |
| .wd (blink_param_1_x_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.blink_param[1].x.q ), |
| |
| // to register interface (read) |
| .qs (blink_param_1_x_1_qs) |
| ); |
| |
| |
| // F[y_1]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_blink_param_1_y_1 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (blink_param_1_y_1_we), |
| .wd (blink_param_1_y_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.blink_param[1].y.q ), |
| |
| // to register interface (read) |
| .qs (blink_param_1_y_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg blink_param |
| // R[blink_param_2]: V(False) |
| |
| // F[x_2]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_blink_param_2_x_2 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (blink_param_2_x_2_we), |
| .wd (blink_param_2_x_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.blink_param[2].x.q ), |
| |
| // to register interface (read) |
| .qs (blink_param_2_x_2_qs) |
| ); |
| |
| |
| // F[y_2]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_blink_param_2_y_2 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (blink_param_2_y_2_we), |
| .wd (blink_param_2_y_2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.blink_param[2].y.q ), |
| |
| // to register interface (read) |
| .qs (blink_param_2_y_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg blink_param |
| // R[blink_param_3]: V(False) |
| |
| // F[x_3]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_blink_param_3_x_3 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (blink_param_3_x_3_we), |
| .wd (blink_param_3_x_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.blink_param[3].x.q ), |
| |
| // to register interface (read) |
| .qs (blink_param_3_x_3_qs) |
| ); |
| |
| |
| // F[y_3]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_blink_param_3_y_3 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (blink_param_3_y_3_we), |
| .wd (blink_param_3_y_3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.blink_param[3].y.q ), |
| |
| // to register interface (read) |
| .qs (blink_param_3_y_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg blink_param |
| // R[blink_param_4]: V(False) |
| |
| // F[x_4]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_blink_param_4_x_4 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (blink_param_4_x_4_we), |
| .wd (blink_param_4_x_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.blink_param[4].x.q ), |
| |
| // to register interface (read) |
| .qs (blink_param_4_x_4_qs) |
| ); |
| |
| |
| // F[y_4]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_blink_param_4_y_4 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (blink_param_4_y_4_we), |
| .wd (blink_param_4_y_4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.blink_param[4].y.q ), |
| |
| // to register interface (read) |
| .qs (blink_param_4_y_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg blink_param |
| // R[blink_param_5]: V(False) |
| |
| // F[x_5]: 15:0 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_blink_param_5_x_5 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (blink_param_5_x_5_we), |
| .wd (blink_param_5_x_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.blink_param[5].x.q ), |
| |
| // to register interface (read) |
| .qs (blink_param_5_x_5_qs) |
| ); |
| |
| |
| // F[y_5]: 31:16 |
| prim_subreg #( |
| .DW (16), |
| .SWACCESS("RW"), |
| .RESVAL (16'h0) |
| ) u_blink_param_5_y_5 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (blink_param_5_y_5_we), |
| .wd (blink_param_5_y_5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.blink_param[5].y.q ), |
| |
| // to register interface (read) |
| .qs (blink_param_5_y_5_qs) |
| ); |
| |
| |
| |
| |
| |
| logic [21:0] addr_hit; |
| always_comb begin |
| addr_hit = '0; |
| addr_hit[ 0] = (reg_addr == PWM_REGEN_OFFSET); |
| addr_hit[ 1] = (reg_addr == PWM_CFG_OFFSET); |
| addr_hit[ 2] = (reg_addr == PWM_PWM_EN_OFFSET); |
| addr_hit[ 3] = (reg_addr == PWM_INVERT_OFFSET); |
| addr_hit[ 4] = (reg_addr == PWM_PWM_PARAM_0_OFFSET); |
| addr_hit[ 5] = (reg_addr == PWM_PWM_PARAM_1_OFFSET); |
| addr_hit[ 6] = (reg_addr == PWM_PWM_PARAM_2_OFFSET); |
| addr_hit[ 7] = (reg_addr == PWM_PWM_PARAM_3_OFFSET); |
| addr_hit[ 8] = (reg_addr == PWM_PWM_PARAM_4_OFFSET); |
| addr_hit[ 9] = (reg_addr == PWM_PWM_PARAM_5_OFFSET); |
| addr_hit[10] = (reg_addr == PWM_DUTY_CYCLE_0_OFFSET); |
| addr_hit[11] = (reg_addr == PWM_DUTY_CYCLE_1_OFFSET); |
| addr_hit[12] = (reg_addr == PWM_DUTY_CYCLE_2_OFFSET); |
| addr_hit[13] = (reg_addr == PWM_DUTY_CYCLE_3_OFFSET); |
| addr_hit[14] = (reg_addr == PWM_DUTY_CYCLE_4_OFFSET); |
| addr_hit[15] = (reg_addr == PWM_DUTY_CYCLE_5_OFFSET); |
| addr_hit[16] = (reg_addr == PWM_BLINK_PARAM_0_OFFSET); |
| addr_hit[17] = (reg_addr == PWM_BLINK_PARAM_1_OFFSET); |
| addr_hit[18] = (reg_addr == PWM_BLINK_PARAM_2_OFFSET); |
| addr_hit[19] = (reg_addr == PWM_BLINK_PARAM_3_OFFSET); |
| addr_hit[20] = (reg_addr == PWM_BLINK_PARAM_4_OFFSET); |
| addr_hit[21] = (reg_addr == PWM_BLINK_PARAM_5_OFFSET); |
| end |
| |
| assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; |
| |
| // Check sub-word write is permitted |
| always_comb begin |
| wr_err = 1'b0; |
| if (addr_hit[ 0] && reg_we && (PWM_PERMIT[ 0] != (PWM_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[ 1] && reg_we && (PWM_PERMIT[ 1] != (PWM_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[ 2] && reg_we && (PWM_PERMIT[ 2] != (PWM_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[ 3] && reg_we && (PWM_PERMIT[ 3] != (PWM_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[ 4] && reg_we && (PWM_PERMIT[ 4] != (PWM_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[ 5] && reg_we && (PWM_PERMIT[ 5] != (PWM_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[ 6] && reg_we && (PWM_PERMIT[ 6] != (PWM_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[ 7] && reg_we && (PWM_PERMIT[ 7] != (PWM_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[ 8] && reg_we && (PWM_PERMIT[ 8] != (PWM_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[ 9] && reg_we && (PWM_PERMIT[ 9] != (PWM_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[10] && reg_we && (PWM_PERMIT[10] != (PWM_PERMIT[10] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[11] && reg_we && (PWM_PERMIT[11] != (PWM_PERMIT[11] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[12] && reg_we && (PWM_PERMIT[12] != (PWM_PERMIT[12] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[13] && reg_we && (PWM_PERMIT[13] != (PWM_PERMIT[13] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[14] && reg_we && (PWM_PERMIT[14] != (PWM_PERMIT[14] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[15] && reg_we && (PWM_PERMIT[15] != (PWM_PERMIT[15] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[16] && reg_we && (PWM_PERMIT[16] != (PWM_PERMIT[16] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[17] && reg_we && (PWM_PERMIT[17] != (PWM_PERMIT[17] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[18] && reg_we && (PWM_PERMIT[18] != (PWM_PERMIT[18] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[19] && reg_we && (PWM_PERMIT[19] != (PWM_PERMIT[19] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[20] && reg_we && (PWM_PERMIT[20] != (PWM_PERMIT[20] & reg_be))) wr_err = 1'b1 ; |
| if (addr_hit[21] && reg_we && (PWM_PERMIT[21] != (PWM_PERMIT[21] & reg_be))) wr_err = 1'b1 ; |
| end |
| |
| assign regen_we = addr_hit[0] & reg_we & !reg_error; |
| assign regen_wd = reg_wdata[0]; |
| |
| assign cfg_clk_div_we = addr_hit[1] & reg_we & !reg_error; |
| assign cfg_clk_div_wd = reg_wdata[26:0]; |
| |
| assign cfg_dc_resn_we = addr_hit[1] & reg_we & !reg_error; |
| assign cfg_dc_resn_wd = reg_wdata[30:27]; |
| |
| assign cfg_cntr_en_we = addr_hit[1] & reg_we & !reg_error; |
| assign cfg_cntr_en_wd = reg_wdata[31]; |
| |
| assign pwm_en_en_0_we = addr_hit[2] & reg_we & !reg_error; |
| assign pwm_en_en_0_wd = reg_wdata[0]; |
| |
| assign pwm_en_en_1_we = addr_hit[2] & reg_we & !reg_error; |
| assign pwm_en_en_1_wd = reg_wdata[1]; |
| |
| assign pwm_en_en_2_we = addr_hit[2] & reg_we & !reg_error; |
| assign pwm_en_en_2_wd = reg_wdata[2]; |
| |
| assign pwm_en_en_3_we = addr_hit[2] & reg_we & !reg_error; |
| assign pwm_en_en_3_wd = reg_wdata[3]; |
| |
| assign pwm_en_en_4_we = addr_hit[2] & reg_we & !reg_error; |
| assign pwm_en_en_4_wd = reg_wdata[4]; |
| |
| assign pwm_en_en_5_we = addr_hit[2] & reg_we & !reg_error; |
| assign pwm_en_en_5_wd = reg_wdata[5]; |
| |
| assign invert_invert_0_we = addr_hit[3] & reg_we & !reg_error; |
| assign invert_invert_0_wd = reg_wdata[0]; |
| |
| assign invert_invert_1_we = addr_hit[3] & reg_we & !reg_error; |
| assign invert_invert_1_wd = reg_wdata[1]; |
| |
| assign invert_invert_2_we = addr_hit[3] & reg_we & !reg_error; |
| assign invert_invert_2_wd = reg_wdata[2]; |
| |
| assign invert_invert_3_we = addr_hit[3] & reg_we & !reg_error; |
| assign invert_invert_3_wd = reg_wdata[3]; |
| |
| assign invert_invert_4_we = addr_hit[3] & reg_we & !reg_error; |
| assign invert_invert_4_wd = reg_wdata[4]; |
| |
| assign invert_invert_5_we = addr_hit[3] & reg_we & !reg_error; |
| assign invert_invert_5_wd = reg_wdata[5]; |
| |
| assign pwm_param_0_phase_delay_0_we = addr_hit[4] & reg_we & !reg_error; |
| assign pwm_param_0_phase_delay_0_wd = reg_wdata[15:0]; |
| |
| assign pwm_param_0_htbt_en_0_we = addr_hit[4] & reg_we & !reg_error; |
| assign pwm_param_0_htbt_en_0_wd = reg_wdata[30]; |
| |
| assign pwm_param_0_blink_en_0_we = addr_hit[4] & reg_we & !reg_error; |
| assign pwm_param_0_blink_en_0_wd = reg_wdata[31]; |
| |
| assign pwm_param_1_phase_delay_1_we = addr_hit[5] & reg_we & !reg_error; |
| assign pwm_param_1_phase_delay_1_wd = reg_wdata[15:0]; |
| |
| assign pwm_param_1_htbt_en_1_we = addr_hit[5] & reg_we & !reg_error; |
| assign pwm_param_1_htbt_en_1_wd = reg_wdata[30]; |
| |
| assign pwm_param_1_blink_en_1_we = addr_hit[5] & reg_we & !reg_error; |
| assign pwm_param_1_blink_en_1_wd = reg_wdata[31]; |
| |
| assign pwm_param_2_phase_delay_2_we = addr_hit[6] & reg_we & !reg_error; |
| assign pwm_param_2_phase_delay_2_wd = reg_wdata[15:0]; |
| |
| assign pwm_param_2_htbt_en_2_we = addr_hit[6] & reg_we & !reg_error; |
| assign pwm_param_2_htbt_en_2_wd = reg_wdata[30]; |
| |
| assign pwm_param_2_blink_en_2_we = addr_hit[6] & reg_we & !reg_error; |
| assign pwm_param_2_blink_en_2_wd = reg_wdata[31]; |
| |
| assign pwm_param_3_phase_delay_3_we = addr_hit[7] & reg_we & !reg_error; |
| assign pwm_param_3_phase_delay_3_wd = reg_wdata[15:0]; |
| |
| assign pwm_param_3_htbt_en_3_we = addr_hit[7] & reg_we & !reg_error; |
| assign pwm_param_3_htbt_en_3_wd = reg_wdata[30]; |
| |
| assign pwm_param_3_blink_en_3_we = addr_hit[7] & reg_we & !reg_error; |
| assign pwm_param_3_blink_en_3_wd = reg_wdata[31]; |
| |
| assign pwm_param_4_phase_delay_4_we = addr_hit[8] & reg_we & !reg_error; |
| assign pwm_param_4_phase_delay_4_wd = reg_wdata[15:0]; |
| |
| assign pwm_param_4_htbt_en_4_we = addr_hit[8] & reg_we & !reg_error; |
| assign pwm_param_4_htbt_en_4_wd = reg_wdata[30]; |
| |
| assign pwm_param_4_blink_en_4_we = addr_hit[8] & reg_we & !reg_error; |
| assign pwm_param_4_blink_en_4_wd = reg_wdata[31]; |
| |
| assign pwm_param_5_phase_delay_5_we = addr_hit[9] & reg_we & !reg_error; |
| assign pwm_param_5_phase_delay_5_wd = reg_wdata[15:0]; |
| |
| assign pwm_param_5_htbt_en_5_we = addr_hit[9] & reg_we & !reg_error; |
| assign pwm_param_5_htbt_en_5_wd = reg_wdata[30]; |
| |
| assign pwm_param_5_blink_en_5_we = addr_hit[9] & reg_we & !reg_error; |
| assign pwm_param_5_blink_en_5_wd = reg_wdata[31]; |
| |
| assign duty_cycle_0_a_0_we = addr_hit[10] & reg_we & !reg_error; |
| assign duty_cycle_0_a_0_wd = reg_wdata[15:0]; |
| |
| assign duty_cycle_0_b_0_we = addr_hit[10] & reg_we & !reg_error; |
| assign duty_cycle_0_b_0_wd = reg_wdata[31:16]; |
| |
| assign duty_cycle_1_a_1_we = addr_hit[11] & reg_we & !reg_error; |
| assign duty_cycle_1_a_1_wd = reg_wdata[15:0]; |
| |
| assign duty_cycle_1_b_1_we = addr_hit[11] & reg_we & !reg_error; |
| assign duty_cycle_1_b_1_wd = reg_wdata[31:16]; |
| |
| assign duty_cycle_2_a_2_we = addr_hit[12] & reg_we & !reg_error; |
| assign duty_cycle_2_a_2_wd = reg_wdata[15:0]; |
| |
| assign duty_cycle_2_b_2_we = addr_hit[12] & reg_we & !reg_error; |
| assign duty_cycle_2_b_2_wd = reg_wdata[31:16]; |
| |
| assign duty_cycle_3_a_3_we = addr_hit[13] & reg_we & !reg_error; |
| assign duty_cycle_3_a_3_wd = reg_wdata[15:0]; |
| |
| assign duty_cycle_3_b_3_we = addr_hit[13] & reg_we & !reg_error; |
| assign duty_cycle_3_b_3_wd = reg_wdata[31:16]; |
| |
| assign duty_cycle_4_a_4_we = addr_hit[14] & reg_we & !reg_error; |
| assign duty_cycle_4_a_4_wd = reg_wdata[15:0]; |
| |
| assign duty_cycle_4_b_4_we = addr_hit[14] & reg_we & !reg_error; |
| assign duty_cycle_4_b_4_wd = reg_wdata[31:16]; |
| |
| assign duty_cycle_5_a_5_we = addr_hit[15] & reg_we & !reg_error; |
| assign duty_cycle_5_a_5_wd = reg_wdata[15:0]; |
| |
| assign duty_cycle_5_b_5_we = addr_hit[15] & reg_we & !reg_error; |
| assign duty_cycle_5_b_5_wd = reg_wdata[31:16]; |
| |
| assign blink_param_0_x_0_we = addr_hit[16] & reg_we & !reg_error; |
| assign blink_param_0_x_0_wd = reg_wdata[15:0]; |
| |
| assign blink_param_0_y_0_we = addr_hit[16] & reg_we & !reg_error; |
| assign blink_param_0_y_0_wd = reg_wdata[31:16]; |
| |
| assign blink_param_1_x_1_we = addr_hit[17] & reg_we & !reg_error; |
| assign blink_param_1_x_1_wd = reg_wdata[15:0]; |
| |
| assign blink_param_1_y_1_we = addr_hit[17] & reg_we & !reg_error; |
| assign blink_param_1_y_1_wd = reg_wdata[31:16]; |
| |
| assign blink_param_2_x_2_we = addr_hit[18] & reg_we & !reg_error; |
| assign blink_param_2_x_2_wd = reg_wdata[15:0]; |
| |
| assign blink_param_2_y_2_we = addr_hit[18] & reg_we & !reg_error; |
| assign blink_param_2_y_2_wd = reg_wdata[31:16]; |
| |
| assign blink_param_3_x_3_we = addr_hit[19] & reg_we & !reg_error; |
| assign blink_param_3_x_3_wd = reg_wdata[15:0]; |
| |
| assign blink_param_3_y_3_we = addr_hit[19] & reg_we & !reg_error; |
| assign blink_param_3_y_3_wd = reg_wdata[31:16]; |
| |
| assign blink_param_4_x_4_we = addr_hit[20] & reg_we & !reg_error; |
| assign blink_param_4_x_4_wd = reg_wdata[15:0]; |
| |
| assign blink_param_4_y_4_we = addr_hit[20] & reg_we & !reg_error; |
| assign blink_param_4_y_4_wd = reg_wdata[31:16]; |
| |
| assign blink_param_5_x_5_we = addr_hit[21] & reg_we & !reg_error; |
| assign blink_param_5_x_5_wd = reg_wdata[15:0]; |
| |
| assign blink_param_5_y_5_we = addr_hit[21] & reg_we & !reg_error; |
| assign blink_param_5_y_5_wd = reg_wdata[31:16]; |
| |
| // Read data return |
| always_comb begin |
| reg_rdata_next = '0; |
| unique case (1'b1) |
| addr_hit[0]: begin |
| reg_rdata_next[0] = regen_qs; |
| end |
| |
| addr_hit[1]: begin |
| reg_rdata_next[26:0] = cfg_clk_div_qs; |
| reg_rdata_next[30:27] = cfg_dc_resn_qs; |
| reg_rdata_next[31] = cfg_cntr_en_qs; |
| end |
| |
| addr_hit[2]: begin |
| reg_rdata_next[0] = pwm_en_en_0_qs; |
| reg_rdata_next[1] = pwm_en_en_1_qs; |
| reg_rdata_next[2] = pwm_en_en_2_qs; |
| reg_rdata_next[3] = pwm_en_en_3_qs; |
| reg_rdata_next[4] = pwm_en_en_4_qs; |
| reg_rdata_next[5] = pwm_en_en_5_qs; |
| end |
| |
| addr_hit[3]: begin |
| reg_rdata_next[0] = invert_invert_0_qs; |
| reg_rdata_next[1] = invert_invert_1_qs; |
| reg_rdata_next[2] = invert_invert_2_qs; |
| reg_rdata_next[3] = invert_invert_3_qs; |
| reg_rdata_next[4] = invert_invert_4_qs; |
| reg_rdata_next[5] = invert_invert_5_qs; |
| end |
| |
| addr_hit[4]: begin |
| reg_rdata_next[15:0] = pwm_param_0_phase_delay_0_qs; |
| reg_rdata_next[30] = pwm_param_0_htbt_en_0_qs; |
| reg_rdata_next[31] = pwm_param_0_blink_en_0_qs; |
| end |
| |
| addr_hit[5]: begin |
| reg_rdata_next[15:0] = pwm_param_1_phase_delay_1_qs; |
| reg_rdata_next[30] = pwm_param_1_htbt_en_1_qs; |
| reg_rdata_next[31] = pwm_param_1_blink_en_1_qs; |
| end |
| |
| addr_hit[6]: begin |
| reg_rdata_next[15:0] = pwm_param_2_phase_delay_2_qs; |
| reg_rdata_next[30] = pwm_param_2_htbt_en_2_qs; |
| reg_rdata_next[31] = pwm_param_2_blink_en_2_qs; |
| end |
| |
| addr_hit[7]: begin |
| reg_rdata_next[15:0] = pwm_param_3_phase_delay_3_qs; |
| reg_rdata_next[30] = pwm_param_3_htbt_en_3_qs; |
| reg_rdata_next[31] = pwm_param_3_blink_en_3_qs; |
| end |
| |
| addr_hit[8]: begin |
| reg_rdata_next[15:0] = pwm_param_4_phase_delay_4_qs; |
| reg_rdata_next[30] = pwm_param_4_htbt_en_4_qs; |
| reg_rdata_next[31] = pwm_param_4_blink_en_4_qs; |
| end |
| |
| addr_hit[9]: begin |
| reg_rdata_next[15:0] = pwm_param_5_phase_delay_5_qs; |
| reg_rdata_next[30] = pwm_param_5_htbt_en_5_qs; |
| reg_rdata_next[31] = pwm_param_5_blink_en_5_qs; |
| end |
| |
| addr_hit[10]: begin |
| reg_rdata_next[15:0] = duty_cycle_0_a_0_qs; |
| reg_rdata_next[31:16] = duty_cycle_0_b_0_qs; |
| end |
| |
| addr_hit[11]: begin |
| reg_rdata_next[15:0] = duty_cycle_1_a_1_qs; |
| reg_rdata_next[31:16] = duty_cycle_1_b_1_qs; |
| end |
| |
| addr_hit[12]: begin |
| reg_rdata_next[15:0] = duty_cycle_2_a_2_qs; |
| reg_rdata_next[31:16] = duty_cycle_2_b_2_qs; |
| end |
| |
| addr_hit[13]: begin |
| reg_rdata_next[15:0] = duty_cycle_3_a_3_qs; |
| reg_rdata_next[31:16] = duty_cycle_3_b_3_qs; |
| end |
| |
| addr_hit[14]: begin |
| reg_rdata_next[15:0] = duty_cycle_4_a_4_qs; |
| reg_rdata_next[31:16] = duty_cycle_4_b_4_qs; |
| end |
| |
| addr_hit[15]: begin |
| reg_rdata_next[15:0] = duty_cycle_5_a_5_qs; |
| reg_rdata_next[31:16] = duty_cycle_5_b_5_qs; |
| end |
| |
| addr_hit[16]: begin |
| reg_rdata_next[15:0] = blink_param_0_x_0_qs; |
| reg_rdata_next[31:16] = blink_param_0_y_0_qs; |
| end |
| |
| addr_hit[17]: begin |
| reg_rdata_next[15:0] = blink_param_1_x_1_qs; |
| reg_rdata_next[31:16] = blink_param_1_y_1_qs; |
| end |
| |
| addr_hit[18]: begin |
| reg_rdata_next[15:0] = blink_param_2_x_2_qs; |
| reg_rdata_next[31:16] = blink_param_2_y_2_qs; |
| end |
| |
| addr_hit[19]: begin |
| reg_rdata_next[15:0] = blink_param_3_x_3_qs; |
| reg_rdata_next[31:16] = blink_param_3_y_3_qs; |
| end |
| |
| addr_hit[20]: begin |
| reg_rdata_next[15:0] = blink_param_4_x_4_qs; |
| reg_rdata_next[31:16] = blink_param_4_y_4_qs; |
| end |
| |
| addr_hit[21]: begin |
| reg_rdata_next[15:0] = blink_param_5_x_5_qs; |
| reg_rdata_next[31:16] = blink_param_5_y_5_qs; |
| end |
| |
| default: begin |
| reg_rdata_next = '1; |
| end |
| endcase |
| end |
| |
| // Unused signal tieoff |
| |
| // wdata / byte enable are not always fully used |
| // add a blanket unused statement to handle lint waivers |
| logic unused_wdata; |
| logic unused_be; |
| assign unused_wdata = ^reg_wdata; |
| assign unused_be = ^reg_be; |
| |
| // Assertions for Register Interface |
| `ASSERT_PULSE(wePulse, reg_we) |
| `ASSERT_PULSE(rePulse, reg_re) |
| |
| `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid) |
| |
| `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) |
| |
| // this is formulated as an assumption such that the FPV testbenches do disprove this |
| // property by mistake |
| //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) |
| |
| endmodule |
