[edn/dv] V0->V1

Signed-off-by: Steve Nelson <steve.nelson@wdc.com>

hw/ip/edn/data/edn.prj.hjson

diff --git a/hw/ip/edn/data/edn.prj.hjson b/hw/ip/edn/data/edn.prj.hjson
index 33509bf..b6c7096 100644
--- a/hw/ip/edn/data/edn.prj.hjson
+++ b/hw/ip/edn/data/edn.prj.hjson
@@ -10,5 +10,5 @@
     version:            "0.5",
     life_stage:         "L1",
     design_stage:       "D1",
-    verification_stage: "V0",
+    verification_stage: "V1",
 }

hw/ip/edn/data/edn_testplan.hjson

diff --git a/hw/ip/edn/data/edn_testplan.hjson b/hw/ip/edn/data/edn_testplan.hjson
index 81823f0..878a28e 100644
--- a/hw/ip/edn/data/edn_testplan.hjson
+++ b/hw/ip/edn/data/edn_testplan.hjson
@@ -21,9 +21,8 @@
     {
       name: firmware
       desc: '''
-            Verify regwen bit enables/disables write access to control registers.
             Verify SW_CMD_REQ/SW_CMD_STS registers/bits behave as predicted.
-            Verify RESEED/GENERATE software cmds work with/without additional data.
+            Verify RESEED/GENERATE software cmds work with 0 and 12 32-bit words of additional data.
             Verify cmd_fifo_reset bit causes fifos to reset.
             Verify boot_req_dis bit disables boot_req mode.
             Verify registers at End-Of-Test.
@@ -34,7 +33,8 @@
     {
       name: csrng_cmd
       desc: '''
-            Verify endpoint agent reqs generate csrng commands as predicted.
+            Verify endpoint agent reqs generate csrng commands for both fifo full/empty conditions.
+            Verify when no/some/all endpoints requesting (test arbiter).
             Verify auto-request mode (RESEED_CMD/GENERATE_CMD registers) behaves as predicted.
             Verify max_num_reqs_between_reseeds in auto-generate mode.
             Verify boot-time request mode behaves as predicted.

hw/ip/edn/doc/checklist.md

diff --git a/hw/ip/edn/doc/checklist.md b/hw/ip/edn/doc/checklist.md
index c72deee..ea486ef 100755
--- a/hw/ip/edn/doc/checklist.md
+++ b/hw/ip/edn/doc/checklist.md
@@ -130,10 +130,10 @@
 Regression    | [FPV_REGRESSION_SETUP][]              | N/A         |
 Coverage      | [SIM_COVERAGE_MODEL_ADDED][]          | Done        |
 Integration   | [PRE_VERIFIED_SUB_MODULES_V1][]       | N/A         |
-Review        | [DESIGN_SPEC_REVIEWED][]              | Not Started |
-Review        | [DV_PLAN_REVIEWED][]                  | Not Started |
-Review        | [STD_TEST_CATEGORIES_PLANNED][]       | Not Started | Exception (?)
-Review        | [V2_CHECKLIST_SCOPED][]               | Not Started |
+Review        | [DESIGN_SPEC_REVIEWED][]              | Done        |
+Review        | [DV_PLAN_REVIEWED][]                  | Done        |
+Review        | [STD_TEST_CATEGORIES_PLANNED][]       | Done        | Exception (Security, Power, Debug)
+Review        | [V2_CHECKLIST_SCOPED][]               | Done        |
 
 [DV_DOC_DRAFT_COMPLETED]:             {{<relref "/doc/project/checklist.md#dv_doc_draft_completed" >}}
 [DV_PLAN_COMPLETED]:                  {{<relref "/doc/project/checklist.md#dv_plan_completed" >}}