[hmac] Remove Invalid Assertion
As `prim_packer` is updated, one of the assertion inside sha2_pad is no
longer valid assumption.
packer now sends out the data first when `flush_i` request is received.
Then it asserts the `flush_done_o` one cycle later. That signal is used
has `hash_process` in the SHA engine. So that the `hash_process_flag`
can be delayed 2 cycles.
Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
diff --git a/hw/ip/hmac/rtl/hmac.sv b/hw/ip/hmac/rtl/hmac.sv
index 043829d..a0b73ab 100644
--- a/hw/ip/hmac/rtl/hmac.sv
+++ b/hw/ip/hmac/rtl/hmac.sv
@@ -259,7 +259,7 @@
prim_fifo_sync #(
.Width ($bits(sha_fifo_t)),
- .Pass (1'b0),
+ .Pass (1'b1),
.Depth (MsgFifoDepth)
) u_msg_fifo (
.clk_i,
diff --git a/hw/ip/hmac/rtl/sha2_pad.sv b/hw/ip/hmac/rtl/sha2_pad.sv
index 5ee9088..cc56535 100644
--- a/hw/ip/hmac/rtl/sha2_pad.sv
+++ b/hw/ip/hmac/rtl/sha2_pad.sv
@@ -309,8 +309,4 @@
// State machine is in Idle only when it meets tx_count == message length
assign msg_feed_complete = hash_process_flag && (st_q == StIdle);
- // When fifo_partial, fifo shouldn't be empty and hash_process was set
- `ASSERT(ValidPartialConditionAssert,
- fifo_partial && fifo_rvalid |-> hash_process_flag)
-
endmodule
