commit bc7f6d6cde2259f2741e40112f2ff4c6871d0d75
author Tom Roberts <tomroberts@lowrisc.org> Thu Mar 04 12:33:23 2021 +0000
committer Tom Roberts <53745528+tomroberts-lowrisc@users.noreply.github.com> Fri Mar 05 17:50:30 2021 +0000
tree 74ae1e77fc3e53cc61ce51db85980b178659bd3c
parent dadebce3951540a3624ce936d79f06b46691e68d

Update lowrisc_ibex to lowRISC/ibex@6d9e1ac

Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
6d9e1aca8ad7cf09d4effcde97e471d6c213ead1

* [rtl] Minor lint fix in ibex_core.sv (Tom Roberts)
* [rtl] Add MCOUNTEREN CSR (Vladimir Rozic)
* Update lowrisc_ip to lowRISC/opentitan@6cc5c164b (Tom Roberts)
* [vendor] Remove fcov patch from dv_utils (Tom Roberts)
* [dv/ibex] update how coverage is merged (Udi Jonnalagadda)
* Don't automatically generate disassembly in the example Makefile
  (Rupert Swarbrick)
* [dv] Fix bug in sim.py and type in testlist (Greg Chadwick)
* [rtl] Add crash dump outputs (Tom Roberts)
* [rtl] Lint fixes for Ascent lint issues (Greg Chadwick)
* [rtl] Remove paths between dmem and imem signals (Greg Chadwick)
* [simple_system] Fix type for mhpmcounter_get (Rupert Swarbrick)
* [rtl] Debug mode controller changes (Greg Chadwick)
* Fix deprecated sphinx html_context usage in conf.py (Philipp Wagner)
* [dv] Reorder checks in sim.py (Greg Chadwick)
* Update google_riscv-dv to google/riscv-dv@0b62525 (Greg Chadwick)
* [dv] Add RISCV-DV patch to fix csr_test (Greg Chadwick)
* [dv] Fix MISA CSR reset value (Greg Chadwick)
* [dv] Fix issues with timeout on WFI (Greg Chadwick)
* [dv] Add ePMP support to cs_registers testbench (Greg Chadwick)
* [dv] Fix race condition in cs_registers testbench (Greg Chadwick)
* [doc] Add ePMP information (Greg Chadwick)
* [rtl] Add ePMP support to Ibex (Greg Chadwick)
* [dv] Improve sim.py error reporting (Greg Chadwick)
* [dv] Rename stored copy of run phase (Rupert Swarbrick)
* [dv] Be explicit about the target priv_mode in wait_ret test (Rupert
  Swarbrick)
* [dv] Wire up alerts to dut probe interface (Rupert Swarbrick)
* Specify boot address in hex to avoid 32-bit signed overflow (Rupert
  Swarbrick)
* [syn] Fail a bit more gracefully if something goes wrong (Rupert
  Swarbrick)
* [doc] Update dependency descriptions for Spike/OVPsim (Rupert
  Swarbrick)
* [syn] Add missing include path (Greg Chadwick)
* [verilator] Remove clock gating waiver and add extra warning (Rupert
  Swarbrick)
* [rtl] Fix lint "fix" with DbgTriggerEn (Rupert Swarbrick)
* [rtl] Fix lint warning when DbgTriggerEn parameter is set (Rupert
  Swarbrick)
* [dv] Ibex uarch functional coverage (Greg Chadwick)
* Update lowrisc_ip to lowRISC/opentitan@7aa5c2b89 (Greg Chadwick)
* [dv] Patch for fcov macros in dv_utils (Greg Chadwick)
* [rtl] Fix overlapping encodings of immediate instructions in tracer
  package (Pirmin Vogel)
* [rtl] Fix encoding of ZIP/UNZIP pseudo-instrcutions in tracer
  package (Pirmin Vogel)
* [rtl] Fix encoding for ORC16/REV16 instructions in tracer package
  (Pirmin Vogel)
* [syn] Fix timing reports in synthesis flow (Greg Chadwick)
* [rtl] Fix PMP NAPOT matching for 0 PMPGranularity (Greg Chadwick)
* [dv] Verilator unused parameter handling (Tobias Wölfel)
* [rtl] Add B extension to misa (Tobias Wölfel)
* [rtl] Avoid latch creation (Tobias Wölfel)
* [rtl] Use tracer parameters for decoding (Tobias Wölfel)
* [rtl] Disable definition of unused instructions (Tobias Wölfel)
* [rtl] Remove unused tracer branch instruction (Tobias Wölfel)
* [doc/um] Updated the python requirements run command for sw simple
  system (Rahul Raveendran)
* CI: The distro-provided pyyaml package is enough (Philipp Wagner)
* Revert "Clear MAKEFLAGS when running dvsim.py" (Rupert Swarbrick)
* Update lowrisc_ip to lowRISC/opentitan@c277e3a8 (Philipp Wagner)
* Use overlapping implications for Xcelium 19.03 (Fresher14)
* Use more descriptive issue template names (Philipp Wagner)
* Add issue templates to GitHub project (Philipp Wagner)
* [rtl] Add branch prediction signals to icache (Tom Roberts)
* [rtl] icache performance updates (Tom Roberts)
* [fpv] Assume icache req_i input is low when in reset (Rupert
  Swarbrick)
* [dv] Make sure the req_i interface is never asserted in reset
  (Rupert Swarbrick)
* [syn] Fix path in synthesis script (Tom Roberts)
* CI: Remove outdated workarounds for Ubuntu 16.04 (Philipp Wagner)
* CI: Update to Ubuntu 18.04 (Philipp Wagner)
* Avoid use of the term "sanity test" in icache UVM testbench (Rupert
  Swarbrick)
* Update lowrisc_ip to lowRISC/opentitan@e619fc60 (Rupert Swarbrick)
* Clear MAKEFLAGS when running dvsim.py (Rupert Swarbrick)
* Delete dv/uvm/data and point DV code at the vendored version (Rupert
  Swarbrick)
* Vendor in hw/dv/{data,tools} from OpenTitan (Rupert Swarbrick)
* Update paths for vendored DV code (Rupert Swarbrick)
* Improve ibex_config command line handling with missing output_fn
  (Rupert Swarbrick)
* Fix Xcelium warnings (Philipp Wagner)
* [dv/ibex] add support for DSim (Udi Jonnalagadda)
* [doc] Add bitmanip note to README (Greg Chadwick)
* [doc] Update info on simulators for verification (Greg Chadwick)
* Update google_riscv-dv to google/riscv-dv@3da32bb (Udi Jonnalagadda)
* [rtl] Fix performance counter bug (Tom Roberts)
* [dv] Fixes for disabling forks, for Cadence Xcelium This makes
  changes to support Cadence Xcelium 20.09.001. (CathalMCrevinn)
* [ibex/dv] Modify EOT ecall check (Udi Jonnalagadda)
* [rtl] Reduce size of PMP addr CSRs to minimum (Michael Platzer)
* [rtl] Fix NAPOT address matching (Michael Platzer)
* [dv] Fix riscv_debug_single_step_test (Greg Chadwick)

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>