)]}' { "commit": "bc7f6d6cde2259f2741e40112f2ff4c6871d0d75", "tree": "74ae1e77fc3e53cc61ce51db85980b178659bd3c", "parents": [ "dadebce3951540a3624ce936d79f06b46691e68d" ], "author": { "name": "Tom Roberts", "email": "tomroberts@lowrisc.org", "time": "Thu Mar 04 12:33:23 2021 +0000" }, "committer": { "name": "Tom Roberts", "email": "53745528+tomroberts-lowrisc@users.noreply.github.com", "time": "Fri Mar 05 17:50:30 2021 +0000" }, "message": "Update lowrisc_ibex to lowRISC/ibex@6d9e1ac\n\nUpdate code from upstream repository\nhttps://github.com/lowRISC/ibex.git to revision\n6d9e1aca8ad7cf09d4effcde97e471d6c213ead1\n\n* [rtl] Minor lint fix in ibex_core.sv (Tom Roberts)\n* [rtl] Add MCOUNTEREN CSR (Vladimir Rozic)\n* Update lowrisc_ip to lowRISC/opentitan@6cc5c164b (Tom Roberts)\n* [vendor] Remove fcov patch from dv_utils (Tom Roberts)\n* [dv/ibex] update how coverage is merged (Udi Jonnalagadda)\n* Don\u0027t automatically generate disassembly in the example Makefile\n (Rupert Swarbrick)\n* [dv] Fix bug in sim.py and type in testlist (Greg Chadwick)\n* [rtl] Add crash dump outputs (Tom Roberts)\n* [rtl] Lint fixes for Ascent lint issues (Greg Chadwick)\n* [rtl] Remove paths between dmem and imem signals (Greg Chadwick)\n* [simple_system] Fix type for mhpmcounter_get (Rupert Swarbrick)\n* [rtl] Debug mode controller changes (Greg Chadwick)\n* Fix deprecated sphinx html_context usage in conf.py (Philipp Wagner)\n* [dv] Reorder checks in sim.py (Greg Chadwick)\n* Update google_riscv-dv to google/riscv-dv@0b62525 (Greg Chadwick)\n* [dv] Add RISCV-DV patch to fix csr_test (Greg Chadwick)\n* [dv] Fix MISA CSR reset value (Greg Chadwick)\n* [dv] Fix issues with timeout on WFI (Greg Chadwick)\n* [dv] Add ePMP support to cs_registers testbench (Greg Chadwick)\n* [dv] Fix race condition in cs_registers testbench (Greg Chadwick)\n* [doc] Add ePMP information (Greg Chadwick)\n* [rtl] Add ePMP support to Ibex (Greg Chadwick)\n* [dv] Improve sim.py error reporting (Greg Chadwick)\n* [dv] Rename stored copy of run phase (Rupert Swarbrick)\n* [dv] Be explicit about the target priv_mode in wait_ret test (Rupert\n Swarbrick)\n* [dv] Wire up alerts to dut probe interface (Rupert Swarbrick)\n* Specify boot address in hex to avoid 32-bit signed overflow (Rupert\n Swarbrick)\n* [syn] Fail a bit more gracefully if something goes wrong (Rupert\n Swarbrick)\n* [doc] Update dependency descriptions for Spike/OVPsim (Rupert\n Swarbrick)\n* [syn] Add missing include path (Greg Chadwick)\n* [verilator] Remove clock gating waiver and add extra warning (Rupert\n Swarbrick)\n* [rtl] Fix lint \"fix\" with DbgTriggerEn (Rupert Swarbrick)\n* [rtl] Fix lint warning when DbgTriggerEn parameter is set (Rupert\n Swarbrick)\n* [dv] Ibex uarch functional coverage (Greg Chadwick)\n* Update lowrisc_ip to lowRISC/opentitan@7aa5c2b89 (Greg Chadwick)\n* [dv] Patch for fcov macros in dv_utils (Greg Chadwick)\n* [rtl] Fix overlapping encodings of immediate instructions in tracer\n package (Pirmin Vogel)\n* [rtl] Fix encoding of ZIP/UNZIP pseudo-instrcutions in tracer\n package (Pirmin Vogel)\n* [rtl] Fix encoding for ORC16/REV16 instructions in tracer package\n (Pirmin Vogel)\n* [syn] Fix timing reports in synthesis flow (Greg Chadwick)\n* [rtl] Fix PMP NAPOT matching for 0 PMPGranularity (Greg Chadwick)\n* [dv] Verilator unused parameter handling (Tobias Wölfel)\n* [rtl] Add B extension to misa (Tobias Wölfel)\n* [rtl] Avoid latch creation (Tobias Wölfel)\n* [rtl] Use tracer parameters for decoding (Tobias Wölfel)\n* [rtl] Disable definition of unused instructions (Tobias Wölfel)\n* [rtl] Remove unused tracer branch instruction (Tobias Wölfel)\n* [doc/um] Updated the python requirements run command for sw simple\n system (Rahul Raveendran)\n* CI: The distro-provided pyyaml package is enough (Philipp Wagner)\n* Revert \"Clear MAKEFLAGS when running dvsim.py\" (Rupert Swarbrick)\n* Update lowrisc_ip to lowRISC/opentitan@c277e3a8 (Philipp Wagner)\n* Use overlapping implications for Xcelium 19.03 (Fresher14)\n* Use more descriptive issue template names (Philipp Wagner)\n* Add issue templates to GitHub project (Philipp Wagner)\n* [rtl] Add branch prediction signals to icache (Tom Roberts)\n* [rtl] icache performance updates (Tom Roberts)\n* [fpv] Assume icache req_i input is low when in reset (Rupert\n Swarbrick)\n* [dv] Make sure the req_i interface is never asserted in reset\n (Rupert Swarbrick)\n* [syn] Fix path in synthesis script (Tom Roberts)\n* CI: Remove outdated workarounds for Ubuntu 16.04 (Philipp Wagner)\n* CI: Update to Ubuntu 18.04 (Philipp Wagner)\n* Avoid use of the term \"sanity test\" in icache UVM testbench (Rupert\n Swarbrick)\n* Update lowrisc_ip to lowRISC/opentitan@e619fc60 (Rupert Swarbrick)\n* Clear MAKEFLAGS when running dvsim.py (Rupert Swarbrick)\n* Delete dv/uvm/data and point DV code at the vendored version (Rupert\n Swarbrick)\n* Vendor in hw/dv/{data,tools} from OpenTitan (Rupert Swarbrick)\n* Update paths for vendored DV code (Rupert Swarbrick)\n* Improve ibex_config command line handling with missing output_fn\n (Rupert Swarbrick)\n* Fix Xcelium warnings (Philipp Wagner)\n* [dv/ibex] add support for DSim (Udi Jonnalagadda)\n* [doc] Add bitmanip note to README (Greg Chadwick)\n* [doc] Update info on simulators for verification (Greg Chadwick)\n* Update google_riscv-dv to google/riscv-dv@3da32bb (Udi Jonnalagadda)\n* [rtl] Fix performance counter bug (Tom Roberts)\n* [dv] Fixes for disabling forks, for Cadence Xcelium This makes\n changes to support Cadence Xcelium 20.09.001. (CathalMCrevinn)\n* [ibex/dv] Modify EOT ecall check (Udi Jonnalagadda)\n* [rtl] Reduce size of PMP addr CSRs to minimum (Michael Platzer)\n* [rtl] Fix NAPOT address matching (Michael Platzer)\n* [dv] Fix riscv_debug_single_step_test (Greg Chadwick)\n\nSigned-off-by: Tom Roberts \u003ctomroberts@lowrisc.org\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "5820aef1e5a18948cbe56889828371ae2eed760b", "old_mode": 33188, "old_path": "hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv", "new_id": "44f8b0a512f3cae0aefc551220a658b09d60b2fb", "new_mode": 33188, "new_path": "hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv" }, { "type": "modify", "old_id": "02889f8fef5fc1389251ee6ea3f60c220218a2d9", "old_mode": 33188, "old_path": "hw/vendor/lowrisc_ibex.lock.hjson", "new_id": "63cc87966e96805f531c9a6079088bca1ed6ced5", "new_mode": 33188, "new_path": "hw/vendor/lowrisc_ibex.lock.hjson" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": 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