| commit | bbba55462b49f139f013fc804e9fb9999cee7102 | [log] [tgz] |
|---|---|---|
| author | Udi Jonnalagadda <udij@google.com> | Wed Mar 10 02:42:37 2021 -0800 |
| committer | udinator <udij@google.com> | Thu Mar 11 12:01:32 2021 -0800 |
| tree | 1017114da45fd7ab423a3a9d68b828e4b832d940 | |
| parent | da3a0707b397a94406d59973920478ab3a5d52b8 [diff] |
[dv/sram] implement pipelining test and update scb
this PR adds the SRAM pipelining test as laid out in the testplan.
in this test, we choose a random mem address and send a series of
back-to-back transactions to that address, to stress the internal
pipelining and forwarding logic.
this requires an overhaul of the scoreboard as the SRAM pipelining logic
means that while TL memory requests are handled in-order, the underlying
memory macro is updated in an out-of-order fashion, leading to several
tricky edge cases.
NOTE: this PR depends on #5530 to be merged first, as that contains a
fix for an issue uncovered by this test.
Signed-off-by: Udi Jonnalagadda <udij@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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