tree 1017114da45fd7ab423a3a9d68b828e4b832d940
parent da3a0707b397a94406d59973920478ab3a5d52b8
author Udi Jonnalagadda <udij@google.com> 1615372957 -0800
committer udinator <udij@google.com> 1615492892 -0800

[dv/sram] implement pipelining test and update scb

this PR adds the SRAM pipelining test as laid out in the testplan.

in this test, we choose a random mem address and send a series of
back-to-back transactions to that address, to stress the internal
pipelining and forwarding logic.

this requires an overhaul of the scoreboard as the SRAM pipelining logic
means that while TL memory requests are handled in-order, the underlying
memory macro is updated in an out-of-order fashion, leading to several
tricky edge cases.

NOTE: this PR depends on #5530 to be merged first, as that contains a
      fix for an issue uncovered by this test.

Signed-off-by: Udi Jonnalagadda <udij@google.com>