[flash_ctrl,dv] regression fix following regression failures are fixed - flash_ctrl_mp_regions add local function to access local region_cfg db - flash_ctrl_derr_detect reset tb mem model (for last-mile-sb) before multiple test runs increase txn number to guarantee at least one double bit error - flash_ctrl_mid_op_rst remove diable fork having csr thread - Other misc clean up Signed-off-by: Jaedon Kim <jdonjdon@google.com>

diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_connect_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_connect_vseq.sv
index 8e29c63..e31e154 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_connect_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_connect_vseq.sv

@@ -47,9 +47,9 @@
     mystr = {dut_path, ".cio_tdo_o"};
     `DV_CHECK(uvm_hdl_read(mystr, jtag_dst_rsp.tdo))
 
-    // Make non-declared port don't care.x
-    jtag_dst_req.trst_n = jtag_src_req.trst_n;
-    jtag_dst_rsp.tdo_oe = jtag_src_rsp.tdo_oe;
+    // Make non-declared port don't care.
+    jtag_dst_req.trst_n = jtag_src_req.trst_n & lc_nvm_debug_en;
+    jtag_dst_rsp.tdo_oe = jtag_src_rsp.tdo_oe & lc_nvm_debug_en;
 
     `DV_CHECK_EQ(jtag_dst_req, jtag_src_req & {4{lc_nvm_debug_en}})
     `DV_CHECK_EQ(jtag_dst_rsp, jtag_src_rsp & {2{lc_nvm_debug_en}})

diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_derr_detect_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_derr_detect_vseq.sv
index a544e8c..40c33f2 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_derr_detect_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_derr_detect_vseq.sv

@@ -21,7 +21,7 @@
 
     fork
       begin
-        repeat(20) begin
+        repeat(40) begin
           `DV_CHECK_RANDOMIZE_FATAL(this)
           ctrl = rand_op;
           bank = rand_op.addr[OTFBankId];
@@ -37,7 +37,7 @@
         end
       end
       begin
-        for (int i = 0; i < 3; ++i) begin
+        for (int i = 0; i < 4; ++i) begin
           fork
             send_rand_host_rd();
           join_none

diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_intr_rd_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_intr_rd_vseq.sv
index 8f78f1c..72a118d 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_intr_rd_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_intr_rd_vseq.sv

@@ -4,7 +4,7 @@
 
 // Send read only traffic with interrup mode.
 // No protection is applied.
-class flash_ctrl_intr_rd_vseq extends flash_ctrl_otf_base_vseq;
+class flash_ctrl_intr_rd_vseq extends flash_ctrl_legacy_base_vseq;
   `uvm_object_utils(flash_ctrl_intr_rd_vseq)
   `uvm_object_new
 

diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_mid_op_rst_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_mid_op_rst_vseq.sv
index 1e45e80..16f2877 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_mid_op_rst_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_mid_op_rst_vseq.sv

@@ -160,8 +160,7 @@
             csr_wr(.ptr(ral.erase_suspend), .value(1));
             low_ready_h();
           end
-        join_any;
-        disable fork;
+        join
       end : isolation_fork_erase_suspend
     join
     wait_cfg_prog_rd();
@@ -186,11 +185,10 @@
             cfg.clk_rst_vif.wait_clks(19);
             low_ready_h();
           end
-        join_any;
-        disable fork;
+        join
       end : isolation_fork_read
     join
-    wait_cfg_prog_rd();
+   wait_cfg_prog_rd();
 
   endtask : body
 

diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_mp_regions_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_mp_regions_vseq.sv
index 8a521cf..8a15695 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_mp_regions_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_mp_regions_vseq.sv

@@ -4,6 +4,7 @@
 
 // Memory protect test. Overlapping regions with randomization.
 // Send one op among program, read and erase (page) in each trans round.
+// This sequence uses local mp_region db. Don't use cfg.get_region()
 class flash_ctrl_mp_regions_vseq extends flash_ctrl_base_vseq;
   `uvm_object_utils(flash_ctrl_mp_regions_vseq)
 
@@ -257,7 +258,7 @@
       for (int i = 0; i < size; i++) begin
         if  (flash_op.partition == FlashPartData) begin
           page = cfg.addr2page(flash_op.addr);
-          my_region = cfg.get_region(page);
+          my_region = get_region_from_page(page);
         end else begin
           page = cfg.addr2page(flash_op.addr[OTFBankId-1:0]);
           my_region = cfg.get_region_from_info(mp_info_pages[bank][flash_op.partition>>1][page]);
@@ -269,7 +270,7 @@
       if (tail) begin
         if  (flash_op.partition == FlashPartData) begin
           page = cfg.addr2page(flash_op.addr);
-          my_region = cfg.get_region(page);
+          my_region = get_region_from_page(page);
         end else begin
           page = cfg.addr2page(flash_op.otf_addr);
           my_region = cfg.get_region_from_info(mp_info_pages[bank][flash_op.partition>>1][page]);
@@ -281,7 +282,7 @@
     end else begin // if (flash_op.op == FlashOpRead)
       if  (flash_op.partition == FlashPartData) begin
         page = cfg.addr2page(flash_op.addr);
-        my_region = cfg.get_region(page);
+        my_region = get_region_from_page(page);
       end else begin
         page = cfg.addr2page(flash_op.addr[OTFBankId-1:0]);
         my_region = cfg.get_region_from_info(mp_info_pages[bank][flash_op.partition>>1][page]);
@@ -290,8 +291,7 @@
     end
 
     if(illegal_trans) begin
-      cfg.scb_h.exp_alert["recov_err"] = 1;
-      cfg.scb_h.alert_chk_max_delay["recov_err"] = 2000; // cycles
+      set_otf_exp_alert("recov_err");
     end
 
     `uvm_info("do_mp_reg", $sformatf("trans:%0d page:%x region:%0d illegal_trans:%0d",
@@ -391,4 +391,19 @@
     flash_ctrl_bank_erase_cfg(.bank_erase_en(bank_erase_en));
   endtask // configure_flash_protection
 
+  function flash_mp_region_cfg_t get_region_from_page(int page, bit dis = 1);
+    flash_mp_region_cfg_t my_region;
+    if (cfg.p2r_map[page] == 8) begin
+      my_region = cfg.default_region_cfg;
+    end else begin
+      my_region = this.mp_regions[cfg.p2r_map[page]];
+      if (my_region.en != MuBi4True) my_region = cfg.default_region_cfg;
+    end
+    if (dis) begin
+      `uvm_info("get_region_from_page", $sformatf("page:%0d --> region:%0d",
+                                        page, cfg.p2r_map[page]), UVM_MEDIUM)
+    end
+    return my_region;
+  endfunction // get_region_from_page
+
 endclass : flash_ctrl_mp_regions_vseq

diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_otf_base_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_otf_base_vseq.sv
index ca65863..94c5f18 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_otf_base_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_otf_base_vseq.sv

@@ -127,9 +127,9 @@
 
     init_p2r_map();
     `uvm_info("cfg_summary",
-              $sformatf({"flash_init:%s ecc_mode %0d allow_spec_info_acc:%3b",
+              $sformatf({"flash_init:%s ecc_mode %s allow_spec_info_acc:%3b",
                          " scr_ecc_cfg:%s always_read:%0d"},
-                        flash_init.name, cfg.ecc_mode, allow_spec_info_acc,
+                        flash_init.name, cfg.ecc_mode.name, allow_spec_info_acc,
                         scr_ecc_cfg.name, cfg.en_always_read),
               UVM_MEDIUM)
 
@@ -1229,6 +1229,12 @@
     cfg.otf_read_entry.hash.delete();
     foreach (cfg.otf_read_entry.prv_read[i]) cfg.otf_read_entry.prv_read[i] = '{};
     cfg.otf_scb_h.clear_fifos();
+
+    for (int i = 0; i < NumBanks; i++) begin
+      cfg.otf_scb_h.data_mem[i].delete();
+      foreach (cfg.otf_scb_h.info_mem[i][j])
+        cfg.otf_scb_h.info_mem[i][j].delete();
+    end
   endtask // otf_tb_clean_up
 
   // Populate cfg.mp_info with default_info_page_cfg except scr, ecc.

diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_vseq_list.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_vseq_list.sv
index 99b9329..be8d2c4 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_vseq_list.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_vseq_list.sv

@@ -25,8 +25,8 @@
 `include "flash_ctrl_error_mp_vseq.sv"
 `include "flash_ctrl_invalid_op_vseq.sv"
 `include "flash_ctrl_mid_op_rst_vseq.sv"
-`include "flash_ctrl_stress_all_vseq.sv"
 `include "flash_ctrl_otf_base_vseq.sv"
+`include "flash_ctrl_legacy_base_vseq.sv"
 `include "flash_ctrl_wo_vseq.sv"
 `include "flash_ctrl_ro_vseq.sv"
 `include "flash_ctrl_rw_vseq.sv"
@@ -43,8 +43,8 @@
 `include "flash_ctrl_intr_rd_vseq.sv"
 `include "flash_ctrl_intr_wr_vseq.sv"
 `include "flash_ctrl_prog_reset_vseq.sv"
-`include "flash_ctrl_legacy_base_vseq.sv"
 `include "flash_ctrl_rw_evict_vseq.sv"
 `include "flash_ctrl_re_evict_vseq.sv"
 `include "flash_ctrl_oversize_error_vseq.sv"
 `include "flash_ctrl_connect_vseq.sv"
+`include "flash_ctrl_stress_all_vseq.sv"

diff --git a/hw/ip/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson b/hw/ip/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson
index ad69751..38047bb 100644
--- a/hw/ip/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson
+++ b/hw/ip/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson

@@ -45,15 +45,10 @@
     }
   ]
 
-  build_modes: []
-
 // Add additional tops for simulation.
   sim_tops: ["flash_ctrl_bind","flash_ctrl_cov_bind", "sec_cm_prim_onehot_check_bind",
              "sec_cm_prim_count_bind", "sec_cm_prim_sparse_fsm_flop_bind"]
 
-  // Flash Ctrl coverage exclusion.
-  // xcelium_cov_refine_files: ["{proj_root}/hw/ip/flash_ctrl/dv/cov/flash_ctrl_cov.vRefine"]
-
   // Default iterations for all tests - each test entry can override this.
   reseed: 50
 
@@ -289,13 +284,13 @@
     {
       name: flash_ctrl_intr_rd
       uvm_test_seq: flash_ctrl_intr_rd_vseq
-      run_opts: ["+scb_otf_en=1"]
+      run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+en_always_read=1"]
       reseed: 40
     }
     {
       name: flash_ctrl_intr_wr
       uvm_test_seq: flash_ctrl_intr_wr_vseq
-      run_opts: ["+scb_otf_en=1", "+test_timeout_ns=500_000_000"]
+      run_opts: ["+scb_otf_en=1", "+ecc_mode=1", "+test_timeout_ns=500_000_000"]
       reseed: 10
     }
     {