| From db50a1c140933c4c7769a5632b89410b9cb4d1b0 Mon Sep 17 00:00:00 2001 |
| From: Michael Schaffner <msf@google.com> |
| Date: Mon, 16 Dec 2019 18:33:18 -0800 |
| Subject: [PATCH 3/4] Make sure all case statements are unique and have a |
| default |
| |
| --- |
| src/dm_mem.sv | 4 +++- |
| src/dm_sba.sv | 8 ++++---- |
| src/dmi_jtag.sv | 2 +- |
| src/dmi_jtag_tap.sv | 10 ++++------ |
| 4 files changed, 12 insertions(+), 12 deletions(-) |
| |
| diff --git a/src/dm_mem.sv b/src/dm_mem.sv |
| index 49daa38..938e883 100644 |
| --- a/src/dm_mem.sv |
| +++ b/src/dm_mem.sv |
| @@ -137,7 +137,7 @@ module dm_mem #( |
| resume = 1'b0; |
| cmdbusy_o = 1'b1; |
| |
| - case (state_q) |
| + unique case (state_q) |
| Idle: begin |
| cmdbusy_o = 1'b0; |
| if (cmd_valid_i && halted_q_aligned[hartsel] && !unsupported_command) begin |
| @@ -182,6 +182,8 @@ module dm_mem #( |
| state_d = Idle; |
| end |
| end |
| + |
| + default: ; |
| endcase |
| |
| // only signal once that cmd is unsupported so that we can clear cmderr |
| diff --git a/src/dm_sba.sv b/src/dm_sba.sv |
| index 43a6dad..f605088 100644 |
| --- a/src/dm_sba.sv |
| +++ b/src/dm_sba.sv |
| @@ -77,7 +77,7 @@ module dm_sba #( |
| |
| state_d = state_q; |
| |
| - case (state_q) |
| + unique case (state_q) |
| Idle: begin |
| // debugger requested a read |
| if (sbaddress_write_valid_i && sbreadonaddr_i) state_d = Read; |
| @@ -96,7 +96,7 @@ module dm_sba #( |
| req = 1'b1; |
| we = 1'b1; |
| // generate byte enable mask |
| - case (sbaccess_i) |
| + unique case (sbaccess_i) |
| 3'b000: begin |
| be[be_idx] = '1; |
| end |
| @@ -108,7 +108,7 @@ module dm_sba #( |
| else be = '1; |
| end |
| 3'b011: be = '1; |
| - default:; |
| + default: ; |
| endcase |
| if (gnt) state_d = WaitWrite; |
| end |
| @@ -129,7 +129,7 @@ module dm_sba #( |
| end |
| end |
| |
| - default:; |
| + default: state_d = Idle; // catch parasitic state |
| endcase |
| |
| // handle error case |
| diff --git a/src/dmi_jtag.sv b/src/dmi_jtag.sv |
| index 60e67f4..2039e25 100644 |
| --- a/src/dmi_jtag.sv |
| +++ b/src/dmi_jtag.sv |
| @@ -98,7 +98,7 @@ module dmi_jtag #( |
| |
| dmi_req_valid = 1'b0; |
| |
| - case (state_q) |
| + unique case (state_q) |
| Idle: begin |
| // make sure that no error is sticky |
| if (dmi_access && update_dr && (error_q == DMINoError)) begin |
| diff --git a/src/dmi_jtag_tap.sv b/src/dmi_jtag_tap.sv |
| index f8b282a..3d11145 100644 |
| --- a/src/dmi_jtag_tap.sv |
| +++ b/src/dmi_jtag_tap.sv |
| @@ -183,7 +183,7 @@ module dmi_jtag_tap #( |
| dtmcs_select_o = 1'b0; |
| idcode_select = 1'b0; |
| bypass_select = 1'b0; |
| - case (jtag_ir_q) |
| + unique case (jtag_ir_q) |
| BYPASS0: bypass_select = 1'b1; |
| IDCODE: idcode_select = 1'b1; |
| DTMCSR: dtmcs_select_o = 1'b1; |
| @@ -204,7 +204,7 @@ module dmi_jtag_tap #( |
| tdo_mux = jtag_ir_shift_q[0]; |
| // here we are shifting the DR register |
| end else begin |
| - case (jtag_ir_q) // synthesis parallel_case |
| + unique case (jtag_ir_q) |
| IDCODE: tdo_mux = idcode_q[0]; // Reading ID code |
| DTMCSR: tdo_mux = dtmcs_q.version[0]; |
| DMIACCESS: tdo_mux = dmi_tdo_i; // Read from DMI TDO |
| @@ -257,9 +257,7 @@ module dmi_jtag_tap #( |
| // pause_ir = 1'b0; unused |
| update_ir = 1'b0; |
| |
| - // note that tap_state_d does not have a default assignment since the |
| - // case statement is full |
| - case (tap_state_q) |
| + unique case (tap_state_q) |
| TestLogicReset: begin |
| tap_state_d = (tms_i) ? TestLogicReset : RunTestIdle; |
| test_logic_reset_o = 1'b1; |
| @@ -330,7 +328,7 @@ module dmi_jtag_tap #( |
| update_ir = 1'b1; |
| tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle; |
| end |
| - default: ; // can't actually happen |
| + default: ; // can't actually happen since case is full |
| endcase |
| end |
| |
| -- |
| 2.24.1.735.g03f4e72817-goog |
| |
